This adds a device-tree binding document that specifies the properties
used by the Sunxi-Cedurs VPU driver, as well as examples.
Signed-off-by: Paul Kocialkowski
---
.../devicetree/bindings/media/sunxi-cedrus.txt | 58 ++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/sunxi-cedrus.txt
diff --git a/Documentation/devicetree/bindings/media/sunxi-cedrus.txt
b/Documentation/devicetree/bindings/media/sunxi-cedrus.txt
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+Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
+Video Engine (VE) in Allwinner literature.
+
+The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
+from the DRAM base. This requires specific memory allocation and handling.
+
+Required properties:
+- compatible : must be one of the following compatibles:
+ - "allwinner,sun4i-a10-video-engine"
+ - "allwinner,sun5i-a13-video-engine"
+ - "allwinner,sun7i-a20-video-engine"
+ - "allwinner,sun8i-a33-video-engine"
+- reg : register base and length of VE;
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property;
+- clock-names : should contain "ahb", "mod" and "ram" entries;
+- assigned-clocks : list of clocks assigned to the VE;
+- assigned-clocks-rates: list of clock rates for the clocks assigned
to the VE;
+- resets : phandle for reset;
+- interrupts : VE interrupt number;
+- allwinner,sram : SRAM region to use with the VE.
+
+Optional properties:
+- memory-region: CMA pool to use for buffers allocation
instead of the
+ default CMA pool.
+
+Example:
+
+reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+ cma_pool: cma@4a00 {
+ compatible = "shared-dma-pool";
+ size = <0x600>;
+ alloc-ranges = <0x4a00 0x600>;
+ reusable;
+ linux,cma-default;
+ };
+};
+
+video-codec@1c0e000 {
+ compatible = "allwinner,sun7i-a20-video-engine";
+ reg = <0x01c0e000 0x1000>;
+
+ clocks = < CLK_AHB_VE>, < CLK_VE>,
+< CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+
+ assigned-clocks = < CLK_VE>;
+ assigned-clock-rates = <32000>;
+
+ resets = < RST_VE>;
+ interrupts = ;
+ allwinner,sram = <_sram 1>;
+};
--
2.16.3