Re: [PATCH v5 04/16] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
Hi hans, 2018-02-06 21:21 GMT+08:00 Hans Verkuil : > On 12/29/17 08:52, Shunqian Zheng wrote: >> From: Jacob Chen >> >> This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver >> >> Signed-off-by: Jacob Chen >> Signed-off-by: Shunqian Zheng >> Signed-off-by: Tomasz Figa >> --- >> .../media/platform/rockchip/isp1/mipi_dphy_sy.c| 787 >> + >> 1 file changed, 787 insertions(+) >> create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c >> >> diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c >> b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c >> new file mode 100644 >> index 000..9421183 >> --- /dev/null >> +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c >> @@ -0,0 +1,787 @@ >> +/* >> + * Rockchip MIPI Synopsys DPHY driver >> + * >> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. >> + * >> + * This software is available to you under a choice of one of two >> + * licenses. You may choose to be licensed under the terms of the GNU >> + * General Public License (GPL) Version 2, available from the file >> + * COPYING in the main directory of this source tree, or the >> + * OpenIB.org BSD license below: >> + * >> + * Redistribution and use in source and binary forms, with or >> + * without modification, are permitted provided that the following >> + * conditions are met: >> + * >> + * - Redistributions of source code must retain the above >> + *copyright notice, this list of conditions and the following >> + *disclaimer. >> + * >> + * - Redistributions in binary form must reproduce the above >> + *copyright notice, this list of conditions and the following >> + *disclaimer in the documentation and/or other materials >> + *provided with the distribution. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS >> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN >> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN >> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE >> + * SOFTWARE. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define RK3288_GRF_SOC_CON6 0x025c >> +#define RK3288_GRF_SOC_CON8 0x0264 >> +#define RK3288_GRF_SOC_CON9 0x0268 >> +#define RK3288_GRF_SOC_CON10 0x026c >> +#define RK3288_GRF_SOC_CON14 0x027c >> +#define RK3288_GRF_SOC_STATUS21 0x02d4 >> +#define RK3288_GRF_IO_VSEL 0x0380 >> +#define RK3288_GRF_SOC_CON15 0x03a4 >> + >> +#define RK3399_GRF_SOC_CON9 0x6224 >> +#define RK3399_GRF_SOC_CON21 0x6254 >> +#define RK3399_GRF_SOC_CON22 0x6258 >> +#define RK3399_GRF_SOC_CON23 0x625c >> +#define RK3399_GRF_SOC_CON24 0x6260 >> +#define RK3399_GRF_SOC_CON25 0x6264 >> +#define RK3399_GRF_SOC_STATUS1 0xe2a4 >> + >> +#define CLOCK_LANE_HS_RX_CONTROL 0x34 >> +#define LANE0_HS_RX_CONTROL 0x44 >> +#define LANE1_HS_RX_CONTROL 0x54 >> +#define LANE2_HS_RX_CONTROL 0x84 >> +#define LANE3_HS_RX_CONTROL 0x94 >> +#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75 >> + >> +#define HIWORD_UPDATE(val, mask, shift) \ >> + ((val) << (shift) | (mask) << ((shift) + 16)) >> + >> +enum mipi_dphy_sy_pads { >> + MIPI_DPHY_SY_PAD_SINK = 0, >> + MIPI_DPHY_SY_PAD_SOURCE, >> + MIPI_DPHY_SY_PADS_NUM, >> +}; >> + >> +enum dphy_reg_id { >> + GRF_DPHY_RX0_TURNDISABLE = 0, >> + GRF_DPHY_RX0_FORCERXMODE, >> + GRF_DPHY_RX0_FORCETXSTOPMODE, >> + GRF_DPHY_RX0_ENABLE, >> + GRF_DPHY_RX0_TESTCLR, >> + GRF_DPHY_RX0_TESTCLK, >> + GRF_DPHY_RX0_TESTEN, >> + GRF_DPHY_RX0_TESTDIN, >> + GRF_DPHY_RX0_TURNREQUEST, >> + GRF_DPHY_RX0_TESTDOUT, >> + GRF_DPHY_TX0_TURNDISABLE, >> + GRF_DPHY_TX0_FORCERXMODE, >> + GRF_DPHY_TX0_FORCETXSTOPMODE, >> + GRF_DPHY_TX0_TURNREQUEST, >> + GRF_DPHY_TX1RX1_TURNDISABLE, >> + GRF_DPHY_TX1RX1_FORCERXMODE, >> + GRF_DPHY_TX1RX1_FORCETXSTOPMODE, >> + GRF_DPHY_TX1RX1_ENABLE, >> + GRF_DPHY_TX1RX1_MASTERSLAVEZ, >> + GRF_DPHY_TX1RX1_BASEDIR, >> + GRF_DPHY_TX1RX1_ENABLECLK, >> + GRF_DPHY_TX1RX1_TURNREQUEST, >> + GRF_DPHY_RX1_SRC_SEL, >> + /* rk3288 only */ >> + GRF_CON_DISABLE_ISP, >> + GRF_CON_ISP_DPHY_SEL, >> + GRF_DSI_CSI_TESTBUS_SEL, >> + GRF_DVP_V18SEL, >> + /* below is for rk3399 only */ >> + GRF_DPHY_RX0_CLK_INV_SEL, >> + GRF_DPHY_RX1_CLK_INV_SEL, >> +}; >> + >> +struct dphy_reg { >> + u32 offset; >> + u32 mask; >> + u32 shift; >> +}; >> + >> +#define PHY_REG(_offset, _widt
Re: [PATCH v5 04/16] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
On 12/29/17 08:52, Shunqian Zheng wrote: > From: Jacob Chen > > This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver > > Signed-off-by: Jacob Chen > Signed-off-by: Shunqian Zheng > Signed-off-by: Tomasz Figa > --- > .../media/platform/rockchip/isp1/mipi_dphy_sy.c| 787 > + > 1 file changed, 787 insertions(+) > create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > > diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > new file mode 100644 > index 000..9421183 > --- /dev/null > +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > @@ -0,0 +1,787 @@ > +/* > + * Rockchip MIPI Synopsys DPHY driver > + * > + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. > + * > + * This software is available to you under a choice of one of two > + * licenses. You may choose to be licensed under the terms of the GNU > + * General Public License (GPL) Version 2, available from the file > + * COPYING in the main directory of this source tree, or the > + * OpenIB.org BSD license below: > + * > + * Redistribution and use in source and binary forms, with or > + * without modification, are permitted provided that the following > + * conditions are met: > + * > + * - Redistributions of source code must retain the above > + *copyright notice, this list of conditions and the following > + *disclaimer. > + * > + * - Redistributions in binary form must reproduce the above > + *copyright notice, this list of conditions and the following > + *disclaimer in the documentation and/or other materials > + *provided with the distribution. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS > + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN > + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE > + * SOFTWARE. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RK3288_GRF_SOC_CON6 0x025c > +#define RK3288_GRF_SOC_CON8 0x0264 > +#define RK3288_GRF_SOC_CON9 0x0268 > +#define RK3288_GRF_SOC_CON10 0x026c > +#define RK3288_GRF_SOC_CON14 0x027c > +#define RK3288_GRF_SOC_STATUS21 0x02d4 > +#define RK3288_GRF_IO_VSEL 0x0380 > +#define RK3288_GRF_SOC_CON15 0x03a4 > + > +#define RK3399_GRF_SOC_CON9 0x6224 > +#define RK3399_GRF_SOC_CON21 0x6254 > +#define RK3399_GRF_SOC_CON22 0x6258 > +#define RK3399_GRF_SOC_CON23 0x625c > +#define RK3399_GRF_SOC_CON24 0x6260 > +#define RK3399_GRF_SOC_CON25 0x6264 > +#define RK3399_GRF_SOC_STATUS1 0xe2a4 > + > +#define CLOCK_LANE_HS_RX_CONTROL 0x34 > +#define LANE0_HS_RX_CONTROL 0x44 > +#define LANE1_HS_RX_CONTROL 0x54 > +#define LANE2_HS_RX_CONTROL 0x84 > +#define LANE3_HS_RX_CONTROL 0x94 > +#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75 > + > +#define HIWORD_UPDATE(val, mask, shift) \ > + ((val) << (shift) | (mask) << ((shift) + 16)) > + > +enum mipi_dphy_sy_pads { > + MIPI_DPHY_SY_PAD_SINK = 0, > + MIPI_DPHY_SY_PAD_SOURCE, > + MIPI_DPHY_SY_PADS_NUM, > +}; > + > +enum dphy_reg_id { > + GRF_DPHY_RX0_TURNDISABLE = 0, > + GRF_DPHY_RX0_FORCERXMODE, > + GRF_DPHY_RX0_FORCETXSTOPMODE, > + GRF_DPHY_RX0_ENABLE, > + GRF_DPHY_RX0_TESTCLR, > + GRF_DPHY_RX0_TESTCLK, > + GRF_DPHY_RX0_TESTEN, > + GRF_DPHY_RX0_TESTDIN, > + GRF_DPHY_RX0_TURNREQUEST, > + GRF_DPHY_RX0_TESTDOUT, > + GRF_DPHY_TX0_TURNDISABLE, > + GRF_DPHY_TX0_FORCERXMODE, > + GRF_DPHY_TX0_FORCETXSTOPMODE, > + GRF_DPHY_TX0_TURNREQUEST, > + GRF_DPHY_TX1RX1_TURNDISABLE, > + GRF_DPHY_TX1RX1_FORCERXMODE, > + GRF_DPHY_TX1RX1_FORCETXSTOPMODE, > + GRF_DPHY_TX1RX1_ENABLE, > + GRF_DPHY_TX1RX1_MASTERSLAVEZ, > + GRF_DPHY_TX1RX1_BASEDIR, > + GRF_DPHY_TX1RX1_ENABLECLK, > + GRF_DPHY_TX1RX1_TURNREQUEST, > + GRF_DPHY_RX1_SRC_SEL, > + /* rk3288 only */ > + GRF_CON_DISABLE_ISP, > + GRF_CON_ISP_DPHY_SEL, > + GRF_DSI_CSI_TESTBUS_SEL, > + GRF_DVP_V18SEL, > + /* below is for rk3399 only */ > + GRF_DPHY_RX0_CLK_INV_SEL, > + GRF_DPHY_RX1_CLK_INV_SEL, > +}; > + > +struct dphy_reg { > + u32 offset; > + u32 mask; > + u32 shift; > +}; > + > +#define PHY_REG(_offset, _width, _shift) \ > + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } > + > +static const struct dphy_reg rk3399_grf_dphy_regs[] = { > + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG
Re: [PATCH v5 04/16] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
On 12/29/17 08:52, Shunqian Zheng wrote: > From: Jacob Chen > > This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver > > Signed-off-by: Jacob Chen > Signed-off-by: Shunqian Zheng > Signed-off-by: Tomasz Figa > --- > .../media/platform/rockchip/isp1/mipi_dphy_sy.c| 787 > + > 1 file changed, 787 insertions(+) > create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > > diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > new file mode 100644 > index 000..9421183 > --- /dev/null > +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c > @@ -0,0 +1,787 @@ > +/* > + * Rockchip MIPI Synopsys DPHY driver > + * > + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. > + * > + * This software is available to you under a choice of one of two > + * licenses. You may choose to be licensed under the terms of the GNU > + * General Public License (GPL) Version 2, available from the file > + * COPYING in the main directory of this source tree, or the > + * OpenIB.org BSD license below: > + * > + * Redistribution and use in source and binary forms, with or > + * without modification, are permitted provided that the following > + * conditions are met: > + * > + * - Redistributions of source code must retain the above > + *copyright notice, this list of conditions and the following > + *disclaimer. > + * > + * - Redistributions in binary form must reproduce the above > + *copyright notice, this list of conditions and the following > + *disclaimer in the documentation and/or other materials > + *provided with the distribution. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS > + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN > + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE > + * SOFTWARE. If possible, please use the new SPDX license tags. Hmm, you used it elsewhere, so why not here? > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RK3288_GRF_SOC_CON6 0x025c > +#define RK3288_GRF_SOC_CON8 0x0264 > +#define RK3288_GRF_SOC_CON9 0x0268 > +#define RK3288_GRF_SOC_CON10 0x026c > +#define RK3288_GRF_SOC_CON14 0x027c > +#define RK3288_GRF_SOC_STATUS21 0x02d4 > +#define RK3288_GRF_IO_VSEL 0x0380 > +#define RK3288_GRF_SOC_CON15 0x03a4 > + > +#define RK3399_GRF_SOC_CON9 0x6224 > +#define RK3399_GRF_SOC_CON21 0x6254 > +#define RK3399_GRF_SOC_CON22 0x6258 > +#define RK3399_GRF_SOC_CON23 0x625c > +#define RK3399_GRF_SOC_CON24 0x6260 > +#define RK3399_GRF_SOC_CON25 0x6264 > +#define RK3399_GRF_SOC_STATUS1 0xe2a4 > + > +#define CLOCK_LANE_HS_RX_CONTROL 0x34 > +#define LANE0_HS_RX_CONTROL 0x44 > +#define LANE1_HS_RX_CONTROL 0x54 > +#define LANE2_HS_RX_CONTROL 0x84 > +#define LANE3_HS_RX_CONTROL 0x94 > +#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75 > + > +#define HIWORD_UPDATE(val, mask, shift) \ > + ((val) << (shift) | (mask) << ((shift) + 16)) > + > +enum mipi_dphy_sy_pads { > + MIPI_DPHY_SY_PAD_SINK = 0, > + MIPI_DPHY_SY_PAD_SOURCE, > + MIPI_DPHY_SY_PADS_NUM, > +}; > + > +enum dphy_reg_id { > + GRF_DPHY_RX0_TURNDISABLE = 0, > + GRF_DPHY_RX0_FORCERXMODE, > + GRF_DPHY_RX0_FORCETXSTOPMODE, > + GRF_DPHY_RX0_ENABLE, > + GRF_DPHY_RX0_TESTCLR, > + GRF_DPHY_RX0_TESTCLK, > + GRF_DPHY_RX0_TESTEN, > + GRF_DPHY_RX0_TESTDIN, > + GRF_DPHY_RX0_TURNREQUEST, > + GRF_DPHY_RX0_TESTDOUT, > + GRF_DPHY_TX0_TURNDISABLE, > + GRF_DPHY_TX0_FORCERXMODE, > + GRF_DPHY_TX0_FORCETXSTOPMODE, > + GRF_DPHY_TX0_TURNREQUEST, > + GRF_DPHY_TX1RX1_TURNDISABLE, > + GRF_DPHY_TX1RX1_FORCERXMODE, > + GRF_DPHY_TX1RX1_FORCETXSTOPMODE, > + GRF_DPHY_TX1RX1_ENABLE, > + GRF_DPHY_TX1RX1_MASTERSLAVEZ, > + GRF_DPHY_TX1RX1_BASEDIR, > + GRF_DPHY_TX1RX1_ENABLECLK, > + GRF_DPHY_TX1RX1_TURNREQUEST, > + GRF_DPHY_RX1_SRC_SEL, > + /* rk3288 only */ > + GRF_CON_DISABLE_ISP, > + GRF_CON_ISP_DPHY_SEL, > + GRF_DSI_CSI_TESTBUS_SEL, > + GRF_DVP_V18SEL, > + /* below is for rk3399 only */ > + GRF_DPHY_RX0_CLK_INV_SEL, > + GRF_DPHY_RX1_CLK_INV_SEL, > +}; > + > +struct dphy_reg { > + u32 offset; > + u32 mask; > + u32 shift; > +}; > + > +#define PHY_REG(_offset, _width, _shift) \ > + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } > + > +st