[PATCH v2 03/16] clk: tz1090: add mux bank clock driver

Add a clock driver for banks of clock muxes in the TZ1090 SoC. A single 32 bit register controls up to 32 separate clock muxes. The generic clock mux clock operations are wrapped in order to acquire and release the Meta global exclusive lock (__global_lock2) to ensure atomicity with other non-Linux

[PATCH v2 01/16] clk: tz1090: add clock provider common code

Add some common code for the TZ1090 SoC to allocate and register onecell based clock providers. These have some memory mapped registers and are instantiated from DT. Also provided is a tz1090_clk_xlate() function to help handle external clocks from other clock providers by processing the internal

[PATCH v2 02/16] clk: tz1090: add gate bank clock driver

Add a clock driver for banks of clock gates in the TZ1090 SoC. A single 32 bit register controls up to 32 separate clock gates. The generic clock gate clock operations are wrapped in order to acquire and release the Meta global exclusive lock (__global_lock2) to ensure atomicity with other non-Linu

[PATCH v2 04/16] clk: tz1090: add deleter clock driver

Add a clock driver for clock deleters in the TZ1090 SoC, which delete up to 1023 out of every 1024 clock pulses. There are 4 of these in TZ1090, for the system clock, the Meta core clock, and one for each UCC. The tz1090_clk_register_deleters() helper function can be used to register a set of dele

[PATCH v2 05/16] clk: tz1090: add divider clock driver

Add a clock driver for dividers in the TZ1090 SoC, which divide an input clock by an integer. The generic divider operations are optionally wrapped in order to acquire and release the Meta global exclusive lock (__global_lock2) to ensure atomicity with other non-Linux cores and threads which may ne

[PATCH v2 07/16] dt: binding: add binding for TZ1090 PDC clocks

The TZ1090 PDC (PowerDown Controller) has a couple of clock components in order to generate its main 32.768KHz clock which the peripherals in the low power domain run off, especially while the SoC is otherwise powered down. Create a clock binding for the provider of these clocks, and a header file

[PATCH v2 06/16] clk: tz1090: add PLL clock driver

Add a clock driver for the main PLLs in the TZ1090 SoC, the system PLL and the ADC PLL. The system PLL is used to derive the core Meta clock, the DDR clock, and the system clock. The ADC PLL can be used for various purposes, but is usually used for the pixel clock. The PLL is a True Circuits PLL,

[PATCH v2 08/16] clk: tz1090: add PDC clock provider driver

The TZ1090 PDC (PowerDown Controller) has a couple of clock components in order to generate its main 32.768KHz clock which the peripherals in the low power domain run off, especially while the SoC is otherwise powered down. It is generated either directly from the XTAL3 clock or by dividing the XT

[PATCH v2 09/16] dt: binding: add binding for TZ1090 TOP clocks

The TZ1090 top level register region controls the majority of the SoC's clocking infrastructure. Create a clock binding for the provider of these clocks, and a header file in for enumerating the provided clocks. There are a variety of clocks provided, including from muxes, gates, deleters, divid

[PATCH v2 13/16] dt: binding: add binding for TZ1090 PERIP clocks

The TZ1090 peripheral (PERIP) register region controls a bank of system clock gates for individual peripherals. Create a clock binding for the provider of these clocks, and a header file in for enumerating the provided clocks. There is a single input clock, the main system clock, and multiple pe

[PATCH v2 10/16] clk: tz1090: add TOP clock provider driver

The TZ1090 top level register region controls the majority of the SoC's clocking infrastructure. Most of the complexity comes from the description of the 2 main banks of clock muxes (TOP_CLKSWITCH, TOP_CLKSWITCH2), with 2 banks of clock gates (TOP_CLKENAB, TOP_CLKENAB2) which roughly speaking gate

[PATCH v2 14/16] clk: tz1090: add PERIP clock provider driver

The TZ1090 peripheral (PERIP) register region controls a bank of system clock gates for individual peripherals. The set up is pretty straight forward, with only a clock gate bank (PERIP_CLKEN) needing to be configured, with all the gates using the same external system clock as input. Signed-off-b

[PATCH v2 12/16] clk: tz1090: add HEP clock provider driver

The TZ1090 High End Peripheral (HEP) register region controls several clocks for the HEP peripherals. The set up is pretty straight forward, with only a clock gate bank (HEP_CLK_EN) needing to be configured. Signed-off-by: James Hogan Cc: Mike Turquette Cc: linux-metag@vger.kernel.org --- Chang

[PATCH v2 11/16] dt: binding: add binding for TZ1090 HEP clocks

The TZ1090 High End Peripheral (HEP) register region controls several clocks for the HEP peripherals. Create a clock binding for the provider of these clocks, and a header file in for enumerating the provided clocks. There are 3 clocks provided, the 2D block clock, the PDP/PDI clocks, and the DD

[PATCH v2 16/16] metag: tz1090: connect Meta core clock

Connect the Meta core clock to the root DT node so that the precise rate of the Meta timer can be determined. Signed-off-by: James Hogan Cc: Mike Turquette Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: linux-metag@vger.kernel.org Cc: devicet...@vger.ker

[PATCH v2 15/16] metag: tz1090: add TZ1090 clocks to device tree

Enable the common clock framework for the TZ1090 SoC, and add a tz1090_clk device tree file instantiating and connecting together the clock providers. Most of the clock graph is represented, apart from the AFE output clocks which aren't usually of much interest to Linux. These are represented with

[PATCH v2 00/16] tz1090: add clock components

This patchset adds common clock framework support for the TZ1090 SoC. Patch 1 adds common code to simplify TZ1090 clock providers. Patches 2 to 6 add TZ1090 clock types, specifically: * Gate banks (a register containing clock gate bits) * Mux banks (a register containing clock mux bits) * Clock d