On Tue, 2018-06-05 at 19:07 -0700, Dan Williams wrote:
> On Tue, Jun 5, 2018 at 5:00 PM, Vishal Verma
> wrote:
> > The ARS status command defines a 'flags' field that wasn't being
> > exposed
> > via an API yet. Add a new ndctl_cmd_ars_get_flags() helper to retrieve
> > this field.
> >
> >
On Tue, Jun 5, 2018 at 5:00 PM, Vishal Verma wrote:
> The ARS status command defines a 'flags' field that wasn't being exposed
> via an API yet. Add a new ndctl_cmd_ars_get_flags() helper to retrieve
> this field.
>
> Reported-by: Jacek Zloch
> Cc: Dan Williams
> Signed-off-by: Vishal Verma
On Tue, Jun 5, 2018 at 4:58 PM, Ross Zwisler
wrote:
> This commit:
>
> 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
>
> intended to make sure that deep flush was always available even on
> platforms which support a power-fail protected CPU cache. An unintended
>
> Hi,
>
> >
> > > I'm investigating status of vNVDIMM on qemu/KVM,
> > > and I have some questions about it. I'm glad if anyone answer them.
> > >
> > > In my understanding, qemu/KVM has a feature to show NFIT for guest,
> > > and it will be still updated about platform capability with this
The ARS status command defines a 'flags' field that wasn't being exposed
via an API yet. Add a new ndctl_cmd_ars_get_flags() helper to retrieve
this field.
Reported-by: Jacek Zloch
Cc: Dan Williams
Signed-off-by: Vishal Verma
---
ndctl/lib/ars.c| 10 ++
ndctl/lib/libndctl.sym
The APIs that iterate over the information contained in an ars_atatus
command require a prior, successfully completed ars_status command
struct. We were neglecting to verify that the firmware status too
indicates a success. We were also incorrectly requiring that
ars_status->status be zero, where
Prior to this commit we would only do a "deep flush" in response to an
msync/fsync/sync call if the nvdimm_has_cache() returned true at the time
we were setting up the request queue. This happens due to the write cache
value passed in to blk_queue_write_cache(). We do have a "write_cache"
sysfs
This commit:
5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
intended to make sure that deep flush was always available even on
platforms which support a power-fail protected CPU cache. An unintended
side effect of this change was that we also lost the ability to
Use dax_write_cache() and dax_write_cache_enabled() instead of open coding
the bit operations.
Signed-off-by: Ross Zwisler
---
drivers/dax/super.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/dax/super.c b/drivers/dax/super.c
index
On Tue, Jun 5, 2018 at 3:07 PM, Ross Zwisler
wrote:
> On Tue, Jun 05, 2018 at 09:37:25PM +0300, Michael S. Tsirkin wrote:
>> On Tue, Jun 05, 2018 at 11:15:00AM -0700, Dan Williams wrote:
>> > On Tue, Jun 5, 2018 at 9:42 AM, Ross Zwisler
>> > wrote:
>> > > On Tue, Jun 05, 2018 at 06:25:27PM
On Tue, Jun 5, 2018 at 2:59 PM, Ross Zwisler
wrote:
> On Tue, Jun 05, 2018 at 02:20:38PM -0700, Dan Williams wrote:
>> On Tue, Jun 5, 2018 at 1:58 PM, Ross Zwisler
>> wrote:
>> > This commit:
>> >
>> > 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via
>> > fsync()")
>> >
>> >
On Tue, Jun 05, 2018 at 09:37:25PM +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 05, 2018 at 11:15:00AM -0700, Dan Williams wrote:
> > On Tue, Jun 5, 2018 at 9:42 AM, Ross Zwisler
> > wrote:
> > > On Tue, Jun 05, 2018 at 06:25:27PM +0300, Michael S. Tsirkin wrote:
> > >> On Mon, May 21, 2018 at
On Tue, Jun 05, 2018 at 02:20:38PM -0700, Dan Williams wrote:
> On Tue, Jun 5, 2018 at 1:58 PM, Ross Zwisler
> wrote:
> > This commit:
> >
> > 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via
> > fsync()")
> >
> > intended to make sure that deep flush was always available even
On Tue, Jun 5, 2018 at 1:58 PM, Ross Zwisler
wrote:
> This commit:
>
> 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
>
> intended to make sure that deep flush was always available even on
> platforms which support a power-fail protected CPU cache. An unintended
>
Use dax_write_cache() and dax_write_cache_enabled() instead of open coding
the bit operations.
Signed-off-by: Ross Zwisler
---
drivers/dax/super.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/dax/super.c b/drivers/dax/super.c
index
This commit:
5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
intended to make sure that deep flush was always available even on
platforms which support a power-fail protected CPU cache. An unintended
side effect of this change was that we also lost the ability to
On Tue, Jun 5, 2018 at 7:01 AM, Andrey Ryabinin wrote:
>
>
> On 06/05/2018 07:22 AM, Dan Williams wrote:
>> On Mon, Jun 4, 2018 at 8:32 PM, Dan Williams
>> wrote:
>>> [ adding KASAN devs...]
>>>
>>> On Mon, Jun 4, 2018 at 4:40 PM, Dan Williams
>>> wrote:
On Sun, Jun 3, 2018 at 6:48 PM,
On Tue, Jun 05, 2018 at 11:15:00AM -0700, Dan Williams wrote:
> On Tue, Jun 5, 2018 at 9:42 AM, Ross Zwisler
> wrote:
> > On Tue, Jun 05, 2018 at 06:25:27PM +0300, Michael S. Tsirkin wrote:
> >> On Mon, May 21, 2018 at 10:32:02AM -0600, Ross Zwisler wrote:
> >> > Add a machine command line option
On Tue, Jun 5, 2018 at 9:42 AM, Ross Zwisler
wrote:
> On Tue, Jun 05, 2018 at 06:25:27PM +0300, Michael S. Tsirkin wrote:
>> On Mon, May 21, 2018 at 10:32:02AM -0600, Ross Zwisler wrote:
>> > Add a machine command line option to allow the user to control the Platform
>> > Capabilities Structure
On Tue, Jun 05, 2018 at 06:25:27PM +0300, Michael S. Tsirkin wrote:
> On Mon, May 21, 2018 at 10:32:02AM -0600, Ross Zwisler wrote:
> > Add a machine command line option to allow the user to control the Platform
> > Capabilities Structure in the virtualized NFIT. This Platform Capabilities
> >
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On Mon, May 21, 2018 at 10:32:02AM -0600, Ross Zwisler wrote:
> Add a machine command line option to allow the user to control the Platform
> Capabilities Structure in the virtualized NFIT. This Platform Capabilities
> Structure was added in ACPI 6.2 Errata A.
>
> Signed-off-by: Ross Zwisler
I
On Tue, Jun 5, 2018 at 7:11 AM, Michal Hocko wrote:
> On Mon 04-06-18 07:31:25, Dan Williams wrote:
> [...]
>> I'm trying to solve this real world problem when real poison is
>> consumed through a dax mapping:
>>
>> mce: Uncorrected hardware memory error in user-access at af34214200
>>
On Mon 04-06-18 07:31:25, Dan Williams wrote:
[...]
> I'm trying to solve this real world problem when real poison is
> consumed through a dax mapping:
>
> mce: Uncorrected hardware memory error in user-access at af34214200
> {1}[Hardware Error]: It has been corrected by h/w and
On 06/05/2018 07:22 AM, Dan Williams wrote:
> On Mon, Jun 4, 2018 at 8:32 PM, Dan Williams wrote:
>> [ adding KASAN devs...]
>>
>> On Mon, Jun 4, 2018 at 4:40 PM, Dan Williams
>> wrote:
>>> On Sun, Jun 3, 2018 at 6:48 PM, Dan Williams
>>> wrote:
On Sun, Jun 3, 2018 at 5:25 PM, Dave
On Tue, Jun 5, 2018 at 6:22 AM, Dan Williams wrote:
> On Mon, Jun 4, 2018 at 8:32 PM, Dan Williams wrote:
>> [ adding KASAN devs...]
>>
>> On Mon, Jun 4, 2018 at 4:40 PM, Dan Williams
>> wrote:
>>> On Sun, Jun 3, 2018 at 6:48 PM, Dan Williams
>>> wrote:
On Sun, Jun 3, 2018 at 5:25 PM,
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