On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
is available to enable Alarm Wakeup feature. This register needs to be
properly handled for the rtcwake to work properly.
Platforms using such IP should set ti,am3352-rtc in rtc
On Tue, Jul 02, 2013 at 11:32:34, Nori, Sekhar wrote:
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
is available to enable Alarm Wakeup feature. This register needs to be
properly handled for the rtcwake to work properly.
On 7/2/2013 11:34 AM, Hebbar, Gururaja wrote:
On Tue, Jul 02, 2013 at 11:32:34, Nori, Sekhar wrote:
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
is available to enable Alarm Wakeup feature. This register needs to be
properly
On Tue, Jul 02, 2013 at 11:39:28, Nori, Sekhar wrote:
On 7/2/2013 11:34 AM, Hebbar, Gururaja wrote:
On Tue, Jul 02, 2013 at 11:32:34, Nori, Sekhar wrote:
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
On some platforms (like AM33xx), a special register (RTC_IRQWAKEEN)
is available to enable
Changing to Benoit's gmail id since he apparently wont access TI mail
anymore.
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has RTC_IRQWAKEEN to support Alarm Wake-up.
Update the rtc compatible property to ti,am3352-rtc to enable handling
of this feature inside rtc-omap
On Tue, Jul 02, 2013 at 11:42:49, Nori, Sekhar wrote:
Changing to Benoit's gmail id since he apparently wont access TI mail
anymore.
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has RTC_IRQWAKEEN to support Alarm Wake-up.
Update the rtc compatible property to
On 7/2/2013 11:41 AM, Hebbar, Gururaja wrote:
On Tue, Jul 02, 2013 at 11:39:28, Nori, Sekhar wrote:
On 7/2/2013 11:34 AM, Hebbar, Gururaja wrote:
On Tue, Jul 02, 2013 at 11:32:34, Nori, Sekhar wrote:
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
On some platforms (like AM33xx), a special
On 07/02/2013 01:23 AM, Kevin Hilman wrote:
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
When an OMAP GPIO is used as an IRQ line, a call to gpio_request()
has to be made to initialize the OMAP GPIO bank before a driver
request the IRQ. Otherwise the call to request_irq()
On Tue, Jul 02, 2013 at 11:42:49, Nori, Sekhar wrote:
Changing to Benoit's gmail id since he apparently wont access TI mail
anymore.
On 6/28/2013 3:05 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has RTC_IRQWAKEEN to support Alarm Wake-up.
Update the rtc compatible property to
On 7/2/2013 9:44 AM, Gupta, Pekon wrote:
This does not apply to l2-mtd.git, could you please re-base?
[Pekon]: rebased to l2-mtd.git
- updated [Patch 3/4] which conflicted with commit '26331c04' which
touched omap2.c.
- Please ignore [Patch 4/4] as it’s a DT update, which adds on top of
On 07/02/2013 12:01 AM, Alan Stern wrote:
On Mon, 1 Jul 2013, Felipe Balbi wrote:
I don't know what Pad wakeup is. The wakeup signal has to originate
from the EHCI controller, doesn't it? If not, how does the Pad know
when a wakeup is needed?
That's really an OMAP thing, I guess. Pad
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will
Hi,
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON)+= spi-octeon.o
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
Does this hardware really support anything other than 8 bits per word?
There is no code in the driver which pays any
Hello Grant,
-Original Message-
From: J, KEERTHY
Sent: Thursday, June 27, 2013 10:05 AM
To: grant.lik...@secretlab.ca
Cc: broo...@kernel.org; ldewan...@nvidia.com; sa...@linux.intel.com;
swar...@nvidia.com; linux-ker...@vger.kernel.org; linux-
d...@vger.kernel.org;
Hello Grant,
-Original Message-
From: J, KEERTHY
Sent: Thursday, June 27, 2013 10:03 AM
To: grant.lik...@secretlab.ca
Cc: broo...@kernel.org; ldewan...@nvidia.com; sa...@linux.intel.com;
swar...@nvidia.com; linux-ker...@vger.kernel.org; linux-
d...@vger.kernel.org;
Hi,
On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote:
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
Does this hardware really support anything other than
Hi Felipe,
On Tuesday 02 July 2013 02:54 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi-master);
+
+ int clk_div;
+
+ if (!qspi-spi_max_frequency)
+
On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote:
Does this hardware really support anything other than 8 bits per word?
There is no code in the driver which pays any attention to the word
size...
the HW has a
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi-master);
+
+ int
Hi Mark,
On Tuesday 02 July 2013 03:47 PM, Mark Brown wrote:
On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote:
Does this hardware really support anything other than 8 bits per word?
There is no code in the driver which
Hi,
On Tue, Jul 02, 2013 at 03:53:49PM +0530, Sourav Poddar wrote:
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+
On Tuesday 02 July 2013 04:01 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:53:49PM +0530, Sourav Poddar wrote:
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device
On Tue, Jul 02, 2013 at 11:17:18AM +0100, Mark Brown wrote:
On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote:
Does this hardware really support anything other than 8 bits per word?
There is no code in the driver
On 7/2/2013 2:26 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data
Hi Sekhar,
On Tuesday 02 July 2013 04:27 PM, Sekhar Nori wrote:
On 7/2/2013 2:26 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped
On Tue, Jul 02, 2013 at 01:43:38PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 11:17:18AM +0100, Mark Brown wrote:
+ /* setup command reg */
+ qspi-cmd = 0;
+ qspi-cmd |= QSPI_WLEN(8);
Sourav hardcodes wordlenght to 8-bits, and yet he enables 8, 16 and
32-bits per word.
With all the minor issues addressed in previous patches
we can now safely migrate over AM335x to OMAP4 APIs and
get rid of the AM335x version of the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 7 ++
arch/arm/mach-omap2/io.c | 3 +
Even though there are differences in the PRCM features on different
TI SoCs (mostly OMAP3+) the underlying PRCM architecture is similar
on OMAP4+, AM335x, AM437x (and DM81xx). With some rework of the OMAP4
APIs we can easily consolidate the low level PRM/CM APIs for these
SoCs and cut down 800+
Commit 65aa94b (ARM: OMAP4: clockdomain/CM code: Update supported transition
modes)
removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not having
SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the way of other
devices like AM335x which have the same hardware underneath
Reset status bits on AM335x have different masks and register
is not consistent across powerdomains. Generalize the OMAP4
reset handling code to take care of these.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 7 +++
Now that we have migrated AM335x over to use OMAP4 style
PRM, CM APIs we can delete the custom APIs
To avoid build breakage the reset function is reimplemented
in the same patch.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/Makefile | 3 +-
Instead of hardcoded offsets of PWRSTCTRL and PWRSTST
use the offsets from the pwrdomain data. This helps
us in reusing the same code across OMAP4 and AM335x.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 30 --
1 file changed,
OMAP4 style PRM, CM APIs expect the pwrdomains to specify a
prcm_partition. Introduce a PRCM_PARTITION for the AM335x
pwrdomains so that we can eventually consolidate the code.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/powerdomains33xx_data.c | 6 ++
OMAP4 style PRM, CM APIs expect the clkdomains to specify a
cm_inst. Introduce a CM_INST for the AM335x clkdomains so that
we can eventually consolidate the code.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/clockdomains33xx_data.c | 18 ++
OMAP4 powerdomains have a consistent register layout
and so far the pwrstctrl and pwrstst offsets were
hardcoded in the lowlevel APIs.
AM335x powerdomains don't have a consistent register
layout and hence the offsets used in the lowlevel APIs
need to be removed. As part of the AM335x work two
AM335x which will migrate to the OMAP4 APIs in subsequent patches
has one CLKCTRL at offset 0. A similar check existed in the AM335x
custom APIs and that was removed to fix a crash on boot in commit
169c82a (ARM: OMAP2: am33xx-hwmod: Fix register offset NULL check bug).
Do the same in the OMAP4
(+ CC: devicetree-disc...@lists.ozlabs.org)
Changes v3 - v4
- [Patch 1/3] removed MTD_NAND_OMAP_BCH8 MTD_NAND_OMAP_BCH4 from nand/Kconfig
ECC scheme selectable via nand DT (nand-ecc-opt).
- [*] rebased for l2-mtd.git
(with Author Name fixed)
Changes v2 - v3
- PATCH-1: re-arranged code
ECC scheme on NAND devices can be implemented in multiple ways.Some using
Software algorithm, while others using in-build Hardware engines.
omap2-nand driver currently supports following flavours of ECC schemes.
+---+---+---+
| ECC
This patch adds following two flavours of BCH4 ECC scheme in omap2-nand driver
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
- uses GPMC H/W engine for calculating ECC.
- uses software library (lib/bch.h nand_bch.h) for error correction.
- OMAP_ECC_BCH4_CODE_HW
- uses GPMC H/W
DT property values for OMAP based gpmc-nand have been updated
to match changes in commit:
6faf096 ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signed-off-by: Pekon Gupta pe...@ti.com
---
ECC scheme on NAND devices can be implemented in multiple ways.Some using
Software algorithm, while others using in-build Hardware engines.
omap2-nand driver currently supports following flavours of ECC schemes,
selectable via DTB.
Hi..
I am running into Problems with a network adapter IRQ connected to an
omap-gpio pin.
omap-gpio expects gpio-request() to be called before i can use the pin.
But this is abstracted via the DeviceTree bindings.
I see 8d4c277e185c31359cf70573d8b0351fb7dd0dfe in mainline.
This one just puts a
+ Grant, Linus W and Jean-Christophe.
On Tue, Jul 2, 2013 at 1:44 PM, Torben Hohn torb...@linutronix.de wrote:
Hi..
I am running into Problems with a network adapter IRQ connected to an
omap-gpio pin.
omap-gpio expects gpio-request() to be called before i can use the pin.
But this is
Hi,
While booting 3.10 on AM355x-evmsk with following steps seeing race condition
leading to SPIN BUG:
Attached log for reference.
Config: omap2plus_defconfig.
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- uImage -j 8
LOADADDR=0x80008000
make ARCH=arm
On 07/01/2013 11:37 PM, Hiremath, Vaibhav wrote:
-Original Message-
From: Balbi, Felipe
Sent: Friday, June 28, 2013 4:24 PM
To: Hiremath, Vaibhav
Cc: Menon, Nishanth; Peter Korsgaard; Kevin Hilman; Balbi, Felipe; Paul
Walmsley; linux-omap@vger.kernel.org; Tony Lindgren; Sebastian
On 07/01/2013 11:29 PM, Hiremath, Vaibhav wrote:
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
Sent: Monday, July 01, 2013 7:46 AM
To: Vutla, Lokesh
Cc: Nayak, Rajendra; Hiremath, Vaibhav; Kevin Hilman; Rini, Tom; linux-
o...@vger.kernel.org; Balbi, Felipe; linux-arm-
On Tue, Jul 02, 2013 at 02:15:46PM +0200, Javier Martinez Canillas wrote:
+ Grant, Linus W and Jean-Christophe.
On Tue, Jul 2, 2013 at 1:44 PM, Torben Hohn torb...@linutronix.de wrote:
Hi..
I am running into Problems with a network adapter IRQ connected to an
omap-gpio pin.
On 06/28/2013 07:47 PM, Michael Trimarchi wrote:
Hi
On Fri, Jun 28, 2013 at 02:46:11PM +0300, Roger Quadros wrote:
On 06/28/2013 02:33 PM, Michael Trimarchi wrote:
Hi Roger
On Thu, Jun 27, 2013 at 11:07:11PM +0300, Ruslan Bilovol wrote:
On Thu, Jun 27, 2013 at 10:24 PM, Michael Trimarchi
Hi Roger
On 07/02/2013 04:42 PM, Roger Quadros wrote:
On 06/28/2013 07:47 PM, Michael Trimarchi wrote:
Hi
On Fri, Jun 28, 2013 at 02:46:11PM +0300, Roger Quadros wrote:
On 06/28/2013 02:33 PM, Michael Trimarchi wrote:
Hi Roger
On Thu, Jun 27, 2013 at 11:07:11PM +0300, Ruslan Bilovol
Add refclock and tcxoclock as clock providers in WiLink. These clocks
are not accesible outside the WiLink module, but they are registered
in the clock framework anyway. Only the WiLink chip consumes these
clocks.
In theory, the WiLink chip could be connected to external clocks
instead of using
The fref and the tcxo clocks settings are optional in some platforms.
WiLink8 doesn't need either, so we don't check the values. WiLink 6
only needs the fref clock, so we check that it is valid or return with
an error. WiLink7 needs both clocks, if either is not available we
return with an
Read the clock nodes from the device tree and use them to set the
frequency for the refclock and the tcxo clock.
Signed-off-by: Luciano Coelho coe...@ti.com
---
drivers/net/wireless/ti/wlcore/sdio.c | 36 +++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff
Since we are now using threaded IRQs without the primary handler, we
need to set IRQF_ONESHOT, otherwise our request will fail.
Signed-off-by: Luciano Coelho coe...@ti.com
---
drivers/net/wireless/ti/wlcore/main.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 16:49-20130702, Michael Trimarchi wrote:
Last question:
If one domain is in RET mode and not OFF mode what happen during SAR restore
in OFF mode?
Without going to the depth of what TRM says already:
SAR comes into play only if device-off sequence was triggered. Depending
on which domain
If platform data is not available, try to get the required information
from the device tree. Register an OF match table and parse the
appropriate device tree nodes.
Parse interrupt property only, for now.
Signed-off-by: Luciano Coelho coe...@ti.com
---
drivers/net/wireless/ti/wlcore/sdio.c |
Instead of defining an enumeration with the FW specific values for the
different clock rates, use the actual frequency instead. Also add a
boolean to specify whether the clock is XTAL or not.
Change all board files to reflect this.
Cc: Tony Lindgren t...@atomide.com
Cc: Sekhar Nori
Move the wl1251 part of the wl12xx platform data structure into a new
structure specifically for wl1251. Change the platform data built-in
block and board files accordingly.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Luciano Coelho coe...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
Hi,
This is a follow-up on a previous patch set that had a smaller
audience. This time, I added the lists and people who were involved
in the review of the bindings documentation, since most of my changes
in v2 are coming from discussions there.
This patch series adds device tree support to the
The platform_quirk element in the platform data was used to change the
way the IRQ is triggered. When set, the EDGE_IRQ quirk would change
the irqflags used and treat edge trigger differently from the rest.
Instead of hiding this irq flag setting behind the quirk, export the
whole irq_flags
On 17:55-20130702, Luciano Coelho wrote:
Instead of defining an enumeration with the FW specific values for the
different clock rates, use the actual frequency instead. Also add a
boolean to specify whether the clock is XTAL or not.
Change all board files to reflect this.
Cc: Tony
On 07/02/2013 05:49 PM, Michael Trimarchi wrote:
Hi Roger
On 07/02/2013 04:42 PM, Roger Quadros wrote:
On 06/28/2013 07:47 PM, Michael Trimarchi wrote:
Hi
When you said earlier that the problem doesn't happen when one of the
ULPIs is used
did you try both of them individually. e.g.
The pwr_in_suspend flag depends on the MMC settings which can be
retrieved from the SDIO subsystem, so it doesn't need to be part of
the platform data structure. Move it to the platform device data that
is passed from SDIO to wlcore.
Signed-off-by: Luciano Coelho coe...@ti.com
---
On Tue, Jul 02, 2013 at 12:04:32PM +0100, Mark Brown wrote:
On Tue, Jul 02, 2013 at 01:43:38PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 11:17:18AM +0100, Mark Brown wrote:
+ /* setup command reg */
+ qspi-cmd = 0;
+ qspi-cmd |= QSPI_WLEN(8);
Sourav hardcodes wordlenght
Hi,
On Tue, Jul 02, 2013 at 05:55:41PM +0300, Luciano Coelho wrote:
The platform_quirk element in the platform data was used to change the
way the IRQ is triggered. When set, the EDGE_IRQ quirk would change
the irqflags used and treat edge trigger differently from the rest.
Instead of
Hi,
On Tue, Jul 02, 2013 at 05:55:43PM +0300, Luciano Coelho wrote:
diff --git a/drivers/net/wireless/ti/wl12xx/main.c
b/drivers/net/wireless/ti/wl12xx/main.c
index 1c627da..903dcb3 100644
--- a/drivers/net/wireless/ti/wl12xx/main.c
+++ b/drivers/net/wireless/ti/wl12xx/main.c
@@ -1701,6
On Tue, Jul 02, 2013 at 05:55:44PM +0300, Luciano Coelho wrote:
Since we are now using threaded IRQs without the primary handler, we
need to set IRQF_ONESHOT, otherwise our request will fail.
Signed-off-by: Luciano Coelho coe...@ti.com
good to see this happening, I remember we talked about
On Tue, Jul 02, 2013 at 05:55:46PM +0300, Luciano Coelho wrote:
Add refclock and tcxoclock as clock providers in WiLink. These clocks
are not accesible outside the WiLink module, but they are registered
in the clock framework anyway. Only the WiLink chip consumes these
clocks.
In theory,
Hi,
On Tue, Jul 02, 2013 at 05:55:47PM +0300, Luciano Coelho wrote:
@@ -294,6 +316,8 @@ static int wl1271_probe(struct sdio_func *func,
/* Use block mode for transferring over one block size of data */
func-card-quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+
On Tue, Jul 02, 2013 at 06:19:47PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 12:04:32PM +0100, Mark Brown wrote:
One thing I really want to get round to doing with the SPI core is
providing an easy to pick up GPIO chip select as standard
that should be fairly simple I guess. Just
On Tue, Jul 2, 2013 at 4:31 PM, Torben Hohn torb...@linutronix.de wrote:
On Tue, Jul 02, 2013 at 02:15:46PM +0200, Javier Martinez Canillas wrote:
+ Grant, Linus W and Jean-Christophe.
On Tue, Jul 2, 2013 at 1:44 PM, Torben Hohn torb...@linutronix.de wrote:
Hi..
I am running into
Hi,
Alright, so I spent some time looking at the SPI framework and :
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct dra7xxx_qspi *qspi =
-20130702):
/work/kernel/next/drivers/gpio/gpio-omap.c: In function 'omap_gpio_chip_init':
/work/kernel/next/drivers/gpio/gpio-omap.c:1080:17: error: 'struct
gpio_chip' has no member named 'of_node'
/work/kernel/next/drivers/gpio/gpio-omap.c: In function 'omap_gpio_irq_map':
/work/kernel/next/drivers
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
On 07/02/2013 01:23 AM, Kevin Hilman wrote:
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
When an OMAP GPIO is used as an IRQ line, a call to gpio_request()
has to be made to initialize the OMAP GPIO bank
On Tue, 2 Jul 2013, Roger Quadros wrote:
On 07/02/2013 12:01 AM, Alan Stern wrote:
On Mon, 1 Jul 2013, Felipe Balbi wrote:
I don't know what Pad wakeup is. The wakeup signal has to originate
from the EHCI controller, doesn't it? If not, how does the Pad know
when a wakeup is
can tell.
This doesn't build for omap1_defconfig (at least in next-20130702):
/work/kernel/next/drivers/gpio/gpio-omap.c: In function 'omap_gpio_chip_init':
/work/kernel/next/drivers/gpio/gpio-omap.c:1080:17: error: 'struct
gpio_chip' has no member named 'of_node'
/work/kernel/next/drivers
Hi,
On Mon, Jul 01, 2013 at 11:42:36PM +0300, Felipe Balbi wrote:
On Mon, Jul 01, 2013 at 07:48:50PM +, Paul Walmsley wrote:
Boot to userspace:
FAIL ( 2/12): 37xxevm, am335xbonelt
quoting part of [1]
| U-Boot# tftp 0x8200 am335x-boneblack.dtb
| link up on port 0, speed 100,
Hi,
On Tue, Jul 02, 2013 at 06:04:45PM +, Paul Zimmerman wrote:
From: linux-usb-ow...@vger.kernel.org
[mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of Felipe Balbi
Sent: Tuesday, July 02, 2013 2:31 AM
Signed-off-by: Felipe Balbi ba...@ti.com
diff --git
The OMAP GPIO driver check if the chip has an associated
Device Tree node using the struct gpio_chip of_node member.
But this is only build if CONFIG_OF_GPIO is defined which
leads to the following error when using omap1_defconfig:
linux/drivers/gpio/gpio-omap.c: In function
On Tue, 2013-07-02 at 18:26 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 05:55:41PM +0300, Luciano Coelho wrote:
The platform_quirk element in the platform data was used to change the
way the IRQ is triggered. When set, the EDGE_IRQ quirk would change
the irqflags used and
On Tue, 2013-07-02 at 18:31 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 05:55:43PM +0300, Luciano Coelho wrote:
diff --git a/drivers/net/wireless/ti/wl12xx/main.c
b/drivers/net/wireless/ti/wl12xx/main.c
index 1c627da..903dcb3 100644
---
On Tue, Jul 2, 2013 at 9:46 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The OMAP GPIO driver check if the chip has an associated
Device Tree node using the struct gpio_chip of_node member.
But this is only build if CONFIG_OF_GPIO is defined which
leads to the
On Tue, 2013-07-02 at 18:32 +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 05:55:44PM +0300, Luciano Coelho wrote:
Since we are now using threaded IRQs without the primary handler, we
need to set IRQF_ONESHOT, otherwise our request will fail.
Signed-off-by: Luciano Coelho
On Tue, 2013-07-02 at 18:35 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 05:55:47PM +0300, Luciano Coelho wrote:
@@ -294,6 +316,8 @@ static int wl1271_probe(struct sdio_func *func,
/* Use block mode for transferring over one block size of data */
func-card-quirks |=
On Tue, 2013-07-02 at 10:02 -0500, Nishanth Menon wrote:
On 17:55-20130702, Luciano Coelho wrote:
Instead of defining an enumeration with the FW specific values for the
different clock rates, use the actual frequency instead. Also add a
boolean to specify whether the clock is XTAL
Linus Walleij linus.wall...@linaro.org writes:
On Tue, Jul 2, 2013 at 9:46 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The OMAP GPIO driver check if the chip has an associated
Device Tree node using the struct gpio_chip of_node member.
But this is only build if
Hi,
On Tue, Jul 02, 2013 at 06:34:23PM +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 05:55:46PM +0300, Luciano Coelho wrote:
Add refclock and tcxoclock as clock providers in WiLink. These clocks
are not accesible outside the WiLink module, but they are registered
in the clock
On Tue, Jul 02, 2013 at 11:19:54PM +0300, Luciano Coelho wrote:
On Tue, 2013-07-02 at 18:35 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 05:55:47PM +0300, Luciano Coelho wrote:
@@ -294,6 +316,8 @@ static int wl1271_probe(struct sdio_func *func,
/* Use block mode for
On Wed, 2013-07-03 at 00:32 +0300, Felipe Balbi wrote:
On Tue, Jul 02, 2013 at 11:19:54PM +0300, Luciano Coelho wrote:
On Tue, 2013-07-02 at 18:35 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 05:55:47PM +0300, Luciano Coelho wrote:
@@ -294,6 +316,8 @@ static int
Hi all,
Kindly ignore this message. It was sent in wrong format.
Sorry for the noise
Regards,
Gururaja
On Wed, Jul 03, 2013 at 10:26:57, Hebbar, Gururaja wrote:
Below is the code snippet I was referring to
From drivers/rtc/rtc-omap.c
static struct platform_device_id
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