Hi,
On Wednesday 17 July 2013 10:55 PM, Greg KH wrote:
On Wed, Jul 17, 2013 at 03:02:59PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 17 July 2013 11:59 AM, Greg KH wrote:
On Wed, Jun 26, 2013 at 05:17:29PM +0530, Kishon Vijay Abraham I wrote:
+menuconfig GENERIC_PHY
+ tristate
On Thu, Jul 18, 2013 at 11:33:17AM +0530, Kishon Vijay Abraham I wrote:
Wanted to group all the PHY drivers to be used by different subsystems
(SATA/USB/PCIE/HDMI/VIDEO) into a single entity. There were some comments
in my
initial version [3] on using a bus_type instead of class but then
On Thursday 18 July 2013 11:54 AM, Greg KH wrote:
On Thu, Jul 18, 2013 at 11:33:17AM +0530, Kishon Vijay Abraham I wrote:
Wanted to group all the PHY drivers to be used by different subsystems
(SATA/USB/PCIE/HDMI/VIDEO) into a single entity. There were some comments
in my
initial version [3]
On 07/17/2013 03:30 PM, Grygorii Strashko wrote:
On 07/17/2013 02:57 PM, Roger Quadros wrote:
Hi Grygorii,
On 07/17/2013 02:41 PM, Grygorii Strashko wrote:
Hi Tony, Kevin
This patch series introduces dynamic pinctrl handling in OMAP device
framework
in the same way as it was before
From: Jingoo Han jg1@samsung.com
Use the generic PHY API to control the DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/video/exynos_dp.txt | 18
From: Jingoo Han jg1@samsung.com
Exynos Display Port can be used only for Exynos SoCs. In addition,
non-DT for EXYNOS SoCs is not supported from v3.11; thus, there is
no need to support non-DT for Exynos Display Port.
The 'include/video/exynos_dp.h' file has been used for non-DT
support and
From: Sylwester Nawrocki s.nawro...@samsung.com
Generic PHY drivers are used to handle the MIPI CSIS and MIPI DSIM
DPHYs so we can remove now unused code at arch/arm/plat-samsung.
In case there is any board file for S5PV210 platforms using MIPI
CSIS/DSIM (not any upstream currently) it should use
From: Jingoo Han jg1@samsung.com
Add a PHY provider driver for the Samsung Exynos SoC Display Port PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by:
Updated the usb_otg_hs dt data to include the *phy* and *phy-names*
binding in order for the driver to use the new generic PHY framework.
Also updated the Documentation to include the binding information.
The PHY binding information can be found at
From: Sylwester Nawrocki s.nawro...@samsung.com
Add a PHY provider driver for the Samsung S5P/Exynos SoC MIPI CSI-2
receiver and MIPI DSI transmitter DPHYs.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Felipe Balbi
Use the generic PHY framework API to get the PHY. The usb_phy_set_resume
and usb_phy_set_suspend is replaced with power_on and
power_off to align with the new PHY framework.
musb-xceiv can't be removed as of now because musb core uses xceiv.state and
xceiv.otg. Once there is a separate state
Now that omap-usb2 is adapted to the new generic PHY framework,
*set_suspend* ops can be removed from omap-usb2 driver.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
In order for controllers to get PHY in case of non dt boot, the phy
binding information (phy device name) should be added in the platform
data of the controller.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Felipe Balbi
From: Sylwester Nawrocki s.nawro...@samsung.com
Use the generic PHY API instead of the platform callback to control
the MIPI CSIS DPHY. The 'phy_label' field is added to the platform
data structure to allow PHY lookup on non-dt platforms
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
From: Sylwester Nawrocki s.nawro...@samsung.com
Use the generic PHY API instead of the platform callback to control
the MIPI DSIM DPHY. The 'phy_label' field is added to the platform
data structure to allow PHY lookup on non-dt platforms.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Now that twl4030-usb is adapted to the new generic PHY framework,
*set_suspend* and *phy_init* ops can be removed from twl4030-usb driver.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
Used the generic PHY framework API to create the PHY. For powering on
and powering off the PHY, power_on and power_off ops are used. Once the
MUSB OMAP glue is adapted to the new framework, the suspend and resume
ops of usb phy library will be removed.
However using the old usb phy library cannot
The PHY framework provides a set of APIs for the PHY drivers to
create/destroy a PHY and APIs for the PHY users to obtain a reference to the
PHY with or without using phandle. For dt-boot, the PHY drivers should
also register *PHY provider* with the framework.
PHY drivers should create the PHY by
Added a generic PHY framework that provides a set of APIs for the PHY drivers
to create/destroy a PHY and APIs for the PHY users to obtain a reference to
the PHY with or without using phandle.
This framework will be of use only to devices that uses external PHY (PHY
functionality is not embedded
Used the generic PHY framework API to create the PHY. Now the power off and
power on are done in omap_usb_power_off and omap_usb_power_on respectively.
However using the old USB PHY library cannot be completely removed
because OTG is intertwined with PHY and moving to the new framework
will break
* Kishon Vijay Abraham I kis...@ti.com [130717 23:53]:
In order for controllers to get PHY in case of non dt boot, the phy
binding information (phy device name) should be added in the platform
data of the controller.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Sylwester
* Kishon Vijay Abraham I kis...@ti.com [130717 23:53]:
Updated the usb_otg_hs dt data to include the *phy* and *phy-names*
binding in order for the driver to use the new generic PHY framework.
Also updated the Documentation to include the binding information.
The PHY binding information can be
On Thu, Jul 18, 2013 at 12:16:10PM +0530, Kishon Vijay Abraham I wrote:
+struct phy_provider *__of_phy_provider_register(struct device *dev,
+ struct module *owner, struct phy * (*of_xlate)(struct device *dev,
+ struct of_phandle_args *args));
+struct phy_provider
On Thu, Jul 18, 2013 at 12:16:11PM +0530, Kishon Vijay Abraham I wrote:
Used the generic PHY framework API to create the PHY. Now the power off and
power on are done in omap_usb_power_off and omap_usb_power_on respectively.
However using the old USB PHY library cannot be completely removed
* Stephen Warren swar...@wwwdotorg.org [130717 14:21]:
On 07/16/2013 03:05 AM, Tony Lindgren wrote:
To toggle dynamic states, let's add the optional active state in
addition to the static default state. Then if the optional active
state is defined, we can require that idle and sleep states
* Stephen Warren swar...@wwwdotorg.org [130717 14:30]:
On 07/16/2013 03:05 AM, Tony Lindgren wrote:
To toggle dynamic states, let's add the optional active state in
addition to the static default state. Then if the optional active
state is defined, we can require that idle and sleep states
* Stephen Warren swar...@wwwdotorg.org [130717 14:28]:
On 07/16/2013 03:05 AM, Tony Lindgren wrote:
We want to have static pin states handled separately from
dynamic pin states, so let's add optional state_active.
Then if state_active is defined, let's check and make sure
state_idle
Hello Lars,
On Wed, Jul 17, 2013 at 9:04 PM, Lars-Peter Clausen l...@metafoo.de wrote:
+static int twl6032_calibration(struct twl6030_gpadc_data *gpadc)
+{
+ int chn, d1 = 0, d2 = 0, temp;
+ u8 trim_regs[17];
+ int ret;
+
+ ret = twl_i2c_read(TWL6030_MODULE_ID2, trim_regs +
Provide RESET controller and Power regulator for the USB PHY,
the USB Host port mode and the PHY device. Provide
pin multiplexer information for USB host pins.
We also relocate omap3_pmx_core pin definations so that they
are close to omap3_pmx_wkup pin definations.
Signed-off-by: Roger Quadros
We no longer need to model a RESET line as a regulator since
we have the reset-gpio driver available.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap4-panda-common.dtsi | 22 --
1 files changed, 8 insertions(+), 14 deletions(-)
diff --git
On 17/07/13 17:38, Joel Fernandes wrote:
On 07/17/2013 10:55 AM, Mark Jackson wrote:
I'm trying to get the MMC port working on our custom AM3352 CPU board.
I have added MMC entries to out dts file (similar to [1]), and I've
enabled CONFIG_TI_EDMA.
Our board boots fine without an SD card
On 07/18/2013 11:09 AM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [130717 09:48]:
Hi,
On 07/17/2013 06:32 PM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [130717 04:49]:
Add dynamic active/idle pin states for uart3/4 which will be applied
when
Till now we were modelling the RESET line as a voltage regulator and
using the regulator framework to manage it.
[1] introduces a GPIO based reset controller driver. We use that
to manage the PHY reset line, at least for DT boots. For legacy boots,
will still need to use the regulator framework
Use a common naming scheme mode0name.modename flags for the
USB host pins to be consistent.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap3-beagle.dts | 24
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git
We no longer need to model a RESET line as a regulator since
we have the reset-gpio driver available.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap3-beagle.dts | 17 -
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git
We no longer need to model a RESET line as a regulator since
we have the reset-gpio driver available.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 17 -
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git
Hi,
Till now we were modelling the RESET line as a voltage regulator and
using the regulator framework to manage it.
[1] introduces a GPIO based reset controller driver. We use that
to manage the PHY reset line, at least for DT boots. For legacy boots,
will still need to use the regulator
* Arend van Spriel ar...@broadcom.com [130718 01:47]:
We are using the panda board (es variant) for testing our SDIO based
chips. For this we have an adapter card connection to expansion
connector A. As this adapter is not publicly available we had
internally patched board-omap4panda.c. Also
Hi,
On Thursday 18 July 2013 12:50 PM, Greg KH wrote:
On Thu, Jul 18, 2013 at 12:16:10PM +0530, Kishon Vijay Abraham I wrote:
+struct phy_provider *__of_phy_provider_register(struct device *dev,
+struct module *owner, struct phy * (*of_xlate)(struct device *dev,
+struct
On Thursday 18 July 2013 12:51 PM, Greg KH wrote:
On Thu, Jul 18, 2013 at 12:16:11PM +0530, Kishon Vijay Abraham I wrote:
Used the generic PHY framework API to create the PHY. Now the power off and
power on are done in omap_usb_power_off and omap_usb_power_on respectively.
However using the
* Grygorii Strashko grygorii.stras...@ti.com [130718 02:01]:
On 07/18/2013 11:09 AM, Tony Lindgren wrote:
Don't think it's debug code - IO chain need to be rearmed after each
PRCM IO IRQ - otherwise IO wakeup events may be lost (at least on
OMAP4, OMAP5 requires more complex handling(( ).
On 07/18/2013 10:36 AM, Oleksandr Kozaruk wrote:
Hello Lars,
On Wed, Jul 17, 2013 at 9:04 PM, Lars-Peter Clausen l...@metafoo.de wrote:
+static int twl6032_calibration(struct twl6030_gpadc_data *gpadc)
+{
+ int chn, d1 = 0, d2 = 0, temp;
+ u8 trim_regs[17];
+ int ret;
+
+
Add support for calculating message length in spi framework.
Add support for quad spi controller.
Patch 2 of this series had been posted before. Sending along
with the series along with ather propsed change.
Sourav Poddar (3):
driver: spi: Modify core to compute the message length
drivers:
Make spi core calculate the message length while
populating the other transfer parameters.
Usecase, driver can use it to populate framelength filed in their
controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes
On 07/18/2013 10:59 AM, Tony Lindgren wrote:
* Arend van Spriel ar...@broadcom.com [130718 01:47]:
So my first step was to follow the recipe given in that commit.
Beside that I noticed a thread about USB issue on LKML so I also
applied the following commit:
commit
Hi,
it might be just me, but ...
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base +
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
Have you
On Thu, Jul 18, 2013 at 03:31:27PM +0530, Sourav Poddar wrote:
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding
* Tony Lindgren t...@atomide.com [130718 00:31]:
* Stephen Warren swar...@wwwdotorg.org [130717 14:21]:
On 07/16/2013 03:05 AM, Tony Lindgren wrote:
+int pinctrl_check_dynamic(struct device *dev, struct pinctrl_state *st1,
+ struct pinctrl_state *st2)
+{
+ struct
Hi Tony, Paul,
On 7/11/2013 12:03 PM, Afzal Mohammed wrote:
AM43x PRCM support (excluding clock tree) is being added with this
series. AM43x reuses most of the IP's from AM335x, as that is the
case, it was felt that reusing AM335x code as much as possible for
AM43x is better - it also helps to
Hi Felipe,
On Thursday 18 July 2013 03:54 PM, Felipe Balbi wrote:
Hi,
it might be just me, but ...
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+
Hi Arend,
On 07/18/2013 11:41 AM, Arend van Spriel wrote:
Hi Tony,
We are using the panda board (es variant) for testing our SDIO based chips.
For this we have an adapter card connection to expansion connector A. As this
adapter is not publicly available we had internally patched
On 07/18/2013 11:14 AM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [130717 10:11]:
On 07/17/2013 06:38 PM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [130717 04:49]:
Before switching to DT pinctrl states of OMAP IPs have been handled by hwmod
On 07/18/2013 01:18 PM, Roger Quadros wrote:
Hi Arend,
On 07/18/2013 11:41 AM, Arend van Spriel wrote:
Hi Tony,
We are using the panda board (es variant) for testing our SDIO based chips. For
this we have an adapter card connection to expansion connector A. As this
adapter is not publicly
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+
On 07/18/2013 02:24 PM, Arend van Spriel wrote:
On 07/18/2013 01:18 PM, Roger Quadros wrote:
Hi Arend,
On 07/18/2013 11:41 AM, Arend van Spriel wrote:
Hi Tony,
We are using the panda board (es variant) for testing our SDIO based chips.
For this we have an adapter card connection to
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for
On Thursday 18 July 2013 04:14 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:27PM +0530, Sourav Poddar wrote:
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following
Hi,
On Thu, Jul 18, 2013 at 05:15:45PM +0530, Sourav Poddar wrote:
+ list_for_each_entry(t,m-transfers, transfer_list) {
+ qspi-cmd |= QSPI_WLEN(t-bits_per_word);
+ qspi-cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret = qspi_transfer_msg(qspi, t);
+ if (ret) {
Hi Tony,
On 07/18/2013 12:04 PM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [130718 02:01]:
On 07/18/2013 11:09 AM, Tony Lindgren wrote:
Don't think it's debug code - IO chain need to be rearmed after each
PRCM IO IRQ - otherwise IO wakeup events may be lost (at least
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
On 07/18/2013 01:30 PM, Roger Quadros wrote:
On 07/18/2013 02:24 PM, Arend van Spriel wrote:
On 07/18/2013 01:18 PM, Roger Quadros wrote:
Hi Arend,
On 07/18/2013 11:41 AM, Arend van Spriel wrote:
Hi Tony,
We are using the panda board (es variant) for testing our SDIO based chips. For
this
On 07/18/2013 03:38 PM, Arend van Spriel wrote:
On 07/18/2013 01:30 PM, Roger Quadros wrote:
On 07/18/2013 02:24 PM, Arend van Spriel wrote:
On 07/18/2013 01:18 PM, Roger Quadros wrote:
Hi Arend,
On 07/18/2013 11:41 AM, Arend van Spriel wrote:
Hi Tony,
We are using the panda board (es
On Thu, Jul 18, 2013 at 05:15:45PM +0530, Sourav Poddar wrote:
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
+ list_for_each_entry(t,m-transfers, transfer_list) {
+ qspi-cmd |= QSPI_WLEN(t-bits_per_word);
+ qspi-cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret =
Hi,
On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote:
+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
+{
+ struct ti_qspi *qspi = dev_id;
+ u16 mask, stat;
+
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(qspi-lock);
+
+ stat = ti_qspi_readl(qspi,
* Tony Lindgren t...@atomide.com [130718 00:57]:
* Stephen Warren swar...@wwwdotorg.org [130717 14:28]:
Oh, I see you're trying to check that the set of pins in the active,
sleep, and idle states are identical.
Right, that's to avoid any further checking during runtime for runtime PM.
On Thu, Jul 18, 2013 at 04:31:58PM +0300, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote:
So why do we report that we handled the interrupt then? Shouldn't we at
least warn if we're getting spurious IRQs?
not spurious. OMAP has two sets of IRQ status
Hi Mark,
On Thursday 18 July 2013 08:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 04:31:58PM +0300, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote:
So why do we report that we handled the interrupt then? Shouldn't we at
least warn if we're getting spurious
Hi all,
Here's this series again with hopefully all the comments addressed.
As discussed earlier, the pinctrl support for changing some of the
consumer device pins during runtime needs some improvment.
It's quite common that we need to dynamically change some pins for a
device for runtime PM, or toggle a pin between rx and tx. Changing all
the pins for a device is not efficient way of doing it.
So let's allow setting up multiple active states for pinctrl. Currently
we only need PINCTRL_STATIC
We want to have static pin states handled separately from
dynamic pin states, so let's add optional state_active.
Then if state_active is defined, let's check and make sure
state_idle and state_sleep match state_active for the
pin groups to avoid checking them during runtime as the
active and
To toggle dynamic states, let's add the optional active state in
addition to the static default state. Then if the optional active
state is defined, we can require that idle and sleep states cover
the same pingroups as the active state.
Then let's add pinctrl_check_dynamic() and
There's no need to duplicate essentially the same functions. Let's
introduce static int pinctrl_pm_select_state() and make the other
related functions call that.
This allows us to add support later on for multiple active states,
and more optimized dynamic remuxing.
Note that we still need to
On Thu, Jul 18, 2013 at 03:31:25PM +0530, Sourav Poddar wrote:
Make spi core calculate the message length while
populating the other transfer parameters.
Applied, thanks.
signature.asc
Description: Digital signature
On Thu, Jul 18, 2013 at 08:25:05PM +0530, Sourav Poddar wrote:
there is a QSPI_INTR_STATUS_ENABLED_CLEAR register, which indicated
the interrupt
status.
if nothing is set in the above register, I should return IRQ_NONE.
Yes, and/or complain in the log.
signature.asc
Description: Digital
On Thu, Jul 18, 2013 at 02:29:52PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 18 July 2013 12:50 PM, Greg KH wrote:
On Thu, Jul 18, 2013 at 12:16:10PM +0530, Kishon Vijay Abraham I wrote:
+struct phy_provider *__of_phy_provider_register(struct device *dev,
+ struct module
Hi,
I'm facing a NULL pointer dereference in omap_hsmmc_start_command() on
an AM33xx board running 3.11-rc1 (DMA enabled).
A quick debug session showed that DMA engine timing leads to a very
reproducable race condition. In omap_hsmmc_request(), we have:
host-mrq = req;
On Thursday 18 July 2013 09:36 PM, Daniel Mack wrote:
Hi,
I'm facing a NULL pointer dereference in omap_hsmmc_start_command() on
an AM33xx board running 3.11-rc1 (DMA enabled).
A quick debug session showed that DMA engine timing leads to a very
reproducable race condition. In
On Wednesday 17 July 2013 10:08 PM, Joel Fernandes wrote:
On 07/17/2013 10:55 AM, Mark Jackson wrote:
I'm trying to get the MMC port working on our custom AM3352 CPU board.
I have added MMC entries to out dts file (similar to [1]), and I've
enabled CONFIG_TI_EDMA.
Our board boots fine without
Some socs have a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt/dma controllers
This adds the irq/dma crossbar device nodes.
There is a IRQ and DMA crossbar device in the soc, which
maps the irq/dma requests from the peripherals to the
mpu/dsp/ipu/eve interrupt and sdma/edma controller's inputs.
The Peripheral irq/dma requests are connected to only one crossbar
input and the
Enable the crossbar driver to handle the irq/dma
crossbar devices in the soc.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/mach-omap2/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 80aaadc..3def350
Some socs have a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt/dma controllers
Hi Balaji,
On 18.07.2013 18:40, Balaji T K wrote:
With DMA channel info retrieved from dt binding on 3.11rc1,
unused_chan_list is broken after hwmod cleanup removing mmc sdma
resource info, hence pdev resource wont have DMA resource populated.
arch/arm/common/edma.c
static int
From: Matt Porter mpor...@ti.com
Implement device_slave_sg_limits().
EDMA has a finite set of PaRAM slots available for linking a
multi-segment SG transfer. In order to prevent any one channel
from consuming all PaRAM slots to fulfill a large SG transfer,
the driver reports a static per-channel
From: Matt Porter mpor...@ti.com
Add a dmaengine API to retrieve slave SG transfer limits.
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this API provides the required dma channel, address width, and
burst size of
From: Matt Porter mpor...@ti.com
The EDMA DMAC has a hardware limitation that prevents supporting
scatter gather lists with any number of segments. The DMA Engine
API reports the maximum number of segments a channel can support
via the optional dma_get_slave_sg_limits() API. If the max_nr_segs
On Thu, 2013-07-18 at 22:13 +0530, Sricharan R wrote:
Some socs have a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers
On 07/17/2013 04:54 PM, Laurent Pinchart wrote:
Hello,
Here's a small patch set that replaces PWM polarity numerical constants with
macros in DT.
The series,
Reviewed-by: Stephen Warren swar...@nvidia.com
I'm (very very) slightly hesitant about patch 3/4, since it's moving
towards all PWMs
On Thu, Jul 18, 2013 at 11:46:39AM -0500, Joel Fernandes wrote:
From: Matt Porter mpor...@ti.com
Add a dmaengine API to retrieve slave SG transfer limits.
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this
Hi Balaji,
On 07/18/2013 11:40 AM, Balaji T K wrote:
On Wednesday 17 July 2013 10:08 PM, Joel Fernandes wrote:
On 07/17/2013 10:55 AM, Mark Jackson wrote:
I'm trying to get the MMC port working on our custom AM3352 CPU board.
I have added MMC entries to out dts file (similar to [1]), and
On 07/18/2013 11:47 AM, Daniel Mack wrote:
Hi Balaji,
On 18.07.2013 18:40, Balaji T K wrote:
With DMA channel info retrieved from dt binding on 3.11rc1,
unused_chan_list is broken after hwmod cleanup removing mmc sdma
resource info, hence pdev resource wont have DMA resource populated.
On Thu, Jul 18, 2013 at 11:46:39AM -0500, Joel Fernandes wrote:
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this API provides the required dma channel, address width, and
burst size of the transfer.
Hi,
On Thu, Jul 18, 2013 at 10:13:48PM +0530, Sricharan R wrote:
Some socs have a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the
On 07/18/2013 11:43 AM, Sricharan R wrote:
Some socs have a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers
On 07/18/2013 12:08 PM, Russell King - ARM Linux wrote:
On Thu, Jul 18, 2013 at 11:46:39AM -0500, Joel Fernandes wrote:
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this API provides the required dma channel,
On 07/18/2013 11:43 AM, Sricharan R wrote:
This adds the irq/dma crossbar device nodes.
There is a IRQ and DMA crossbar device in the soc, which
maps the irq/dma requests from the peripherals to the
mpu/dsp/ipu/eve interrupt and sdma/edma controller's inputs.
The Peripheral irq/dma requests are
On Thu, Jul 18, 2013 at 3:01 AM, Sourav Poddar sourav.pod...@ti.com wrote:
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods:
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