I submitted this in December last year. I got lots of good feedback
and fixed some things, but it never got accepted. Not entirely sure
why, maybe I dropped the ball.
Anyway, here is again with device-tree support added.
This is only an RFC and not a real submission for two reasons, both of
I would like to use omap dmtimer for a PWM driver (for the backlight
on my display).
But there are two difficulties.
Unfortunately Jon Hunter (who has helped me with dmtimers before)
seems to have disappeared. So I guess I get to do it myself :-)
Following two patches make dmtimers more usable.
It is perfectly appropriate to set the counter register
when the timer isn't running. The value set will be where
the counter starts counting from.
Signed-off-by: NeilBrown ne...@suse.de
---
arch/arm/plat-omap/dmtimer.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
This is no need for dmtimer.h to be in the 'plat' include directory,
and it makes it hard to write drivers which use it (such as a
PWM driver). So move it to linux/omap-dmtimer.h.
Signed-off-by: NeilBrown ne...@suse.de
---
arch/arm/mach-omap1/pm.c |2
Hi Tony, Tero,
On 09/10/13 16:12, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/cclock44xx_data.c | 3
Am Dienstag, 17. September 2013, 14:43:26 schrieb Russ Dill:
This patch adds support for and demonstrates the usage of an embedded
position independent executable (PIE). The goal is to allow the use of C
code in situations where carefully written position independent assembly
was previously
Hi!
3. cmt_speech
This is an hsi client driver, which takes care of interchanging
speech data with the modem. This one is needed for calling. I
will have a look at it once the basic stuff is working.
P.S.: You can get a mainline kernel status matrix for the Nokia
N900 on this
On Tue, 1 Oct 2013, Rob Herring wrote:
On 10/01/2013 06:13 AM, Sricharan R wrote:
Is there an actual usecase on a single h/w design that you run out of
interrupts and it is a user decision which interrupts to use?
I don't think that matters. What matters is that you have a single DT
entry
On Mon, 30 Sep 2013, Sricharan R wrote:
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1760ceb..c5778ab 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -72,6 +72,8 @@ struct gic_chip_data {
static
On Mon, 30 Sep 2013, Sricharan R wrote:
+/*
+ * @int_max: maximum number of supported interrupts
+ * @irq_map: array of interrupts to crossbar number mapping
+ * @crossbar_base: crossbar base address
+ * @register_offsets: offsets for each irq number
+ */
+struct crossbar_device {
+
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input
On Oct 24, 2013, at 12:50 AM, NeilBrown wrote:
[my first device-tree related patch. Please let me know what I got wrong so
I wont repeat the mistake in all the others I have queued]
This allows the charger to be enabled with devicetree, and
allows the parameters for charging the backup
On Thu, 24 Oct 2013 04:44:03 -0500, Kumar Gala ga...@codeaurora.org wrote:
On Oct 24, 2013, at 12:50 AM, NeilBrown wrote:
[my first device-tree related patch. Please let me know what I got wrong so
I wont repeat the mistake in all the others I have queued]
This allows the charger
Hi Thomas,
Thanks a lot for reviewing this.
On Thursday 24 October 2013 02:42 PM, Thomas Gleixner wrote:
On Mon, 30 Sep 2013, Sricharan R wrote:
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1760ceb..c5778ab 100644
--- a/drivers/irqchip/irq-gic.c
+++
Hi Thomas,
On Thursday 24 October 2013 02:50 PM, Thomas Gleixner wrote:
On Mon, 30 Sep 2013, Sricharan R wrote:
+/*
+ * @int_max: maximum number of supported interrupts
+ * @irq_map: array of interrupts to crossbar number mapping
+ * @crossbar_base: crossbar base address
+ *
On Tue, 22 Oct 2013 06:49:48 -0700, Tony Lindgren t...@atomide.com wrote:
With the recent pinctrl-single changes, omaps can treat
wake-up events from deeper idle states as interrupts.
There's a separate io chain controller on most omaps
that stays enabled when the device hits off-idle and
On Thu, 24 Oct 2013 11:06:52 +0100 Grant Likely grant.lik...@linaro.org
wrote:
On Thu, 24 Oct 2013 04:44:03 -0500, Kumar Gala ga...@codeaurora.org wrote:
On Oct 24, 2013, at 12:50 AM, NeilBrown wrote:
[my first device-tree related patch. Please let me know what I got wrong
so
Hi Kumar,
On Thursday 24 October 2013 03:03 PM, Kumar Gala wrote:
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at
On Thursday 24 October 2013 03:08 PM, Kumar Gala wrote:
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and
This patch updates following in omap_nand_probe() and omap_nand_remove()
- replaces info-nand with nand_chip (struct nand_chip *nand_chip)
- replaces info-mtd with mtd (struct mtd_info *mtd)
- white-space and formatting cleanup
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to nand_scan_ident(), incase first call fails
then omap_nand_probe just returns error.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 21 +
1 file changed, 9
OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.
This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
-
generic frame-work in mtd/nand/nand_bch.c is a wrapper above lib/bch.h which
encapsulates all control information specific to BCH ecc algorithm in software.
Thus this patch:
(1) replace omap specific implementations with equivalent wrapper in nand_bch.c
so that generic code from nand_bch.c is
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE
In current implementation omap3_init_bch_tail() is a common function to
define ecc layout for different BCHx ecc schemes.This patch:
(1) removes omap3_init_bch_tail() and defines ecc layout for individual
ecc-schemes along with populating their nand_chip-ecc data in
omap_nand_probe(). This
current implementation in omap3_init_bch() has some redundant code like:
(1) omap3_init_bch() re-probes the DT-binding to detect presence of ELM h/w
engine on SoC. And based on that it selects implemetation of ecc-scheme.
However, this is already done as part of GPMC DT parsing.
(2) As
*changes v10 - v11*
- [PATCH v10 04/10] replaced with newer [PATCH v11 04/11] so that
nand_scan_ident() is called only once.
discussion thread with Brian Norris computersforpe...@gmail.com
http://lists.infradead.org/pipermail/linux-mtd/2013-October/049335.html
- No change in any other patch
Managed Device Resource or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver
With OMAP NAND driver updates, selection of ecc-scheme:
*DT enabled kernel*
depends on ti,nand-ecc-opt and ti,elm-id DT bindings.
*Non DT enabled kernel*
depends on elm_dev and ecc-scheme passed along with platform-data
from board file.
So, selection of ecc-scheme (BCH8 or
Updated DTS to replace deprecated binding with newer values
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
2 files
Hi Ezequiel,
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
I won't be able to make too much progress without some help or without
squeezing my brains out :P
Care to push some git branch on some random repo with DT support for
the NAND cape in the Beaglebone?
Apologies
Pekon,
On Thu, Oct 24, 2013 at 12:59:26PM +, Gupta, Pekon wrote:
Hi Ezequiel,
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
I won't be able to make too much progress without some help or without
squeezing my brains out :P
Care to push some git branch on some
* Grant Likely grant.lik...@secretlab.ca [131024 03:33]:
On Tue, 22 Oct 2013 06:49:48 -0700, Tony Lindgren t...@atomide.com wrote:
@@ -1572,11 +1603,23 @@ static int serial_omap_probe(struct platform_device
*pdev)
struct uart_omap_port *up;
struct resource *mem, *irq;
On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
Hi Tony, Tero,
On 09/10/13 16:12, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
* Tero Kristo t-kri...@ti.com [131024 06:23]:
On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
Hi Tony, Tero,
On 09/10/13 16:12, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
On Oct 24, 2013, at 5:43 AM, Sricharan R wrote:
Hi Kumar,
On Thursday 24 October 2013 03:03 PM, Kumar Gala wrote:
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
On 10/24/2013 04:28 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131024 06:23]:
On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
Hi Tony, Tero,
On 09/10/13 16:12, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the
* Tero Kristo t-kri...@ti.com [131024 06:32]:
On 10/24/2013 04:28 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131024 06:23]:
On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
Hi Tony, Tero,
On 09/10/13 16:12, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so
Hi Pekon,
Just as suggestion, I think you should reconsider your 'upstream strategy'.
On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote:
[..]
Pekon Gupta (10):
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
mtd: nand: omap: combine different flavours of 1-bit
On Wed, 9 Oct 2013, Tomi Valkeinen wrote:
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other
On Wed, 9 Oct 2013, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
Thanks, queued.
- Paul
--
To unsubscribe from this list: send
On Wed, 9 Oct 2013, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Tony,
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git
On Tue, Oct 22, 2013 at 10:30:43AM -0500, Joel Fernandes wrote:
On 10/21/2013 01:53 AM, Vinod Koul wrote:
On Mon, Sep 23, 2013 at 06:05:14PM -0500, Joel Fernandes wrote:
+ nr_periods = (buf_len / period_len) + 1;
?
consider the case of buf = period_len, above makes nr_period = 2.
On 10/24/2013 11:38 AM, Vinod Koul wrote:
On Tue, Oct 22, 2013 at 10:30:43AM -0500, Joel Fernandes wrote:
On 10/21/2013 01:53 AM, Vinod Koul wrote:
On Mon, Sep 23, 2013 at 06:05:14PM -0500, Joel Fernandes wrote:
+ nr_periods = (buf_len / period_len) + 1;
?
consider the case of buf =
Sorry for top posting Probably we should move the dmtimer to drivers/misc
or create drivers/timer/
This has been pending for quite some time now
Tony, what you say ?
From: linux-arm-kernel [linux-arm-kernel-boun...@lists.infradead.org] on behalf
Hi Ezequiel
On Wed, Oct 23, 2013 at 4:13 PM, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
Pekon,
On Wed, Oct 23, 2013 at 01:55:58PM +, Gupta, Pekon wrote:
I'm wondering how are you testing this in your SOC_AM33XX board (which
is not ARCH_OMAP3). You probably have
Javier,
On Thu, Oct 24, 2013 at 09:49:09PM +0200, Javier Martinez Canillas wrote:
Hi Ezequiel
On Wed, Oct 23, 2013 at 4:13 PM, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
Pekon,
On Wed, Oct 23, 2013 at 01:55:58PM +, Gupta, Pekon wrote:
I'm wondering how are you
On Thu, Oct 24, 2013 at 06:20:20PM +0530, Pekon Gupta wrote:
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to nand_scan_ident(), incase first call fails
then omap_nand_probe just returns error.
Signed-off-by: Pekon Gupta pe...@ti.com
---
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index
This option does not need to depend in MTD_NAND, for it's enclosed
under it. Also, it's wrong to make it depend in ARCH_OMAP3 only
since the controller is used in a wider range of SoCs.
Instead, just leave the dependency on the OMAP2 driver option.
Signed-off-by: Ezequiel Garcia
From: Pekon Gupta pe...@ti.com
Add GPMC timing configurations and NAND partitions for the Beaglebone
NAND cape. Further information and datasheets of this cape can be found at:
- http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
-
This simplifies the code and makes it less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 30 +++---
1 file changed, 7 insertions(+), 23 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c
Hello everyone,
As it was discussed recently in the mailing list, the omap2-nand driver
currently
has an issue preventing proper ONFI detection of 16-bit devices (other drivers
may suffer from this same issue).
In an attempt to address such issue, patch 2/5 mtd: nand: omap2: Fix device
From: Pekon Gupta pe...@ti.com
Because the device bus can be 8-bit or 16-bit width, yet ONFI detection
cannot work in 16-bit mode, we need to set the NAND_BUSWIDTH_AUTO option
which allows proper initialization configuration.
Once the bus width is detected, nand_scan_ident() updates the
Hi,
On Fri, Oct 25, 2013 at 12:12 AM, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 6 +-
1 file changed, 1
On Thu, Oct 24, 2013 at 06:27:15PM -0300, Ezequiel Garcia wrote:
On Thu, Oct 24, 2013 at 06:20:20PM +0530, Pekon Gupta wrote:
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to nand_scan_ident(), incase first call fails
then omap_nand_probe
On Thu, Oct 24, 2013 at 03:43:00PM -0700, Brian Norris wrote:
On Thu, Oct 24, 2013 at 06:27:15PM -0300, Ezequiel Garcia wrote:
On Thu, Oct 24, 2013 at 06:20:20PM +0530, Pekon Gupta wrote:
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to
On Fri, Oct 25, 2013 at 12:24:38AM +0200, Belisko Marek wrote:
Hi,
On Fri, Oct 25, 2013 at 12:12 AM, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia
On Oct 24, 2013, at 5:41 AM, NeilBrown wrote:
On Thu, 24 Oct 2013 11:06:52 +0100 Grant Likely grant.lik...@linaro.org
wrote:
On Thu, 24 Oct 2013 04:44:03 -0500, Kumar Gala ga...@codeaurora.org wrote:
On Oct 24, 2013, at 12:50 AM, NeilBrown wrote:
[my first device-tree related patch.
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