On Tue, Sep 17, 2013 at 03:30:23PM +0200, Benoit Cousson wrote:
I've just applied it on top of Joel's one.
Benoit,
Can you tell me where to find your git tree so that I can follow these
patches' progress?
Thanks,
Richard
--
To unsubscribe from this list: send the line unsubscribe linux-omap
On 10/25/2013 04:04 AM, Richard Cochran wrote:
On Tue, Sep 17, 2013 at 03:30:23PM +0200, Benoit Cousson wrote:
I've just applied it on top of Joel's one.
Benoit,
Can you tell me where to find your git tree so that I can follow these
patches' progress?
From: Wei Yongjun yongjun_...@trendmicro.com.cn
In case of error, the function platform_device_register_resndata()
returns ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
DISPLAY_SEL_GPIO and DLP_POWER_ON_GPIO are now handled in the .dts file,
so we can remove them from dss-common.c.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/dss-common.c | 21 -
1 file changed, 21 deletions(-)
diff --git
New u-boot versions no longer set the pinmuxing for Panda's DPI output,
and the muxing has to be done in the .dts file.
Add pinmuxing for DPI and TFP410. Without these, the DVI output on Panda
does not work with recent u-boot.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
Add pinmuxing for the LCD panels.
Both panels have a reset GPIO, but the second one has some extra
complexity: some boards have a PicoDLP projector, which shares resources
with the LCD2. We don't currently support switching between the PicoDL
and the LCD2, so we use pin pull-ups and pull-downs to
From: Pekon Gupta pe...@ti.com
Because the device bus can be 8-bit or 16-bit width, yet ONFI detection
cannot work in 16-bit mode, we need to set the NAND_BUSWIDTH_AUTO option
which allows proper initialization configuration.
Once the bus width is detected, nand_scan_ident() updates the
This option does not need to depend in MTD_NAND, for it's enclosed
under it. Also, it's wrong to make it depend in ARCH_OMAP3 only
since the controller is used in a wider range of SoCs.
Instead, just leave the dependency on the OMAP2 driver option.
Signed-off-by: Ezequiel Garcia
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index
From: Pekon Gupta pe...@ti.com
Add GPMC timing configurations and NAND partitions for the Beaglebone
NAND cape. Further information and datasheets of this cape can be found at:
- http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
-
Hello everyone,
As it was discussed recently in the mailing list, the omap2-nand driver
currently
has an issue preventing proper ONFI detection of 16-bit devices (other drivers
may suffer from this same issue).
In an attempt to address such issue, patch 2/5 mtd: nand: omap2: Fix device
This simplifies the code and makes it less error-prone. In fact,
this commit fixes a missing iounmap() in the cleanup error path.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 31 +++
1 file changed, 7 insertions(+),
On 10/25/2013 05:07 AM, Tomi Valkeinen wrote:
DISPLAY_SEL_GPIO and DLP_POWER_ON_GPIO are now handled in the .dts file,
so we can remove them from dss-common.c.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/dss-common.c | 21 -
1 file
Hi,
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
-int r;
-
-r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
-display_sel);
-if (r)
-pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
Hi Laurent,
Sorry about the late response, I had scrapped the DT patch out of the
VPE series since there were dependencies on crossbar drivers and some
other baseport stuff. Comments below.
On Friday 09 August 2013 03:41 AM, Laurent Pinchart wrote:
Hi Archit,
Thank you for the patch.
On
On Fri, Oct 25, 2013 at 10:25:02AM +, Gupta, Pekon wrote:
Hi,
This simplifies the error path and makes the code less error-prone.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 5 +
1 file changed, 1 insertion(+), 4
On 10/25/2013 05:25 AM, Tomi Valkeinen wrote:
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
- display_sel);
- if (r)
- pr_err(%s:
Pekon,
On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote:
*changes v10 - v11*
- [PATCH v10 04/10] replaced with newer [PATCH v11 04/11] so that
nand_scan_ident() is called only once.
discussion thread with Brian Norris computersforpe...@gmail.com
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
Hm.. well the problem with that patch is that it's in the middle of an
unrelated series. As I already told you, I think you should have pushed
that as a one-patch fix. Have you seen that suggestion?
Yes, I know.. actually
On 25/10/13 13:54, Nishanth Menon wrote:
would you not be depending on the weak IO pull done using mux to drive
these GPIO pins since the GPIO is not requested and held?
Yes. Is that not enough?
It depend on what the signal draw is and io drive strength which
varies - original intent of
On 10/25/2013 05:54 AM, Nishanth Menon wrote:
On 10/25/2013 05:25 AM, Tomi Valkeinen wrote:
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
-
Hi,
-Original Message-
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
[...]
Pekon, Brian: Do you think this solution might work for 8-bit and 16-bit
devices?
I think NAND_BUSWIDTH_AUTO (without GPMC changes) would fail in
following scenarios..
Case-1:
On 25/10/13 14:14, Nishanth Menon wrote:
one additional angle before I forget - this is something we do as part
of power optimization - to identify pins which are programmed for a
pull in non-functional scenario as it has direct impact on idle power
numbers.
For example patch #3 in this
On Fri, Oct 25, 2013 at 11:09:14AM +, Gupta, Pekon wrote:
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
Hm.. well the problem with that patch is that it's in the middle of an
unrelated series. As I already told you, I think you should have pushed
that as a
On 10/25/2013 06:13 AM, Tomi Valkeinen wrote:
On 25/10/13 13:54, Nishanth Menon wrote:
[..]
Could we not use Documentation/devicetree/bindings/gpio/gpio.txt
binding to map to the right GPIO and drive it using the GPIO module?
Hmm, what do you mean?
I do mux the pins to gpios, but there's
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
Subject: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option
dependency
This option does not need to depend in MTD_NAND, for it's enclosed
under it. Also, it's wrong to make it depend in ARCH_OMAP3 only
since the controller
On 25/10/13 14:21, Nishanth Menon wrote:
The problem here is that the gpios don't really belong to anyone in the
kernel, as we don't have a driver for the switch.
Or did you mean that we'd still have the code in dss-common.c, but just
get the gpio numbers from the .dts instead? That makes
On 25/10/13 14:14, Nishanth Menon wrote:
lcd2_pins: pinmux_lcd2_pins {
+ pinctrl-single,pins =
+ 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+ 0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+ 0x56
Pekon,
On Fri, Oct 25, 2013 at 11:15:57AM +, Gupta, Pekon wrote:
Hi,
-Original Message-
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
[...]
Pekon, Brian: Do you think this solution might work for 8-bit and 16-bit
devices?
I think
On Fri, Oct 25, 2013 at 11:26:06AM +, Gupta, Pekon wrote:
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
Subject: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option
dependency
This option does not need to depend in MTD_NAND, for it's enclosed
under it. Also,
enable a few more drivers as modules on omap2plus_defconfig,
this helps us getting more platforms working out of the box
by just building omap2plus_defconfig.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Hi Tony,
would you consider enabling these drivers ? I didn't, yet,
make sure that these
* Shilimkar, Santosh santosh.shilim...@ti.com [131024 11:11]:
Sorry for top posting Probably we should move the dmtimer to
drivers/misc or create drivers/timer/
This has been pending for quite some time now
Tony, what you say ?
Yes that should be done and we should cc Thomas
* Felipe Balbi ba...@ti.com [131025 07:20]:
enable a few more drivers as modules on omap2plus_defconfig,
this helps us getting more platforms working out of the box
by just building omap2plus_defconfig.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Hi Tony,
would you consider enabling
On 10/25/2013 06:46 AM, Tomi Valkeinen wrote:
On 25/10/13 14:14, Nishanth Menon wrote:
lcd2_pins: pinmux_lcd2_pins {
+pinctrl-single,pins =
+0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/*
Hi,
On Fri, Oct 25, 2013 at 07:44:26AM -0700, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [131025 07:20]:
enable a few more drivers as modules on omap2plus_defconfig,
this helps us getting more platforms working out of the box
by just building omap2plus_defconfig.
Signed-off-by:
Previously, only direct register read/write was supported. Now a per-clock
regmap can be provided for same purpose, which allows the clock drivers
to access clock registers behind e.g. I2C bus.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c|6 +++---
Multiplexer clock can now be initialized to use regmap for control register
access.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 17 +++--
include/linux/clk-provider.h |4
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git
Hi all,
Version 9 contains following major changes:
- Clock nodes changed to use offsets instead of direct memory addresses
* of_iomap() no longer called by individual clock drivers
* prcm-driver provides regmap for accessing the registers based on
the offsets
* added support for
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo
This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../bindings/clock/ti/fixed-factor-clock.txt | 29 +
drivers/clk/ti/Makefile
Divider clock can now be initialized to use regmap for control register
access.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 37 -
include/linux/clk-provider.h |6 ++
2 files changed, 38 insertions(+), 5 deletions(-)
This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/divider.txt | 86 +++
drivers/clk/ti/Makefile|
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/composite.txt
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific
ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/ti/clk.c | 59
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c |1 +
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 81 +++
arch/arm/mach-omap2/clock.h| 144 +
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock3xxx.h |
From: J Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/clock/ti/mux.txt | 67 ++
drivers/clk/ti/Makefile|2 +-
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/interface.txt | 54
arch/arm/mach-omap2/clock.h
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero
clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |2 +-
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/clockdomain.txt |
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
-
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock.h |1 -
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |1 +
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 672 ++
arch/arm/boot/dts/am33xx.dtsi|2 +
2 files changed, 674
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am3517-evm.dts|2 +-
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
Signed-off-by: Tero Kristo
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |2 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1416
2 files changed,
From: J Keerthy j-keer...@ti.com
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
From: J Keerthy j-keer...@ti.com
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |9 +++--
1 file
From: Roger Quadros rog...@ti.com
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
From: J Keerthy j-keer...@ti.com
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++---
1 file changed, 11 insertions(+), 3
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..bf7797e 100644
---
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am4372.dtsi|2 +
arch/arm/boot/dts/am43xx-clocks.dtsi | 666 ++
2 files changed, 668
Initializes clock data from device tree.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/io.c
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c | 13 -
1 file
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/Makefile |1 -
Using regmap is required for isolating the actual memory access from
the clock code. Now, the driver providing the support for the clock IP
block can provide a regmap for this purpose.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 20
clk_init is now separated to a common function which gets called for all
SoC:s, which initializes the DT clocks and calls the SoC specific clock init.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/common.h |2 +-
arch/arm/mach-omap2/io.c | 32
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |2 +
Clock nodes shall use the services provided by underlying drivers to access
the hardware registers instead of direct memory read/write. Thus, change
all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
On Fri, 2013-10-25 at 18:57 +0300, Tero Kristo wrote:
+ mcasp0_fck: mcasp0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+
79 matches
Mail list logo
