On 03/26/2014 12:36 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [140304 08:23]:
There is a solitary write to this register every wakeup from off-mode,
which isn't doing anything, so remove it.
Argh, this chunk of code is for sure the the thing that's blocking all
the voltage
During system resume, if the event buffers are not setup before
the gadget controller starts then we start with invalid context
and this can lead to bus access errors. This is especially true for
platforms that loose the controller context during system suspend.
e.g. AM437x.
The following
On 01/08/2014 02:39 AM, Tony Lindgren wrote:
* Taras Kondratiuk taras.kondrat...@linaro.org [131223 10:20]:
On 23 December 2013 20:10, Taras Kondratiuk taras.kondrat...@linaro.org
wrote:
This series does trivial replacement of __raw_xxx functions with xxx_relaxed
endian-neutral variants in
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 46f8c53..352f252
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 16
1 file changed, 16 insertions(+)
diff --git
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |8
1 file changed, 8 insertions(+)
diff --git
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++
drivers/pci/host/Kconfig | 10
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
This patch series adds support for PCIe in DRA7xx including drivers and dt
data. PCIe in DRA7xx uses desingware IP and hence this re-uses the
pcie desingware driver (pcie-designware.c) by Jingoo.
This patch series depends on a few patches that is already in -next.
Tested broadcom PCIe card and
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git
On Wed, Mar 26, 2014 at 8:57 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On Wednesday 26 March 2014 08:15 PM, Rob Herring wrote:
On Wed, Mar 26, 2014 at 8:57 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay
On Mon, 24 Mar 2014 12:15:23 +0200
Jyri Sarha jsa...@ti.com wrote:
This patch is implemented on top of late patches from Jean-Francois
Moine [1].
These patches implement the main part of the simple-card changes
discussed in alsa-devel mailing list [2].
Acked-by: Jean-Francois Moine
* Tero Kristo t-kri...@ti.com [140326 01:04]:
On 03/26/2014 12:36 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [140304 08:23]:
There is a solitary write to this register every wakeup from off-mode,
which isn't doing anything, so remove it.
Argh, this chunk of code is for sure the
now that we can finally read the new registers for
new versions of the mmc IP, we can set max_blk_size
correctly depending on the version of the IP we're
running on.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 45 ++-
1
the newly introduced accessor funtions will help
dealing with register access which shouldn't be
done with offset in consideration.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 200 --
1 file changed, 96 insertions(+), 104
we introduce new accessors which provide for register
access with and without offsets.
This is just to make sure newer versions of the IP
can access the new registers prepended at the beginning
of the address space.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 36
This patch is in preparation for a larger series
of cleanups on the omap_hsmmc.c driver.
In newer instances of this IP, there's a lot of
configuration details which we can grab by reading
some new registers which were prepended to the
address space.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Hi,
this series lets us access the newer registers introduced
back in OMAP4 which give us some valid information about
the OMAP HSMMC IP like max block size, support for ADMA,
support for Retention.
Right now, only setting max_blk_size correctly as supporting
ADMA and Retention will take a lot
by saving reg_offset inside our host structure
we can ioremap the correct area, make use of
resource_size() and make sure newer versions
of the IP have access to the new set of registers
which were added back in OMAP4.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |
Hi,
On Wed, Mar 26, 2014 at 07:04:50PM -0500, Felipe Balbi wrote:
@@ -1867,6 +1879,37 @@ static inline struct omap_mmc_platform_data
}
#endif
+static void omap_hsmmc_set_max_blk_size(struct omap_hsmmc_host *host)
+{
+ struct mmc_host *mmc = host-mmc;
+
+ if
[ +to Marcel Holtmann ]
On 03/20/2014 03:30 PM, Felipe Balbi wrote:
LDISCs shouldn't call tty-ops-write() from within
-write_wakeup().
-write_wakeup() is called with port lock taken and
IRQs disabled, tty-ops-write() will try to acquire
the same port lock and we will deadlock.
Reviewed-by:
On Mon, Mar 24, 2014 at 12:15:23PM +0200, Jyri Sarha wrote:
This patch is implemented on top of late patches from Jean-Francois
Moine [1].
Applied both, thanks.
signature.asc
Description: Digital signature
Hi,
On Wed, Mar 26, 2014 at 08:47:15PM -0400, Peter Hurley wrote:
[ +to Marcel Holtmann ]
On 03/20/2014 03:30 PM, Felipe Balbi wrote:
LDISCs shouldn't call tty-ops-write() from within
-write_wakeup().
-write_wakeup() is called with port lock taken and
IRQs disabled, tty-ops-write() will
Hi,
On Wed, Mar 26, 2014 at 08:39:11PM -0400, Peter Hurley wrote:
On 03/25/2014 02:28 PM, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [140320 12:39]:
This reverts commit 0324a821029e1f54e7a7f8fed48693cfce42dc0e.
That commit tried to fix a deadlock problem when using
hci_ldisc, but it
On 03/26/2014 10:09 PM, Felipe Balbi wrote:
I just noticed this patch wasn't addressed to Marcel;
seems like this should go through the bluetooth tree (but not
through bluetooth-next because it fixes an oops).
read the archives:
http://marc.info/?l=linux-bluetoothm=139534449409583w=2
Sorry.
On 03/26/2014 10:10 PM, Felipe Balbi wrote:
Hi,
On Wed, Mar 26, 2014 at 08:39:11PM -0400, Peter Hurley wrote:
On 03/25/2014 02:28 PM, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [140320 12:39]:
This reverts commit 0324a821029e1f54e7a7f8fed48693cfce42dc0e.
That commit tried to fix a
On 03/25/2014 02:28 PM, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [140320 12:39]:
This reverts commit 0324a821029e1f54e7a7f8fed48693cfce42dc0e.
That commit tried to fix a deadlock problem when using
hci_ldisc, but it turns out the bug was in hci_ldsic
all along where it was calling
Hi,
On Wed, Mar 26, 2014 at 10:20:15PM -0400, Peter Hurley wrote:
You may want to build on top of this patch split handling;
I noticed some of the protocol drivers are calling
hci_uart_tx_wakeup() from work functions already (so don't
need to schedule another work...)
I don't think that
Hi,
On Wed, Mar 26, 2014 at 10:27:13PM -0400, Peter Hurley wrote:
On 03/26/2014 10:10 PM, Felipe Balbi wrote:
Hi,
On Wed, Mar 26, 2014 at 08:39:11PM -0400, Peter Hurley wrote:
On 03/25/2014 02:28 PM, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [140320 12:39]:
This reverts commit
On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Hi Kishon,
Long time no see! I added trivial
On Thursday 27 March 2014 09:13 AM, Jingoo Han wrote:
On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I
38 matches
Mail list logo
