In ARM: dts: am33xx: correcting dt node unit address for usb, the
usb_ctrl_mod and cppi41dma nodes were updated with the correct register
addresses. However, the dts files that reference these nodes were not
updated, and those devices are no longer being enabled.
This patch corrects the
Add compatible property for omap hdq driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
.../devicetree/bindings/hdq1w/omap_hdq.txt | 20
drivers/w1/masters/omap_hdq.c |8
2 files changed, 28 insertions(+)
create mode
This series adds support for HDQ/1w protocol driver for
am43x epos evm where it can be used for measuring the
temperature of a slave device connected to a particular header.
Tested the patch series on AM437x, hdq master and slave devices are
getting registered and interrupts are getting triggered
For SOCs with dt enabled, device should be build through device tree.
Prevent device build call from platform code, if device tree is
enabled.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/hdq1w.c |2 ++
1 file changed, 2 insertions(+)
diff --git
The patch adds the following to the omap hdq driver.
1. HDQ Device reset call in probe.
2. Enabling '1 wire mode' and checking for presence pulse bit.
3. Proper disabling and enabling of interrupts during read path.
4. Add re-initialization code during SKIP ROM command execution.
5. Miscellaneous
These adds hwmod data for hdq/1w driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 36
arch/arm/mach-omap2/prcm43xx.h |1 +
2 files changed, 37 insertions(+)
diff --git
Add device tree nodes and pinmux for hdq/1wire on
am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 10 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 12
2 files changed, 22 insertions(+)
diff --git
On 04/14/2014 05:32 PM, Sekhar Nori wrote:
Yes, you can. But as soon as you have other devices using the same priority
(with eDMA3 at least) and asks for a 'long' transfer it can ruin the audio.
During audio playback/capture you execute a long MMC read for example can
introduce a glitch.
The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.
The DESHDCP clock is enabled/disabled at the DSS boundary by the bit
DSS_DESHDCP_CLKEN in
The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.
This is because the DSS IP is designed in such a way that if DES-HDCP block
can't transition from idle
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the
CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register
fields which configure clocks. The remainder of the registers are related to
pad configurations or cross-bar configurations, and therefore
The control module isn't actually a clock management module, but there are a few
register bits which perform gating and muxing of clocks.
Add CTRL_MODULE_CORE sub block as a clock provider for DRA7. The control module
has 2 sub modules: CTRL_MODULE_CORE, and CTRL_MODULE_WKUP. Out of these, only
On Tue, Apr 15, 2014 at 12:51:43PM -0500, Joel Fernandes wrote:
On 04/15/2014 12:18 PM, Nishanth Menon wrote:
On 04/15/2014 12:06 PM, Joachim Eastwood wrote:
On 15 April 2014 18:58, Nishanth Menon n...@ti.com wrote:
pm_runtime_get_sync may not always succeed depending on SoC involved.
So
On Wed, Apr 16, 2014 at 1:56 AM, Tony Lindgren t...@atomide.com wrote:
* Grazvydas Ignotas nota...@gmail.com [140414 15:51]:
On Fri, Apr 11, 2014 at 2:47 AM, Tony Lindgren t...@atomide.com wrote:
@@ -282,6 +283,7 @@ void omap_sram_idle(void)
/* CORE */
if (core_next_state
Hi Laurent,
On Fri, Apr 04, 2014 at 12:11:52AM +0200, Laurent Pinchart wrote:
Laurent Pinchart (3):
iommu/omap: Fix 'no page for' debug message in flush_iotlb_page()
iommu/omap: Remove comment about supporting single page mappings only
iommu/omap: Fix map protection value
Hi,
On Tue, Apr 15, 2014 at 06:24:11PM +0530, Vivek Gautam wrote:
I had seen your patches in the mailing list, but i don't see any
updated version of these patches.
Are you planning to work on this above mentioned patch-series any time soon ?
I'm sorry, I forgot this completely. I have not
Hi Joerg,
On Wednesday 16 April 2014 16:01:07 Joerg Roedel wrote:
Hi Laurent,
On Fri, Apr 04, 2014 at 12:11:52AM +0200, Laurent Pinchart wrote:
Laurent Pinchart (3):
iommu/omap: Fix 'no page for' debug message in flush_iotlb_page()
iommu/omap: Remove comment about supporting
Hi Joerg,
The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5:
Linux 3.15-rc1 (2014-04-13 14:18:35 -0700)
are available in the git repository at:
git://linuxtv.org/pinchartl/media.git iommu/omap
for you to fetch changes up to
Hi Joerg,
Last but not least, could you please provide a stable branch with those
patches, directly on top of v3.15-rc1 ? I'll need to base OMAP3 ISP driver
patches on top of it.
On Wednesday 16 April 2014 16:51:56 Laurent Pinchart wrote:
Hi Joerg,
The following changes since commit
TRM says we *must* write 1 to each bit we're handling
in order to clear the IRQ status and bring IRQ line
low. This patch implements that.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Russell, I don't have HW to test, but this should
solve the problem you saw when not using battery
with Zoom
On 04/16/2014 07:59 AM, Peter Ujfalusi wrote:
[..]
If the dma-priority is missing we should assume lowest priority (0).
The highest priority depends on the platform. For eDMA3 in AM335x it is
three
level. For designware controller you might have the range 0-8 as valid.
The question is how
On 16 April 2014 07:40, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On 15/04/14 20:36, Joachim Eastwood wrote:
Hello,
I am trying to get HDMI work with DT on my VAR-STK-OM44 (4460) board.
But during kernel boot I get the following message:
[ 0.953796] [ cut here ]
[
On Fri, Oct 11, 2013 at 05:46:12PM +0300, Roger Quadros wrote:
Hi,
On 10/10/2013 01:49 PM, Kishon Vijay Abraham I wrote:
From: George Cherian george.cher...@ti.com
Added dr_mode property in dwc3 and set its default mode to device.
If there is a specific reason why this is not set to
On Wed, Apr 16, 2014 at 11:16:19AM -0500, Felipe Balbi wrote:
On Fri, Oct 11, 2013 at 05:46:12PM +0300, Roger Quadros wrote:
Hi,
On 10/10/2013 01:49 PM, Kishon Vijay Abraham I wrote:
From: George Cherian george.cher...@ti.com
Added dr_mode property in dwc3 and set its default
* Felipe Balbi ba...@ti.com [140416 08:18]:
TRM says we *must* write 1 to each bit we're handling
in order to clear the IRQ status and bring IRQ line
low. This patch implements that.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Russell, I don't have HW to test, but this should
solve the
On 04/14/2014 06:41 AM, Peter Ujfalusi wrote:
Hi,
Changes since v2:
- Dropped patch 10 from v2 (simplify direction configuration...)
- Dropped the channel priority related patches since we are going to go via
different route for configuring the priority.
- Added ACK from Joel for the
On Wed, Apr 16, 2014 at 04:51:56PM +0200, Laurent Pinchart wrote:
The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5:
Linux 3.15-rc1 (2014-04-13 14:18:35 -0700)
are available in the git repository at:
git://linuxtv.org/pinchartl/media.git iommu/omap
for
Move mode (Host, Peripheral, OTG) initialization
to its own function in order to decrease the size
of our probe() routine.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/dwc3/core.c | 133
1 file changed, 67 insertions(+), 66
no functional changes, just renaming the function
in order to make it slightly clearer what it should
be used for, also matching the driver name.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/dwc3/dwc3-exynos.c| 6 ++---
drivers/usb/dwc3/dwc3-pci.c | 6 ++---
now that all functions match the driver name,
the only missing piece is to rename the header
file itself.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/dwc3/dwc3-exynos.c | 2 +-
drivers/usb/dwc3/dwc3-pci.c | 2 +-
so it seems like DWC3 IP doesn't clear stalls
automatically when we disable an endpoint, because
of that, we _must_ make sure stalls are cleared
before clearing the proper bit in DALEPENA register.
Cc: sta...@vger.kernel.org # v3.4+
Reported-by: Johannes Stezenbach j...@sig21.net
Signed-off-by:
it's now very easy to return a platform_device pointer
and have the caller pass it as argument when calling
usb_phy_generic_unregister().
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/musb/am35x.c| 12 +---
drivers/usb/musb/blackfin.c | 10 --
This patch is in preparation to supporting
calling those functions multiple times.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/musb/am35x.c| 4 ++--
drivers/usb/musb/blackfin.c | 6 +++---
drivers/usb/musb/da8xx.c| 4 ++--
drivers/usb/musb/davinci.c | 4 ++--
our probe() routine is too large and we can
easily refactor PHY-related code out to another
function to make it slightly less painful to read.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/dwc3/core.c | 120 ++--
1 file changed, 66
We only support GPL drivers in the USB Gadget Framework,
it sounds correct to make all exported symbols GPL too.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/usb/gadget/configfs.c | 2 +-
drivers/usb/gadget/f_fs.c | 6 ++---
drivers/usb/gadget/f_rndis.c| 2 +-
Hi folks,
I have been playing with following patches today and
I think they're ready to be queued up for v3.16 but
I wanted to get some comments/test results before
I apply them to my 'next' branch.
Thanks
Felipe Balbi (8):
usb: dwc3: gadget: clear stall when disabling endpoint
usb: dwc3:
Hi Joerg,
On Wednesday 16 April 2014 21:31:58 Joerg Roedel wrote:
On Wed, Apr 16, 2014 at 04:51:56PM +0200, Laurent Pinchart wrote:
The following changes since commit
c9eaa447e77efe77b7fa4c953bd62de8297fd6c5:
Linux 3.15-rc1 (2014-04-13 14:18:35 -0700)
are available in the git
Here are some minor cleanups for dmtimer code in preparation for moving it out
to drivers.
There is OMAP1 specific dmtimer code earlier, that are handled in mach-omap1
directly now. Other than this, few functions and code has been refactored to
reduce redundancy and some minor cleanups.
OMAP1
OMAP1 doesn't support clock framework, add a comment where needed
and correct a FIXME.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/plat-omap/dmtimer.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c
load_start implies start, so it makes sense to set the ST bit in
__omap_dm_timer_load_start instead of callers.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/mach-omap2/timer.c |6 +++---
arch/arm/plat-omap/dmtimer.c |1 -
The subsequent devm_ioremap_resource will catch it and print an error, let it
be checked there.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/plat-omap/dmtimer.c |4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index
Inorder to move non-DM timer specific code that modifies the idlect
mask on OMAP1, from dmtimer code, to OMAP1 specific timer initialization code,
we introduce a new function that can possibly be reused for other purposes in
the future. The function just checks if a timer is running based on the
While at it, also delete the old definition of the function in dmtimer.c code.
This completes the separation and removal of OMAP1 header dependency in dmtimer
code and removes references to MOD_CONF_CTRL registers in dmtimer.
Signed-off-by: Joel Fernandes jo...@ti.com
---
Simplify the check for a timer availability in atleast 4 places by providing a
function to do the same.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git
There is a platform specific hook just for OMAP1 to set its clk parent. Remove
this hook and have OMAP1 set its parent in omap1_dm_timer_init. If OMAP1 is
ever migrated to clock framework, the correct way to do this would be through
clk_set_parent like other platforms.
Signed-off-by: Joel
A common pattern in dmtimer code is to read the control reg, set and reset
certain bits, and write it back. We abstract this pattern and introduce a
new function to do so.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 63
Once clock-parents or default-parent support for DT clocks is available,
we should use it to set clock parent and turn clk_set_parent into a NOOP.
Signed-off-by: Joel Fernandes jo...@ti.com
---
arch/arm/plat-omap/dmtimer.c |4
1 file changed, 4 insertions(+)
diff --git
The vchan lock in edma_callback is acquired in hard interrupt context. As
interrupts are already disabled, there's no point in save/restoring interrupt
mask bit or cpsr flags.
Get rid of flags local variable and use spin_lock instead of spin_lock_irqsave.
Signed-off-by: Joel Fernandes
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