On 29 September 2014 11:32, Andreas Fenkart afenk...@gmail.com wrote:
v2:
- replace erroneous mmci by omap1/2
- add description to all patches
- full compile check with:
CONFIG_MACH_OMAP3_BEAGLE=y
CONFIG_MACH_DEVKIT8000=y
CONFIG_MACH_OMAP_LDP=y
On 09/29/2014 02:06 PM, Sebastian Andrzej Siewior wrote:
The queue is getting smaller. The highlights of v9…v10
- the DMA stall Frans Klaver reported which popped up in yocto is gone. It
also seems that the ack the err-irq even if nothing happened in EDMA
can be dropped.
- the RX- and
Hi,
OMAP3+ DPLL code is currently using set_rate op to change DPLL rates.
This is kind of wrong, as it also involves changing DPLL parent in certain
cases (switch between locked mode - bypass mode.) This set fixes these
issues by introducing the support of determine_rate and set_rate_and_parent
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the
Currently, DPLL code hides the re-parenting within its internals, which
is wrong. This needs to be exposed to the common clock code via
determine_rate and set_rate_and_parent APIs. This patch adds support
for these, which will be taken into use in the following patches.
Signed-off-by: Tero Kristo
DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.
Signed-off-by: Tero Kristo
Expand the support of omap4 per-dpll to provide set_rate_and_parent.
This is required for proper behavior of clk_change_rate with
determine_rate support.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock3xxx.c | 36
Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock
type is wrong. This patch adds basic functionality for determine_rate
for this clock type which will be taken into use in the patches following
later.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
On Thu, Oct 02, 2014 at 04:59:30PM -0500, Felipe Balbi wrote:
Hi,
On Thu, Oct 02, 2014 at 02:19:08PM -0700, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [141002 13:18]:
On Thu, Oct 02, 2014 at 12:52:38PM -0700, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [141002 09:36]:
* Felipe Balbi ba...@ti.com [141003 07:53]:
On Thu, Oct 02, 2014 at 04:59:30PM -0500, Felipe Balbi wrote:
On Thu, Oct 02, 2014 at 02:19:08PM -0700, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [141002 13:18]:
On Thu, Oct 02, 2014 at 12:52:38PM -0700, Tony Lindgren wrote:
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
drivers/clk/ti/clk-44xx.c | 1 -
drivers/clk/ti/clk-54xx.c | 1 -
drivers/clk/ti/clk-7xx.c | 1 -
include/linux/clk/ti.h| 1 +
4 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c
On 10/02, Tomeu Vizoso wrote:
Moves clock state to struct clk_core, but takes care to change as little API
as
possible.
struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.
The struct clk that
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