Hi Vignesh,
On Fri, Jul 17, 2015 at 12:10:40PM +0530, Vignesh R wrote:
> On am437x-gp-evm, pixcir touchscreen can wake the system from low power
> state by generating wake-up interrupt via pinctrl and IO daisy chain.
> Add support for optional wakeup interrupt source by regsitering to
> automated
From: Suman Anna
Add the Wakeup M3 IPC node for the wkup_m3_ipc driver on AM33xx SoCs.
This node uses the IPC registers, part of the Control Module, and is
therefore added as a child of the scm node.
Signed-off-by: Suman Anna
Signed-off-by: Dave Gerlach
---
arch/arm/boot/dts/am33xx.dtsi | 8 +
From: Keerthy
Add ti,mbox-send-noirq to wkup_m3 mailbox so that messages using
wkup_m3 mailbox are sent without triggering any further interrupts.
This is required to be able to send multiple messages to the WkupM3
after the mailbox usage logic adjustment in the wkup_m3_ipc driver.
Signed-off-by
From: Suman Anna
Add the Wakeup M3 IPC device node for the wkup_m3_ipc driver on
AM4372 SoC. This node uses the IPC registers, part of the Control
Module, and is therefore added as a child of the scm node.
Signed-off-by: Suman Anna
Signed-off-by: Dave Gerlach
---
arch/arm/boot/dts/am4372.dtsi
Hi,
This series adds the necessary dt nodes for the wkup_m3_ipc on am335x
and am437x and also adds the ti,mbox-send-noirq flag to the wkup_m3
mailbox on both platforms as well so that we can use mailbox from
noirq context when needed. This series is to make use of the
driver introduced here [1].
Add ti,mbox-send-noirq to wkup_m3 mailbox so that messages using
wkup_m3 mailbox are sent without triggering any further interrupts.
This is needed to achieve lower power numbers during CPU idle on
AM33xx.
Signed-off-by: Dave Gerlach
[s-a...@ti.com: revise commit description]
Signed-off-by: Suman
Add the device tree bindings document for the TI Wakeup M3 IPC
device on AM33xx and AM43xx SoCs. These devices are used by the
TI wkup_m3_ipc driver, and contain the registers upon which the
IPC protocol to communicate with the Wakeup M3 processor is
implemented.
Signed-off-by: Dave Gerlach
Signe
Introduce a wkup_m3_ipc driver to handle communication between the MPU
and Cortex M3 wkup_m3 present on am335x.
This driver is responsible for actually booting the wkup_m3_rproc and
also handling all IPC which is done using the IPC registers in the control
module, a mailbox, and a separate interru
The mailbox framework controls the transmission queue and requires
either its controller implementations or clients to run the state
machine for the Tx queue. The OMAP mailbox controller uses a Tx-ready
interrupt as the equivalent of a Tx-done interrupt to run this Tx
queue state-machine.
The Wkup
Hi,
This series is version 2 of the code to introduce a wkup_m3_ipc driver
to handle communication between the MPU and Cortex M3 present on TI AM335x
and AM437x SoCs. v1 of this series can be found at [1]. Changes include:
- Buildable as a module
- Added am437x support
- Various cleanups and fixe
* Grazvydas Ignotas [150717 04:24]:
> On Fri, Jul 17, 2015 at 7:54 AM, Tony Lindgren wrote:
> > * Tony Lindgren [150716 09:28]:
> >> * Grazvydas Ignotas [150716 07:16]:
> >> > Hi,
> >> >
> >> > On Thu, Jul 16, 2015 at 2:59 PM, Tony Lindgren wrote:
> >> > > We've been moving all omap2+ based sy
This register is required to be passed to the SATA PHY driver
to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dr
SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
between a SATA DPLL unlock and re-lock to prevent SATA lockup.
Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
regmap access to this register which sits in the control module.
If the register is not provided we fal
scm_conf1 maps the control register address space after the
padconf till the end.
Fix the scm_conf and pmx_core resource lengths. We need to add
4 bytes to include the last 32-bit register space.
Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
They are not used by anyone and no l
* Sebastian Reichel [150717 01:29]:
> Hi,
>
> On Thu, Jul 16, 2015 at 04:59:09AM -0700, Tony Lindgren wrote:
> > I think we can drop these now. This just leaves n900 and ldp with
> > n900 pending patches for legacy proc support.
>
> So I guess n900 board file removal depends on the atag procfs
>
Hi,
Implement workaround for SATA errata i783 (SATA Lockup After SATA DPLL
Unlock/Relock)
so that we can now turn off sata_refclk to support suspend-to-ram without
preventing
core-retention.
Depends on http://article.gmane.org/gmane.linux.ports.arm.omap/126670.
Changelog:
v3:
- used scm_conf n
Hi Li,
On 17/07/15 10:48, Li Jun wrote:
> Hi, Roger
>
> On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
>> The OTG core instantiates the OTG Finite State Machine
>> per OTG controller and manages starting/stopping the
>> host and gadget controllers based on the bus state.
>>
>> It
Hook omap_hwmod_rtc_unlock/lock functions into RTC hwmod,
so that SYSCONFIG register is updated properly
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap
RTC IP have kicker feature which prevents spurious writes to its registers.
In order to write into any of the RTC registers, KICK values has to be
written to KICK registers.
Introduce omap_hwmod_rtc_unlock/lock functions, which writes into these
KICK registers inorder to lock and unlock RTC regist
Hook omap_hwmod_rtc_unlock/lock functions into RTC hwmod,
so that SYSCONFIG register is updated properly.
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock
This series implements lock and unlock functions for RTC and hooks
the same to DRA7 and AMx3xx hwmod.
This is dependent on the patch https://patchwork.kernel.org/patch/6578281/,
which is queued recently by Paul.
Tested on DRA72-evm: http://pastebin.ubuntu.com/11892356/
Lokesh Vutla (3):
ARM: hw
Hi Sascha,
Sascha Hauer writes:
> The thermal code uses int, long and unsigned long for temperatures
> in different places.
>
> Using an unsigned type limits the thermal framework to positive
> temperatures without need. Also several drivers currently will report
> temperatures near UINT_MAX for
On Fri, Jul 17, 2015 at 7:54 AM, Tony Lindgren wrote:
> * Tony Lindgren [150716 09:28]:
>> * Grazvydas Ignotas [150716 07:16]:
>> > Hi,
>> >
>> > On Thu, Jul 16, 2015 at 2:59 PM, Tony Lindgren wrote:
>> > > We've been moving all omap2+ based systems to boot in device tree only
>> > > mode for a
On 13/07/15 04:39, Peter Chen wrote:
> On Fri, Jul 10, 2015 at 04:06:43PM +0800, Li Jun wrote:
>> On Wed, Jul 08, 2015 at 01:19:28PM +0300, Roger Quadros wrote:
>>> Move the state_changed variable into struct otg_fsm
>>> so that we can support multiple instances.
>>>
>> I am not sure if multiple in
On 17/07/15 12:02, Li Jun wrote:
> On Wed, Jul 08, 2015 at 01:19:36PM +0300, Roger Quadros wrote:
>
> [...]
>
>> struct otg_fsm *usb_otg_register(struct device *parent_dev,
>> - struct otg_fsm_ops *fsm_ops)
>> + struct otg_fsm_ops *fsm_ops,
On 17/07/15 11:14, Li Jun wrote:
> Hi,
>
> On Wed, Jul 08, 2015 at 01:19:36PM +0300, Roger Quadros wrote:
>> DRD mode is a reduced functionality OTG mode. In this mode
>> we don't support SRP, HNP and dynamic role-swap.
>>
>> In DRD operation, the controller mode (Host or Peripheral)
>> is decided
On 16/07/15 21:29, Andrew Bresticker wrote:
> Hi Roger,
>
> On Wed, Jul 15, 2015 at 6:26 AM, Roger Quadros wrote:
>> Hi Andrew,
>>
>> On 13/07/15 22:14, Andrew Bresticker wrote:
>>> Hi Roger,
>>>
>>> On Wed, Jul 8, 2015 at 3:19 AM, Roger Quadros wrote:
Usage model:
---
>>>
On Wed, Jul 08, 2015 at 01:19:36PM +0300, Roger Quadros wrote:
[...]
> struct otg_fsm *usb_otg_register(struct device *parent_dev,
> - struct otg_fsm_ops *fsm_ops)
> + struct otg_fsm_ops *fsm_ops,
> + bool drd
Hello,
adding linux-iio...
> To get a chance of this patch being considered for inclusion, you
> should send this to the maintainers of the phy and iio framework.
> There is a high chance, that none of them will see your mail.
>
> On Thu, Jul 16, 2015 at 03:20:27PM -0700, Adam YH Lee wrote:
> >
Hi,
On Wed, Jul 08, 2015 at 01:19:36PM +0300, Roger Quadros wrote:
> DRD mode is a reduced functionality OTG mode. In this mode
> we don't support SRP, HNP and dynamic role-swap.
>
> In DRD operation, the controller mode (Host or Peripheral)
> is decided based on the ID pin status. Once a cable p
Hi,
To get a chance of this patch being considered for inclusion, you
should send this to the maintainers of the phy and iio framework.
There is a high chance, that none of them will see your mail.
On Thu, Jul 16, 2015 at 03:20:27PM -0700, Adam YH Lee wrote:
> MADC[3:6] reads incorrect values wit
Hi, Roger
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
> The OTG core instantiates the OTG Finite State Machine
> per OTG controller and manages starting/stopping the
> host and gadget controllers based on the bus state.
>
> It provides APIs for the following tasks
>
> - Regist
Hi,
On Thu, Jul 16, 2015 at 04:59:09AM -0700, Tony Lindgren wrote:
> I think we can drop these now. This just leaves n900 and ldp with
> n900 pending patches for legacy proc support.
So I guess n900 board file removal depends on the atag procfs
support in DT. What's the problem with ldp? Its DT f
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