Hi Paul,
On 04/11/2012 07:44 PM, Paul Walmsley wrote:
Cc Mark Greer, Mark Salter
Hi Greg, Aneesh,
On Sat, 17 Mar 2012, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2
: Aneesh V
---
v2:
- replaced __init with __init_or_module
v1:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data/emif_plat.h
and the other part is
Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature polling
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2
On Saturday 17 March 2012 03:03 AM, Greg KH wrote:
On Sat, Mar 17, 2012 at 02:28:47AM +0530, Aneesh V wrote:
Hi Greg,
[...]
I have fixed these comments and pushed my latest patches at:
git://github.com/aneeshv/linux.git
branch: emif-upstream-v4
Sorry, but I don't take git pulls for
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2:
- Corrected the frequency value shown in
register cache dump
- replaced __init with
going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2:
- replaced __init with __init_or_module
v1:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v1:
- Added comment in commit log as well as code about
missing integration part that needs to be done in
future
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH
Signed-off-by: Aneesh V
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same file in subsequent
patches
---
drivers
.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
this patch is used currently
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline
v1:
- Moved to /lib from /dr
a hwmod series [1] that adds hwmod for EMIF
- Converted instances of __init to __init_or_module
[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions for EMIF
misc: emif: add basic infrastr
On Saturday 17 March 2012 03:13 AM, Greg KH wrote:
On Sat, Mar 17, 2012 at 02:20:07AM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data
Hi Greg,
On Friday 16 March 2012 12:32 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data
.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
this patch is used currently
v3:
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline
v1:
- Moved to /lib from /dr
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH
Signed-off-by: Aneesh V
---
v3:
- Converted
On Friday 16 March 2012 12:34 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:30PM +0530, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds
On Friday 16 March 2012 12:32 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data
Cc: Rajendra Nayak
Cc: Benoit Cousson
Cc: Grant Likely
Signed-off-by: Aneesh V
---
v2:
- Addressed comments from Grant Likely:
Converted occurences of __init to __init_or_module
Removed un-necessary instances of #ifdef CONFIG_OF
- Rebased to v2 of EMIF driver series
v1:
- Rebased to the
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Cc: Grant Likely
Signed-off-by: Aneesh V
---
v1:
- Removed DDR3 only parameters from
elpida_ecb240abacn.dtsi
---
arch/arm/boot/dts
Likely
Signed-off-by: Aneesh V
---
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation/devicetree
on
Cc: Grant Likely
Signed-off-by: Aneesh V
---
v1:
- Removed two DDR3 only timing parameters that were
inadvertently added in the binding
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102
mp;m=133183554007498&w=2
Cc: Rajendra Nayak
Cc: Benoit Cousson
Cc: Grant Likely
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
arm: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
misc: emif: add device tr
Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature polling
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2:
- Corrected the frequency value shown in
register cache dump
- replaced __init with
going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v2:
- replaced __init with __init_or_module
v1:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH
Signed-off-by: Aneesh V
---
v1:
- Added comment in commit log as well as code about
missing integration part that needs to be done in
future
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH
Signed-off-by: Aneesh V
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same file in subsequent
patches
---
drivers
: Aneesh V
---
v2:
- replaced __init with __init_or_module
v1:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data/emif_plat.h
and the other part is
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH
Signed-off-by: Aneesh V
---
v1:
- Moved to /lib
e.org/gmane.linux.ports.arm.omap/72855
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions for EMIF
misc: emif: add basic infrastructure for EMIF driver
misc: emif: handle frequency and voltage change events
misc: emif: add interrupt and temperature handling
misc: emif
Hi Grant,
On Friday 09 March 2012 11:07 AM, Grant Likely wrote:
On Thu, 8 Mar 2012 22:03:57 +0530, Aneesh V wrote:
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
Changes since RFC v4:
- Rebased to the latest version of EMIF series
- Replace kzalloc()/kfree() with devm_
On Friday 09 March 2012 02:29 AM, Greg KH wrote:
On Thu, Mar 08, 2012 at 09:24:17PM +0530, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds
On Thursday 08 March 2012 10:11 PM, Cousson, Benoit wrote:
Hi Aneesh
On 3/8/2012 4:54 PM, Aneesh V wrote:
From: Benoit Cousson
Add hwmod data for EMIF IP instances in OMAP4.
Paul has just posted an OMAP4 hwmod series (ARM: OMAP4: hwmod data: add
almost all remaining IP blocks) that does
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
Changes since RFC v4:
- Rebased to the latest version of EMIF series
- Replace kzalloc()/kfree() with devm_* variants
---
drivers/misc/emif.c | 289 ++-
1 files changed, 288
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
Changes since RFC v4:
- Removed DDR3 only parameters from
elpida_ecb240abacn.dtsi
---
arch/arm/boot/dts
-by: Aneesh V
---
Changes sice RFC v4:
- None
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation
device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.
The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings'
for specifying the AC timing parameters of the memory device at
different speed-bins.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Sig
42&w=2
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
arm: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
misc: emif: add device tree support to emif driver
.../devicetree/bindings/lpddr2/lpddr
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH
Signed-off-by: Aneesh V
---
Changes since RFC:
- None
---
drivers/misc/emif.c | 138
doesn't have DVFS support yet,
testing was done using a test module.
- Temperature alert handling was tested with simulated interrupts
and faked temperature values as testing all cases in real-life
scenarios is difficult.
- Tested the driver as a module
Cc: Greg KH
Aneesh V (7):
misc
Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature polling
Cc: Greg KH
Signed-off-by: Aneesh V
going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH
Signed-off-by: Aneesh V
---
Changes since RFC:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211 ++-
1 files
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH
Signed-off-by: Aneesh V
---
Changes since RFC:
- Added comment in commit log as well as code about
missing integration part that needs to be
: Aneesh V
---
Changes since RFC:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data/emif_plat.h
and the other part is now merged in drivers/misc
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH
Signed-off-by: Aneesh V
---
Changes since RFC:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same file in subsequent
patches
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH
Signed-off-by: Aneesh V
---
Changes since RFC
From: Benoit Cousson
Add hwmod data for EMIF IP instances in OMAP4.
Signed-off-by: Benoit Cousson
---
Changes since RFC:
- Improved commit log
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 110
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/ar
On Thursday 16 February 2012 10:00 PM, Cousson, Benoit wrote:
Hi Aneesh,
[...]
+struct emif_data {
+ u8 duplicate;
+ u8 temperature_level;
+ u32 irq;
+ spinlock_t
On Saturday 04 February 2012 06:12 PM, Aneesh V wrote:
This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and other details of LPDDR2 memories.
Ping! Any comments on this series?
br,
Aneesh
--
To
On Friday 17 February 2012 11:20 PM, Greg KH wrote:
On Fri, Feb 17, 2012 at 07:26:29PM +0530, Aneesh V wrote:
[...]
I don't know what any of those TLA words mean, so I really can't suggest
This is a driver for TI's memory controller(called EMIF). The
driver is needed fo
On Friday 17 February 2012 07:14 PM, Cousson, Benoit wrote:
Hi Aneesh,
[...]
+ emif = kzalloc(sizeof(struct emif_data), GFP_KERNEL);
You should use the devm_* version of this API to get the simplify the
error handling / removal.
Please note that most of my allocations are happening throug
Greg,
On Thursday 16 February 2012 09:53 PM, Greg KH wrote:
On Thu, Feb 16, 2012 at 04:21:11PM +0530, Santosh Shilimkar wrote:
Andrew, Greg,
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that
Hi Benoit,
On Thursday 16 February 2012 10:00 PM, Cousson, Benoit wrote:
Hi Aneesh,
On 2/4/2012 1:16 PM, Aneesh V wrote:
EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.
Add the basic
On Thursday 16 February 2012 04:14 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add settings that are not dependent on frequency
or any other transient parameters
Expand the changelog a bit. One time settings like
SDRAM_CONFIG, PHY_CONTROL, TEMP alert
On Thursday 16 February 2012 04:40 PM, Alan Cox wrote:
On Thu, 16 Feb 2012 15:57:57 +0530
Aneesh V wrote:
On Thursday 16 February 2012 03:37 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes
On Thursday 16 February 2012 04:11 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add an ISR for EMIF that:
1. reports details of access errors
2. takes action on thermal events
On thermal events SDRAM timing parameters are
adjusted to
On Thursday 16 February 2012 04:08 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs
On Thursday 16 February 2012 04:03 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.
Add the basic
On Thursday 16 February 2012 03:40 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Signed-off-by: Aneesh V
---
drivers/misc/emif_regs.h | 461 ++
1 files changed, 461 insertions(+), 0 deletions(-)
create mode
On Thursday 16 February 2012 03:37 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data
Santosh,
Thanks for the review.
On Thursday 16 February 2012 03:32 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
From: Benoit Cousson
One line of change log will do here.
Ok. Will add.
br,
Aneesh
--
To unsubscribe from this list: send the line
On Thursday 09 February 2012 04:55 PM, Bedia, Vaibhav wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of V, Aneesh
Sent: Saturday, February 04, 2012 5:46 PM
To: linux-omap@vger.kernel.org
Cc: linux-ker...@vger.kernel.or
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
drivers/misc/emif.c | 281 ++-
1 files changed, 280 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index f67a9e7..2fc0813 100644
--- a
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 71 +
arch/arm/boot/dts/omap4-panda.dts
-by: Aneesh V
---
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation/devicetree/bindings/memory
device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.
The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings'
for specifying the AC timing parameters of the memory device at
different speed-bins.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Sig
* Incorporated review comments from Olof
Changes from RFC v3 to RFC v4:
* Added a new patch to add DT support in the EMIF driver
[1] http://marc.info/?l=linux-omap&m=132835811606125&w=2
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI'
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Signed-off-by: Aneesh V
---
drivers/misc/emif.c | 129 +++
1 files changed, 129 insertions
Add settings that are not dependent on frequency
or any other transient parameters
Signed-off-by: Aneesh V
---
drivers/misc/emif.c | 147 +++
1 files changed, 147 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc
-by: Aneesh V
---
drivers/misc/emif.c | 209 ++-
1 files changed, 207 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 36ba6f4..5c2b0ae 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -500,6
Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping), temperature level etc.
Signed-off-by: Aneesh V
---
drivers/misc
EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.
Add the basic infrastructure for EMIF driver that includes
driver registration, probe, parsing of platform data etc.
Signed-off-by: Aneesh V
Signed-off-by: Aneesh V
---
drivers/misc/emif_regs.h | 461 ++
1 files changed, 461 insertions(+), 0 deletions(-)
create mode 100644 drivers/misc/emif_regs.h
diff --git a/drivers/misc/emif_regs.h b/drivers/misc/emif_regs.h
new file mode 100644
index
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Signed-off-by: Aneesh V
---
drivers/misc/Kconfig
From: Benoit Cousson
Signed-off-by: Benoit Cousson
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 110
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index
g was done using a test module.
- Temperature alert handling was tested with simulated interrupts
and faked temperature values as testing all cases in real-life
scenarios is difficult.
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions for EMIF
misc:
Hi Catalin,
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
On Fri, Jan 20, 2012 at 08:57:11AM +, Joe Woodward wrote:
So I re-iterate that we need to have solution to this problem.
... I don't want to be a pain, but it seems to me that this dicussion
didn't reach a full conclus
On Saturday 21 January 2012 12:58 PM, Olof Johansson wrote:
On Thu, Jan 19, 2012 at 12:56 PM, Aneesh V wrote:
Hi Olof,
On Friday 20 January 2012 01:01 AM, Olof Johansson wrote:
Hi,
Sorry for the delay in responding, I know you pinged me about it
yesterday.
On Thu, Jan 19, 2012 at 6:31 AM
Hi Olof,
On Friday 20 January 2012 01:01 AM, Olof Johansson wrote:
Hi,
Sorry for the delay in responding, I know you pinged me about it yesterday.
On Thu, Jan 19, 2012 at 6:31 AM, Aneesh V wrote:
device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.
The 'l
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Cc: Olof Johansson
Signed-off-by: Aneesh V
---
Changes in RFC v3:
* Fixed review comments from RFC v2
---
arch/arm/boot/dts
Johansson
Signed-off-by: Aneesh V
---
Changes in RFC v3:
* Fixed review comments from RFC v2
---
.../bindings/memory-controllers/ti/emif.txt| 49
1 files changed, 49 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory
Cc: Olof Johansson
Signed-off-by: Aneesh V
Changes in RFC v2:
* Removed the "manufacturer" property and added it in
compatible property instead
* Changed the DDR device names in example to indicate
the part number
Changes in RFC v3:
* Removed DDR3 support
* Fixed review comments
4 and LPDDR2 memories attached to them on various boards.
Thanks to Rajendra for answering my numerous queries on device tree.
Changes in RFC v3:
* Removed support for DDR3
* Incorporated review comments from Olof
Aneesh V (3):
dt: device tree bindings for DDR memories
dt: device tree bindings for
On Thursday 19 January 2012 07:58 PM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only DDR3 and LPDDR2 memories.
However, the bi
Device tree data for the EMIF sdram controllers in OMAP4
and DDR memories attached to OMAP4 boards.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 64 +
arch/arm/boot/dts/omap4-panda.dts
-by: Aneesh V
---
.../bindings/memory-controllers/ti/emif.txt| 62
1 files changed, 62 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation/devicetree/bindings/memory
x27;ddr-timings'
for specifying the AC timing parameters of the memory device
at different speed-bins.
Cc: Rajendra Nayak
Cc: Benoit Cousson
Signed-off-by: Aneesh V
Changes in RFC v2:
* Removed the "manufacturer" property and added it in
compatible property instead
* Changed the
a re-post of the RFC that was posted to devicetree-discuss ml,
now sent to a larger audience and looping out an internal list.
Please ignore the previous version.
Aneesh V (3):
dt: device tree bindings for DDR memories
dt: device tree bindings for TI's EMIF sdram controller
arm/dts: EMIF
Hi Olof,
On Tuesday 20 December 2011 12:39 PM, Aneesh V wrote:
Hi Olof,
On Monday 19 December 2011 10:22 PM, Olof Johansson wrote:
Hi,
Some comments below, but also a more general question: How much of
this generic data makes sense to encode in the device tree? Final
hardware configuration
On Tuesday 17 January 2012 07:11 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 12:27:25PM +, Aneesh V wrote:
Hi Catalin,
On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So, is the upshot of this that the
Hi Catalin,
On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So, is the upshot of this that the kernel isn't going to be in a
position to enable the L2/outer cache on OMAP3 (due to the need for
hacky/unmaintainable code)?
Hi Olof,
On Saturday 14 January 2012 01:06 AM, Aneesh V wrote:
Hi Olof,
We wish to drop the DDR3 support because we have concluded that our
platforms with DDR3 memories will not scale DDR frequency due to
limitations in DDR3 protocol(operating frequency can vary only in a
small range). So
Santosh, Russel,
On Monday 16 January 2012 06:52 PM, Shilimkar, Santosh wrote:
On Mon, Jan 16, 2012 at 2:13 PM, Russell King - ARM Linux
wrote:
On Mon, Jan 16, 2012 at 01:43:03PM +0100, Shilimkar, Santosh wrote:
This code will be in assembly and that's what I have
been using. Not having stac
Hi Olof,
On Monday 09 January 2012 11:12 AM, Olof Johansson wrote:
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh V wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
In general, is it
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime.
But we
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime.
But we can boot to userspace with bootloader set timings, so I'm
As
On Tuesday 20 December 2011 05:05 AM, Tony Lindgren wrote:
* Rob Herring [111219 14:29]:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currentl
On Tuesday 20 December 2011 04:31 AM, Rob Herring wrote:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for
On Monday 19 December 2011 10:29 PM, Olof Johansson wrote:
Oh wait, when I saw 3/3 I realized the following too:
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh V wrote:
+- phy-type : string indicating the phy type. Should be one of the
+ following:
+
+ "phy-type-omap4" : PHY use
On Monday 19 December 2011 10:26 PM, Olof Johansson wrote:
Hi,
Fewer comments here. :) But see below.
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh V wrote:
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,64 @@
+* EMIF family of TI SDRAM
ed by our driver to
re-configure our SDRAM controller during DVFS. In fact, I have not
listed all AC timing parameters in the spec in this binding, leaving
the rest for future users to add if they need them.
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh V wrote:
diff --git a/Documentation/devic
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