On 07/08/2013 02:28 AM, Felipe Balbi wrote:
On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote:
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: Nikhil
On 07/04/2013 01:26 AM, Ruchika Kharwar wrote:
DRA7XX has several USB OTG subsystems. USB_OTG_SS1 includes a USB1 and USB2
phy. USB_OTG_SS2 includes only a USB2 phy.
This patch allows the dwc3 probe to continue if a usb3_phy is not found.
The need for this will go away as soon
On 07/05/2013 08:32 AM, Sebastian Andrzej Siewior wrote:
The memory address contains three pieces that is the reset module which
is currently the only one used and two other pices which seem
interresting based on what the register.
Please fix typos pices.. interresting.. also the description
When there is an error with the usb3_phy probe or absence, the error returned
is erroneously for usb2_phy.
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
drivers/usb/dwc3/core.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3
-by: Ruchika Kharwar ruch...@ti.com
---
drivers/usb/dwc3/core.c | 38 --
drivers/usb/dwc3/gadget.c | 11 ---
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 358375e..feea92d
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
drivers/usb/phy/phy-omap-usb3.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/phy
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
drivers/usb/phy/phy-omap-usb3.c
Kishon,
What is the expectation when there is no palmas tied to dwc3/dwc3-omap ?
Thank you
Regards
Ruchika
On 06/03/2013 11:13 AM, Kishon Vijay Abraham I wrote:
The first three patches deals with cleanup of extcon inorder to get
through compilation without any issues. It also adds an API to get
This patch adds the possibility of the mode being specified in a device
tree. This allows the scenario when there maybe multiple USB subsystems
operating in different modes.
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |3 ++-
drivers/usb
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
drivers/usb/phy/phy-omap-usb3.c |7 ++-
1 files changed, 6 insertions(+), 1
or
specifies it superfluously to drd the functionality will be that
of a dual role device.
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |3 ++-
drivers/usb/dwc3/core.c| 21 +
2 files changed, 19
or
specifies it superfluously to drd the functionality will be that
of a dual role device.
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |3 ++-
drivers/usb/dwc3/core.c| 20 +---
2 files changed, 19 insertions
On 05/30/2013 03:35 PM, Dan Murphy wrote:
Fix spelling in my own comments
On 05/30/2013 03:31 PM, Dan Murphy wrote:
On 05/30/2013 03:14 PM, Ruchika Kharwar wrote:
This patch adds an optional parameter dr_mode to the dwc3 core device node.
In the case the compile flag for the DWC3 controller
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