On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
following transition modes ...
NO_SLEEP (0x0) - A clock domain sleep transition is never initiated,
irrespective
Benoit,
On Wednesday 09 May 2012 04:28 PM, Cousson, Benoit wrote:
Hi Kevin and Jon,
On 5/8/2012 11:22 PM, Kevin Hilman wrote:
Jon Hunterjon-hun...@ti.com writes:
Hi Benoit,
On 05/08/2012 06:01 AM, Cousson, Benoit wrote:
[...]
P.S. Please note there is also already a different fix in
with me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
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On Thursday 10 May 2012 02:23 PM, Russell King - ARM Linux wrote:
On Thu, May 10, 2012 at 12:41:35PM +0530, Santosh Shilimkar wrote:
Are you planning to merge below patch as is or split
the patch like 1) Refactoring 2) ARMv7 fix
I don't see any point in splitting this up, especially
On Thursday 10 May 2012 05:18 PM, Roger Quadros wrote:
On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
On Thu, May 10, 2012 at 5:06 PM, Roger Quadros rog...@ti.com wrote:
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
OMAP4 and OMAP5 share
-omap-dev.git
for_3.5/omap_misc_cleanup
R Sricharan (1):
ARM: OMAP2+: dma: Define dma capabilities register bitfields and use them.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Makefile
On Tuesday 08 May 2012 04:33 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120502 02:51]:
This series has some miscellianeous clean up patches which help to add future
OMAP2+ device support with bit less changes. It is a preparatory series for
adding minimal OMAP5
On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120507 02:53]:
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
The series adds minimal OMAP5 support.
OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
L2 cache
On Tuesday 08 May 2012 06:17 PM, Will Deacon wrote:
Hello,
On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off
to various interconnect violations. The issue is observed on OMAP5.
This patch tries to fix the issue by ensuring that all regions
are marked as a client domain so that XN attribute is effective.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
On Saturday 05 May 2012 04:25 AM, Tony Lindgren wrote:
* R Sricharan r.sricha...@ti.com [120503 00:30]:
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
#include linux/kernel.h
#include linux/errno.h
#include linux/smp.h
+#include
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
The series adds minimal OMAP5 support.
OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
hence large part of the peripherals are re-used.
OMAP5432 is
for the devices used like debug console etc.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/boot/compressed/head.S |7 ++-
1 files changed, 6
On Friday 04 May 2012 05:33 AM, Greg KH wrote:
On Thu, May 03, 2012 at 06:38:23PM -0400, Paul Gortmaker wrote:
On Fri, Apr 27, 2012 at 8:24 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Add a driver for the EMIF SDRAM controller used in Texas Instrument SoCs
Hi Santosh,
Can you
: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap1/gpio15xx.c |2 --
arch/arm/mach-omap1/gpio16xx.c |5 -
arch/arm
khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap2/gpio.c |2 ++
arch/arm
(), the bank-workaround_enabled check is
moved after context restore. Otherwise, it would prevent
context restore when bank-enabled_non_wakeup_gpios is 0.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous
on OMAP1710SDP.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Tarun Kanti DebBarma (8):
gpio/omap: remove virtual_irq_start variable
gpio
+: Add prm and cm base init function.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Makefile
ARM: OMAP4: Remove un-used WakeupGen register defines.
ARM: OMAP: dma: Make use of cpu_class_is_omap2
Since OMAP4 code base now makes use of OMAP4 specific PRCM functions,
cm2xxx_3xxx.c need not be compiled for OMAP4 only builds.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/Makefile |5 +
1 files changed, 1 insertions
Current OMAP code doesn't use any of the OMAP_WKG_ENB_SECURE_*
registers.
So remove those defines.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |8
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/arch
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile | 160 -
1 files changed, 78 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 56ed62e..669e2b1 100644
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need to patch
the file for any future OMAP2+ devices.
In long run, all these attributes should come from hwmod dev_attr based
on DMA IP version.
Signed-off-by: Santosh Shilimkar
EMIF, GMPC and DMM driver can ioremap() the address
space as part of driver intialisation and there is
no need to have static IO mapping for them.
Hence remove the un-used static IP space and let
the respective drivers manage it as part if driver
init.
Signed-off-by: Santosh Shilimkar
All OMAP2PLUS arch based machines makes use of mach-omap2 directory.
So just add one entry so that there is no need to patch this file
for any OMAP2+ devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/Makefile |4 +---
1 files changed, 1 insertions(+), 3
: Paul Walmsley p...@pwsan.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 28 ++--
arch/arm/mach-omap2/common.c |1 +
arch/arm/mach-omap2/common.h |1
Greg,
On Wednesday 02 May 2012 10:46 AM, Greg KH wrote:
On Fri, Apr 27, 2012 at 05:54:02PM +0530, Santosh Shilimkar wrote:
Add a driver for the EMIF SDRAM controller used in Texas Instrument SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2
EMIF SDRAM controller
driver.
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous...@ti.com
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
in
the mainline yet.
Discussions with Santosh Shilimkar santosh.shilim...@ti.com
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
vvard...@gmail.com did the initial code snippet for thermal
handling.
Testing:
- The driver is tested on OMAP4430 SDP.
- The driver in a slightly adapted
-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous...@ti.com
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Cc
From: Aneesh V ane...@ti.com
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit
and voltage change handling needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous
this and also takes care of going back to nominal settings
when temperature falls back to nominal levels.
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous...@ti.com
[santosh.shilim...@ti.com: Moved to drivers/memory
From: Aneesh V ane...@ti.com
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous...@ti.com
[santosh.shilim...@ti.com: Moved to drivers/memory
.
Signed-off-by: Aneesh V ane...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Benoit Cousson b-cous...@ti.com
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Tested-by: Lokesh Vutla lokeshvu
Greg,
On Monday 23 April 2012 08:14 PM, Shilimkar, Santosh wrote:
On Mon, Apr 23, 2012 at 7:57 PM, Greg KH g...@kroah.com wrote:
On Mon, Apr 23, 2012 at 04:34:46PM +0530, Shilimkar, Santosh wrote:
Afzal,
On Mon, Apr 23, 2012 at 4:26 PM, Mohammed, Afzal af...@ti.com wrote:
Hi Aneesh,
On
+ Tero
On Tuesday 24 April 2012 03:20 PM, Jean Pihet wrote:
Hi Grazvydas, Kevin,
I did some gather some performance measurements and statistics using
custom tracepoints in __omap3_enter_idle.
All the details are at
for ST_32KSYNC timer to prcm-common
header
ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database
ARM: OMAP: Make OMAP clocksource source selection using kernel param
This versions of series seems to fine with me.
Feel free to add,
Reviewed-by: Santosh Shilimkar santosh.shilim
On Thursday 12 April 2012 06:27 PM, Cousson, Benoit wrote:
Hi Santosh,
On 4/12/2012 12:31 PM, Santosh Shilimkar wrote:
Benoit,
On Monday 27 February 2012 04:02 PM, Santosh Shilimkar wrote:
Most of the OMAP4 control module register defines are not used and
can be removed. Keep only needed
On Saturday 14 April 2012 06:54 PM, Russell King - ARM Linux wrote:
Using coherent DMA memory with the OMAP DMA engine results in
unpredictable behaviour due to memory ordering issues; as things stand,
there is no guarantee that data written to coherent DMA memory will be
visible to the DMA
issue, I have been
observing on OMAP4 devices and also can be potential reason for some
other UART wakeup issues.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Govindraj.R govindraj.r...@ti.com
Cc: Kevin Hilman khil...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2
On Thursday 12 April 2012 08:30 AM, Greg KH wrote:
On Wed, Apr 11, 2012 at 08:44:39PM -0600, Paul Walmsley wrote:
Cc Mark Greer, Mark Salter
Hi Greg, Aneesh,
On Sat, 17 Mar 2012, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that
restore of sysconfig register.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
v2: removed tiocp_cfg from struct timer_regs {}
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Benoit,
On Monday 27 February 2012 04:02 PM, Santosh Shilimkar wrote:
Most of the OMAP4 control module register defines are not used and
can be removed. Keep only needed defines and move them to common
control module header just like other OMAP versions.
Signed-off-by: Santosh Shilimkar
Couple of patches on the ARMv7 cache code. First patch adds
v7_flush_dcache_by_level() API and second patch updates the setup
function to use the same.
R Sricharan (1):
ARM: mm: Add v7_flush_dcache_by_level() API.
Santosh Shilimkar (1):
ARM: mm: Flush only CPU local cache instead of all
be quite
expensive.
So introduce v7_flush_dcache_by_level() API which takes a
parameter (cache level), and flush only on that level.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Sricharan R r.sricha...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Russell King rmk+ker
functions are used in CPU hotplug scenario's too and
hence flushing all cache levels should be avoided.
Fix this code by restricting the cache flush to local cpu
cache or L1.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Russell King rmk+ker
On Tuesday 10 April 2012 02:14 PM, Russell King - ARM Linux wrote:
On Mon, Apr 09, 2012 at 03:18:22PM -0500, Jon Hunter wrote:
True, but we would always want to use the 32k timer if CONFIG_PM is
specified. So what I am saying is that if a device has a 32ksync timer
and CONFIG_PM is
On Tuesday 03 April 2012 08:36 PM, Santosh Shilimkar wrote:
On Tuesday 03 April 2012 10:34 AM, Kevin Hilman wrote:
Hi Santosh,
Santosh Shilimkar santosh.shilim...@ti.com writes:
The series adds the coupled cpuidle support for OMAP4 based on the v2
series posted [1]. This makes OMAP4
On Thursday 05 April 2012 04:01 PM, Hiremath, Vaibhav wrote:
On Thu, Apr 05, 2012 at 15:22:21, Russell King - ARM Linux wrote:
On Thu, Apr 05, 2012 at 09:36:00AM +, Hiremath, Vaibhav wrote:
There seems to be limitation for ARM architecture, it is restricted by
sched_clock implementation
On Tuesday 03 April 2012 10:34 AM, Kevin Hilman wrote:
Hi Santosh,
Santosh Shilimkar santosh.shilim...@ti.com writes:
The series adds the coupled cpuidle support for OMAP4 based on the v2
series posted [1]. This makes OMAP4 to support SMP cpuidle and also
removes the hard dependency
Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
CC: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Ming Lei tom.leim...@gmail.com
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
CC: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Ming Lei tom.leim...@gmail.com
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Balbi ba...@ti.com
CC: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tarun Kanti DebBarma tarun.ka...@ti.com
Cc: Ming Lei tom.leim...@gmail.com
---
Thanks for the change log update Vaibhav
+ Kevin
On Friday 30 March 2012 01:56 PM, Tomi Valkeinen wrote:
On Fri, 2012-03-30 at 13:51 +0530, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 1:37 PM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
All OMAP4 versions seem to be affected. I couldn't find a mention about
this in the
2001
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Fri, 30 Mar 2012 12:43:29 +0530
Subject: [PATCH] ARM: OMAP: Make OMAP clocksource source selection runtime.
Current OMAP code support couple of clocksource options based on compilation
flag. The 32KHz based sync timer and a gptimer
On Friday 30 March 2012 02:04 PM, Archit Taneja wrote:
On Friday 30 March 2012 02:01 PM, Santosh Shilimkar wrote:
+ Kevin
On Friday 30 March 2012 01:56 PM, Tomi Valkeinen wrote:
On Fri, 2012-03-30 at 13:51 +0530, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 1:37 PM, Tomi
On Friday 30 March 2012 03:53 PM, Cousson, Benoit wrote:
On 3/30/2012 10:44 AM, Santosh Shilimkar wrote:
On Friday 30 March 2012 02:04 PM, Archit Taneja wrote:
On Friday 30 March 2012 02:01 PM, Santosh Shilimkar wrote:
+ Kevin
On Friday 30 March 2012 01:56 PM, Tomi Valkeinen wrote:
On Fri
On Friday 30 March 2012 04:59 PM, Hiremath, Vaibhav wrote:
On Fri, Mar 30, 2012 at 15:12:19, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 2:58 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 2:42 PM,
On Friday 30 March 2012 05:30 PM, Cousson, Benoit wrote:
On 3/30/2012 1:20 PM, Shilimkar, Santosh wrote:
[..]
Playing with clock domain state from the driver is just not acceptable.
Sorry for small digration but the clock-domain/power domain APIs
were coming in between CPUIDLE code movement
on this
series.
Kevin Hilman (1):
ARM: OMAP4: CPUidle: add synchronization for coupled idle states
Santosh Shilimkar (2):
ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
ARM: OMAP4: cpuidle: Use coupled cpuidle states to implement SMP
cpuidle.
arch/arm/mach-omap2
, and
set the irq to allow the clockevent core to determine the affinity of the
timer.
Signed-off-by: Colin Cross ccr...@android.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/timer.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git
Cross on the suggestions/fixes
on the intermediate version of this patch.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
CC: Kevin Hilman khil...@ti.com
Cc: Colin Cross ccr...@android.com
---
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2/cpuidle44xx.c | 167
the coupled
state enter method can return.
In addition, cpuidle_coupled_parallel_barrier() is used to ensure the
clearing of the 'done' flag is synchronized on all CPUs.
Cc: Colin Cross ccr...@android.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Kevin Hilman khil
+ Jean,
On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
The cpuidle API allows to declare statically the states in the driver
structure. Let's use it.
We do no longer need the fill_cstate function called at runtime and
by the way adding more instructions at boot time.
On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
arch/arm/mach-omap2/cpuidle44xx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
This patchset is a proposition to improve a bit the code.
The changes are code cleanup and does not
On Wednesday 21 March 2012 03:16 PM, Daniel Lezcano wrote:
On 03/21/2012 10:41 AM, Shilimkar, Santosh wrote:
On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
The 'valid' field is never used in the code, let's remove it.
Signed-off-by: Daniel
Daniel,
On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
This patchset is a proposition to improve a bit the code.
The changes are code cleanup and does not change the behavior of the
driver itself.
A couple a things call my intention. Why the cpuidle device is set for cpu0
only
On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
I think you made very good point here. With the above patch, we are almost
missing the capability of registering dmtimer as a clocksource for OMAP.
It will always use
On Monday 12 March 2012 10:21 PM, Kevin Hilman wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
On OMAP4, recently a synchronisation bug is discovered by hardware
team, which leads to incorrect timer value read from 32K sync timer
IP when the IP is comming out of idle.
The issue
Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
does wait for the powerdomain transition which is not the case.
Fix this API by adding the pwrdm_wait_transition().
Signed-off-by: Santosh Shilimkar
With patch 'ARM: OMAP: powerdomain: Wait for powerdomain transition
in pwrdm_state_switch()', the pwrdm_clkdm_state_switch() API becomes
duplicate of pwrdm_state_switch().
Get rid off duplicate pwrdm_clkdm_state_switch() and update the
users of it with pwrdm_state_switch()
Signed-off-by: Santosh
Paul,
Can you please have at this series ?
First patch is the bug fix and second one is the cleanup which you proposed some
time back.
Santosh Shilimkar (2):
ARM: OMAP: powerdomain: Wait for powerdomain transition in
pwrdm_state_switch()
ARM: OMAP: powerdomain: Get rid off duplicate
...@linaro.org
[dave.l...@linaro.org: Reported the oprofile time stamp issue with synctimer
and helped to test this patch]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/pm44xx.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch
).
This can not be done now as DVFS support is not available in
the mainline yet.
Discussions with Santosh Shilimkar santosh.shilim...@ti.com
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
vvard...@gmail.com did the initial code snippet for thermal
handling.
Testing
is not programmed in wakeup_en register. Fix this.
chip.irq_set_type()-gpio_irq_type()-_set_gpio_triggering()-set_gpio_trigger()
chip.irq_set_wake()-gpio_wake_enable()-_set_gpio_wakeup()
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
Looks good.
Reviewed-by: Santosh Shilimkar
is programmed in omap_gpio_restore_context() called
which is called from runtime resume callback.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
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this.
Reported-by: Govindraj Raja govindraj.r...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
Good catch. Is the suspend/resume caught this issue?
This can go as a fix as well.
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
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into these functions as GPIO number - chip-base ?
Reported-by: Russell King - ARM Linux li...@arm.linux.org.uk
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Looks good.
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
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On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
In omap_gpio_runtime_resume() the context restore should be independent
of bank-enabled_non_wakeup_gpios. This was preventing context restore
of GPIO lines which are not wakeup enabled.
Reported-by: Govindraj Raja
-irqenable_inv)
l = ~gpio_mask;
else
l |= gpio_mask;
}
Make the same change for _disable_gpio_irqbank().
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
OK.
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
is written by another. Fix this so that previous
value is always preserved until explicitly changed by respective
user/driver of the GPIO line.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
This can also go as fix.
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
omap4_hotplug_cpu lacks a __cpuinit
annotation or the annotation of omap_secondary_startup is wrong.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap
Tony,
Below are couple of section mismatch warning fixes for v3.3-rc5
Santosh Shilimkar (2):
ARM: OMAP: fix section mismatch warning for omap4_hotplug_cpu()
ARM: OMAP: Fix section mismatch warning for platform_cpu_die()
arch/arm/mach-omap2/omap-hotplug.c|2 +-
arch/arm/mach
annotation or the annotation of omap4_hotplug_cpu is wrong.
Thanks to Russell King for suggesting __ref annotation trick
just like it's parent function for this warning becasue __cupinit
usage was definitely wrong to fix this warning..
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
On Friday 17 February 2012 04:36 PM, Marc Zyngier wrote:
On 17/02/12 10:40, Shilimkar, Santosh wrote:
On Fri, Feb 17, 2012 at 3:17 PM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Santosh,
On Fri, 17 Feb 2012 13:18:37 +0530, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
[..]
diff
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
From: Benoit Cousson b-cous...@ti.com
One line of change log will do here.
Regards
santosh
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On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc/emif_regs.h | 461
++
1 files changed, 461 insertions(+), 0 deletions(-)
create mode 100644 drivers/misc/emif_regs.h
Changelog
/drivers/misc/emif.c
@@ -0,0 +1,300 @@
+/*
+ * EMIF driver
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
Fix year. 2012
+ *
+ * Aneesh V ane...@ti.com
+ * Santosh Shilimkar santosh.shilim...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping),
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add an ISR for EMIF that:
1. reports details of access errors
2. takes action on thermal events
On thermal events SDRAM timing parameters are
adjusted to ensure safe operation
Also clear all interrupts on shut-down.
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add settings that are not dependent on frequency
or any other transient parameters
Expand the changelog a bit. One time settings like
SDRAM_CONFIG, PHY_CONTROL, TEMP alert etc.
Signed-off-by: Aneesh V ane...@ti.com
---
Patch looks fine.
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Signed-off-by: Aneesh V ane...@ti.com
looks good.
Regards
santosh
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is not available yet in mainline.
Discussions with Santosh Shilimkar santosh.shilim...@ti.com
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
vvard...@gmail.com did the initial code snippet for thermal
handling.
Testing:
- The driver is tested
with the userspace governor. Here's what I did on my 3430/n900:
Below patch fixes the issue.
Regards
Santosh
From 3a16f7a6694c14e201fdf6ad195c821816b2de84 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Fri, 17 Feb 2012 11:11:28 +0530
Subject: [PATCH] ARM
On Wednesday 08 February 2012 04:08 AM, Kevin Hilman wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
OMAP4 cpuidle driver is reporting the state requested by governor rather than
the actually attempted one.
This is obviously misleading sysfs and powertop cpuidle statistics.
Fix
On Saturday 11 February 2012 12:49 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120202 05:33]:
arm_memblock_steal() is not suppose to be used outside -reserve callback.
OMAP barrier errata code was using it outside reserve callback and hence
it was broken.
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