On Tue, Oct 13, 2015 at 02:56:12PM +0200, Joel Porquet wrote:
> The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h', making it
> globally accessible.
>
> See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d ("irqchip: Move
> IRQCHIP_DECLARE macro to include/linux/irqchip.h").
>
> This
On Tue, Oct 13, 2015 at 12:12:29AM +0300, Laurent Pinchart wrote:
> Laurent Pinchart (37):
...
> ARM: imx6sx-sdb: Fix typo in regulator enable GPIO property
...
> ARM: dts: imx6qdl-tx6: Fix regulator enable GPIO polarity
...
> ARM: dts: imx23-evk: Fix regulator enable GPIO polarity
> ARM:
On Tue, Oct 13, 2015 at 05:17:24PM +0300, Laurent Pinchart wrote:
> Hi Shawn,
>
> On Tuesday 13 October 2015 22:09:46 Shawn Guo wrote:
> > On Tue, Oct 13, 2015 at 12:12:29AM +0300, Laurent Pinchart wrote:
> > > Laurent Pinchart (37):
> > ...
> >
> >
On Fri, Sep 04, 2015 at 04:54:21PM -0400, Joel Porquet wrote:
> On Monday, July 13, 2015 11:20:35 PM Shawn Guo wrote:
> > On Tue, Jul 07, 2015 at 04:02:53PM -0400, Joel Porquet wrote:
> > > The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h', making it
> &g
adds inclusions of 'include/linux/irqchip.h' and replaces uses of
macro OF_DECLARE_2 with IRQCHIP_DECLARE.
Signed-off-by: Joel Porquet j...@porquet.org
---
...
arch/arm/mach-imx/gpc.c | 7 ++-
Acked-by: Shawn Guo shawn...@kernel.org
How will this patch be sent to upstream
khil...@deeprootsystems.com
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Cc: Gregory Clement gregory.clem...@free-electrons.com
Acked-by: Hans Ulli Kroll ulli.kr...@googlemail.com
Cc: Shawn Guo shawn@linaro.org
On Fri, Mar 13, 2015 at 09:20:10AM +0100, Sebastian Andrzej Siewior wrote:
Hi Shawn,
On Fri, Mar 13, 2015 at 11:29:32AM +0800, Shawn Guo wrote:
We did not add a DT property for it, because there was already enough
info (clock configuration) in DT for kernel to figure it out.
Correct. My
On Thu, Mar 12, 2015 at 12:43:40PM -0700, Stephen Boyd wrote:
On 03/12/15 10:20, Sebastian Andrzej Siewior wrote:
On 2015-02-17 14:01:04 [-0800], Stephen Boyd wrote:
diff =
--- arch/arm/mach-imx/mach-imx6q.c
+++ /tmp/cocci-output-11792-b62223-mach-imx6q.c
@@ -211,7 +211,6 @@ static
DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Shawn Guo shawn@linaro.org
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On Tue, Aug 26, 2014 at 11:03:24AM +0100, Marc Zyngier wrote:
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Shawn Guo shawn@freescale.com
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On Tue, Aug 26, 2014 at 11:03:37AM +0100, Marc Zyngier wrote:
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Shawn Guo shawn@freescale.com
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On Tue, Aug 26, 2014 at 11:03:38AM +0100, Marc Zyngier wrote:
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Shawn Guo shawn@freescale.com
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the ARCH_HAS_OPP symbol
has become redundant and can be removed. Do so.
Signed-off-by: Mark Brown broo...@linaro.org
---
...
arch/arm/mach-imx/Kconfig | 1 -
Acked-by: Shawn Guo shawn@freescale.com
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On Sun, Feb 23, 2014 at 09:40:12PM -, Thomas Gleixner wrote:
Use the proper functions. There is no need to fiddle with irq_desc.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: Shawn Guo shawn@linaro.org
...
arch/arm/mach-imx/pm-imx6q.c|7 +++
Acked-by: Shawn
On Thu, Jul 11, 2013 at 04:37:47PM +0200, Laurent Pinchart wrote:
The i.MX53 PWM controller uses two cells to describe the PWM specifier.
Remove the extra unused values from the backlight DT node pwms property.
Signed-off-by: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
On Tue, Apr 30, 2013 at 01:04:20PM +0200, Arnd Bergmann wrote:
arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_die':
arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function
'cpu_do_idle'
arch/arm/mach-imx/hotplug.c: In function 'imx_cpu_kill':
: Shawn Guo shawn@linaro.org
The same BUG was observed on IMX/MXS systems, so
Acked-by: Shawn Guo shawn@linaro.org
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the
following in kernel will just help cpufreq-cpu0 find the clock, if
you instantiate cpufreq-cpu0 driver in the same way that
highbank-cpufreq does.
clk_register_clkdev(cpuclk, NULL, cpufreq-cpu0.0);
Shawn
Cc: Rafael J. Wysocki r...@sisk.pl
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Shawn
/cpus, and it does not belong to device tree.
Shawn
Cc: Rafael J. Wysocki r...@sisk.pl
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Shawn Guo shawn@linaro.org
Cc: linux-ker...@vger.kernel.org
Cc: cpuf...@vger.kernel.org
Cc: linux...@vger.kernel.org
Cc: linux-omap@vger.kernel.org
On Thu, Jan 31, 2013 at 09:40:43AM +, AnilKumar, Chimata wrote:
On Wed, Jan 30, 2013 at 20:02:22, Shawn Guo wrote:
The cpufreq-cpu0 driver changes to instantiate use platform_driver
mechanism. The patch is an am33xx platform level adaptation for it.
Tested-by: AnilKumar Ch anilku
The cpufreq-cpu0 driver changes to instantiate use platform_driver
mechanism. The patch is an am33xx platform level adaptation for it.
Signed-off-by: Shawn Guo shawn@linaro.org
---
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/cclock33xx_data.c |2 +-
arch/arm/mach
On Tue, Sep 25, 2012 at 10:05:01AM +0530, Vinod Koul wrote:
On Mon, 2012-09-24 at 17:25 -0500, Jon Hunter wrote:
For DT bindings, I think the binding itself shouldn't change based on my
work but I would like these same bindings to help build the DMA engine
code mappings.
Now would
On Thu, Sep 20, 2012 at 12:27:55PM +0100, Lorenzo Pieralisi wrote:
[adding CCs: Kukjin Kim, Shawn Guo, Magnus Damm, Rob Herring]
On imx6q with suspend/hotplug,
Tested-by: Shawn Guo shawn@linaro.org
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...@vista-silicon.com
CC: Zhangfei Gao zhangfei@marvell.com
CC: Shawn Guo shawn@linaro.org
CC: Laxman Dewangan ldewan...@nvidia.com
---
...
drivers/dma/imx-dma.c | 2 +-
drivers/dma/imx-sdma.c| 2 +-
...
drivers/dma/mxs-dma.c | 2 +-
Acked-by: Shawn Guo shawn
Gao zhangfei@marvell.com
CC: Shawn Guo shawn@linaro.org
CC: Laxman Dewangan ldewan...@nvidia.com
---
drivers/dma/at_hdmac.c| 3 ++-
drivers/dma/ep93xx_dma.c | 4 +++-
drivers/dma/imx-dma.c | 2 +-
drivers/dma/imx-sdma.c| 2 +-
drivers/dma/mmp_tdma.c
On Mon, Sep 17, 2012 at 10:16:53AM +0300, Peter Ujfalusi wrote:
All users of this callback is updated with this patch.
The public API (dmaengine_prep_dma_cyclic) is only used by ASoC, which has
been updated by the previous patch.
Ah, ok. You actually changed dmaengine_prep_dma_cyclic
It seems the same patch has been there for a while.
http://thread.gmane.org/gmane.linux.kernel/1303115
Regards,
Shawn
On Sun, Jun 24, 2012 at 12:28:10PM +0200, Javier Martinez Canillas wrote:
On reboot or poweroff (machine_shutdown()) a call to smp_send_stop() is
made (to stop the others
On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-König wrote:
...
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573..7e00748 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -102,7 +102,7 @@ static struct sys_timer
On Fri, Mar 30, 2012 at 11:50:24AM +0200, Uwe Kleine-König wrote:
Hello Shawn,
On Fri, Mar 30, 2012 at 02:11:36PM +0800, Shawn Guo wrote:
On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-König wrote:
...
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
On Fri, Feb 03, 2012 at 12:55:08PM -0800, Tony Lindgren wrote:
Add simple pinmux driver using device tree data.
Currently this driver only works on omap2+ series of
processors, where there is either an 8 or 16-bit mux
register for each pin. Support for other similar pinmux
controllers could
/arm/mach-mxs/devices.c: In function ‘mxs_add_amba_device’:
arch/arm/mach-mxs/devices.c:80:50: error: ‘const struct amba_device’ has no
member named ‘init_name’
Other than that,
Acked-by: Shawn Guo shawn@linaro.org
Regards,
Shawn
+ dev-res.start, resource_size(dev-res
On Fri, Jan 20, 2012 at 09:26:28AM +, Russell King - ARM Linux wrote:
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Acked-by: Shawn Guo shawn@linaro.org
---
arch/arm/mach-mxs/devices/amba-duart.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On Thu, Jan 12, 2012 at 04:04:23PM -0800, Saravana Kannan wrote:
While the original clk_hw suggestion was well intentioned, it just
forces too many unnecessary dereferences and indirection. It also
prevents static init of some fields as others have mentioned.
Overall, it made the MSM clock
in this patch.
[0]: http://www.spinics.net/lists/linux-omap/msg62124.html
Changes in v2:
- Don't use ERR_PTR, keep the WARN_ON(1) and return NULL as requested
by Grant Likely.
- Integrate i.MX cleanup patch by Shawn Guo.
...
arch/arm/mach-imx/imx51-dt.c | 13
AUTO_ZRELADDR if !ZBOOT_ROM
select ARM_PATCH_PHYS_VIRT
+ select MIGHT_HAVE_CACHE_L2X0
help
This enables support for systems based on the Freescale i.MX3 and
i.MX6
family.
Acked-by: Shawn Guo shawn@linaro.org
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Shawn
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for debugging purposes etc.
Since SOC_IMX6Q already depends on ARCH_IMX_V6_V7 and
ARCH_IMX_V6_V7 selects MIGHT_HAVE_CACHE_L2X0, there is no need to
select that option explicitly from SOC_IMX6Q.
Thanks to Shawn Guo for this suggestion. [1]
[1]
http://lists.infradead.org/pipermail/linux
and selects MIGHT_HAVE_CACHE_L2X0 instead.
This makes the l2x0 support optional, so that it can be turned off
when desired for debugging purposes etc.
Thanks to Shawn Guo for this suggestion. [1]
Signed-off-by: Dave Martin dave.mar...@linaro.org
[1]
http://lists.infradead.org/pipermail/linux
On Thu, Dec 15, 2011 at 09:02:20AM +0800, Richard Zhao wrote:
On Wed, Dec 14, 2011 at 03:01:19PM +, Dave Martin wrote:
On Wed, Dec 14, 2011 at 10:05:04PM +0800, Richard Zhao wrote:
On Wed, Dec 14, 2011 at 09:26:24PM +0800, Shawn Guo wrote:
Hi Dave,
Sorry for that I did
On Wed, Nov 23, 2011 at 12:33:47PM -0800, Turquette, Mike wrote:
On Tue, Nov 22, 2011 at 6:03 PM, Saravana Kannan skan...@codeaurora.org
wrote:
On 11/21/2011 05:40 PM, Mike Turquette wrote:
[...]
+is modified slightly for brevity:
+
+struct clk {
+ const char
On Mon, Nov 21, 2011 at 05:40:45PM -0800, Mike Turquette wrote:
[...]
+/**
+ * DOC: Using the CLK_PARENT_SET_RATE flag
+ *
+ * __clk_set_rate changes the child's rate before the parent's to more
+ * easily handle failure conditions.
+ *
+ * This means clk might run out of spec for a short
On Mon, Nov 21, 2011 at 05:40:46PM -0800, Mike Turquette wrote:
Many platforms support simple gateable clks and fixed-rate clks that
should not be re-implemented by every platform.
This patch introduces a gateable clk with a common programming model of
gate control via a write of 1 bit to a
One comment was missed.
On Mon, Nov 21, 2011 at 05:40:46PM -0800, Mike Turquette wrote:
[...]
+struct clk_hw_ops clk_hw_gate_set_enable_ops = {
const?
+ .enable = clk_hw_gate_enable_set,
+ .disable = clk_hw_gate_disable_clear,
+ .recalc_rate = clk_hw_gate_recalc_rate,
+
On Mon, Nov 21, 2011 at 05:40:43PM -0800, Mike Turquette wrote:
The common clk framework provides clk_prepare and clk_unprepare
implementations. Create an entry for HAVE_CLK_PREPARE so that
GENERIC_CLK can select it.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Acked-by: Shawn
On Mon, Nov 21, 2011 at 05:40:42PM -0800, Mike Turquette wrote:
[...]
.the most notable change is the removal of struct clk_hw.
Happy to see that.
This extra
layer of abstraction is only necessary if we want hide the definition of
struct clk from platform code. Many developers expressed
On Wed, Nov 09, 2011 at 01:46:52PM -0800, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [07 16:11]:
* Russell King - ARM Linux li...@arm.linux.org.uk [06 05:18]:
Here's a list of my peaves about current platform code - which are
causing me great issue when trying to clean
On Wed, Oct 19, 2011 at 03:47:34PM +0100, Mark Brown wrote:
On Wed, Oct 19, 2011 at 01:33:55PM +0800, Shawn Guo wrote:
On Tue, Oct 18, 2011 at 05:00:46PM +0100, Mark Brown wrote:
It's not just Linux-specific stuff, some of this is even specific to
what current Linux drivers can do
On Tue, Sep 20, 2011 at 08:46:25AM +0100, Russell King - ARM Linux wrote:
On Tue, Sep 20, 2011 at 11:47:18AM +0800, Shawn Guo wrote:
On Mon, Sep 19, 2011 at 05:37:41PM +0100, Russell King - ARM Linux wrote:
This is a re-post of the previous patch series, but with an additional
TLB flush
On Mon, Sep 19, 2011 at 05:22:22PM +0100, Russell King - ARM Linux wrote:
On Sun, Sep 11, 2011 at 12:10:04AM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 11:57:54PM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 04:34:51PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 01, 2011
On Mon, Sep 19, 2011 at 05:37:41PM +0100, Russell King - ARM Linux wrote:
This is a re-post of the previous patch series, but with an additional
TLB flush to ensure that hte global TLB entry in the page tables is
flushed out. This is a flush of all TLB entries, but it could probably
be more
On Thu, Sep 01, 2011 at 11:57:54PM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 04:34:51PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 01, 2011 at 11:33:43PM +0800, Shawn Guo wrote:
This is also the case on i.MX6Q, which L2 cache is retained during a
suspend/resume cycle
Hi Santosh,
On Sun, Sep 04, 2011 at 07:24:15PM +0530, Santosh Shilimkar wrote:
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR) is not supported by hardware design.
The CPUx OFF mode isn't supported on OMAP4430 ES1.0
CPUx sleep code is common for
On Fri, Sep 09, 2011 at 01:39:51PM +0530, Santosh wrote:
On Friday 09 September 2011 01:34 PM, Shawn Guo wrote:
Hi Santosh,
On Sun, Sep 04, 2011 at 07:24:15PM +0530, Santosh Shilimkar wrote:
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR
On Fri, Sep 09, 2011 at 07:41:08PM +0530, Shilimkar, Santosh wrote:
On Fri, Sep 9, 2011 at 7:43 PM, Shawn Guo shawn@freescale.com wrote:
On Fri, Sep 09, 2011 at 01:39:51PM +0530, Santosh wrote:
On Friday 09 September 2011 01:34 PM, Shawn Guo wrote:
Hi Santosh,
On Sun, Sep 04, 2011
On Fri, Sep 09, 2011 at 10:29:49PM +0530, Santosh wrote:
On Friday 09 September 2011 08:57 PM, Shawn Guo wrote:
On Fri, Sep 09, 2011 at 07:41:08PM +0530, Shilimkar, Santosh wrote:
On Fri, Sep 9, 2011 at 7:43 PM, Shawn Guoshawn@freescale.com wrote:
On Fri, Sep 09, 2011 at 01:39:51PM +0530
On Sat, Sep 10, 2011 at 09:08:16AM +0530, Shilimkar, Santosh wrote:
IOn Sat, Sep 10, 2011 at 5:04 AM, Shawn Guo shawn@freescale.com wrote:
[...]
Also, IMO, lable l2x_clean_inv should be put after the bne do_WFI.
Otherwise, my original statement (it seems l2x_clean_inv will be
called
Hi Russell,
On Thu, Sep 01, 2011 at 01:47:52PM +0100, Russell King - ARM Linux wrote:
Some systems (such as OMAP) preserve the L2 cache across a suspend/
resume cycle. This means they do not perform L2 cache maintanence
in their suspend finisher function.
However, the side effect is that
On Thu, Sep 01, 2011 at 04:34:51PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 01, 2011 at 11:33:43PM +0800, Shawn Guo wrote:
This is also the case on i.MX6Q, which L2 cache is retained during a
suspend/resume cycle. Currently, I have to call into the following
before calling
On Fri, Aug 12, 2011 at 10:56:13AM +0200, Cousson, Benoit wrote:
[...]
The devil is in the details, but the way the DMA lines are connected
in OMAP is similar to IRQ lines, and maybe a little bit simpler.
So starting with a copy/paste of the of_irq file should be a good start.
And then the
multiple dma controllers like we do for multiple irq controllers.
--- quote ---
Shawn Guo:
Then like that IRQ number is decoded and populated into IORESOURCE_IRQ
by device tree infrastructural code, we can also do the same into
IORESOURCE_DMA. In that case, drivers do not need any code change
+--
arch/arm/plat-orion/include/plat/gpio.h |6 ++
arch/arm/plat-spear/include/plat/gpio.h |6 +-
25 files changed, 36 insertions(+), 151 deletions(-)
For mxs and mxc:
Tested-by: Shawn Guo shawn@linaro.org
--
Regards,
Shawn
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On Wed, Jul 06, 2011 at 06:12:49PM -0600, Grant Likely wrote:
On Wed, Jul 6, 2011 at 5:26 PM, Stephen Warren swar...@nvidia.com wrote:
Grant Likely wrote at Wednesday, July 06, 2011 12:56 PM:
On Thu, Jun 30, 2011 at 03:07:23PM +0500, G, Manjunath Kondaiah wrote:
Add I2C and it's child
On Wed, Jul 20, 2011 at 12:55:13PM -0600, Grant Likely wrote:
On Wed, Jul 20, 2011 at 07:04:20PM +0800, Shawn Guo wrote:
Mostly consistency. Most of the experience we have with the flattened
device tree up to this point hasn't bothered with the 'status'
property. It is only when AMP
On Thu, May 19, 2011 at 01:08:41PM -0600, Grant Likely wrote:
On Thu, May 12, 2011 at 11:42:39AM +0200, Kevin Hilman wrote:
Linus Walleij linus.wall...@linaro.org writes:
[...]
For TI I guess this currently means you simply cannot work
on GPIO stuff until you know where to go with
On Thu, Apr 21, 2011 at 11:23:22PM -0400, Nicolas Pitre wrote:
On Thu, 21 Apr 2011, Nicolas Pitre wrote:
On Thu, 21 Apr 2011, Nicolas Pitre wrote:
On Thu, 21 Apr 2011, Tony Lindgren wrote:
Otherwise we end up overwriting ourselves. This fixes booting
on n900 after commit
On Fri, Apr 22, 2011 at 01:19:14PM +0800, Shawn Guo wrote:
- 8
From: Nicolas Pitre nicolas.pi...@linaro.org
ARM: zImage: make sure the stack is 64-bit aligned
With ARMv5+ and EABI, the compiler expects a 64-bit aligned stack so
instructions like STRD and LDRD can be used
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