Hi Sylwester,
On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim kg...@kernel.org wrote:
On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
The series has dependency on
a) [PATCH
Hi Alim,
On Sat, Nov 22, 2014 at 7:07 PM, Alim Akhtar alim.akh...@gmail.com wrote:
Hi Vivek,
On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl
.
The USB driver patches in this series were part of [1] sent earlier.
[1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
https://lkml.org/lkml/2014/10/7/191
Vivek Gautam (11):
pinctrl: exynos: Add BUS1 pin controller for exynos7
dwc3: exynos: Remove local variable
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
---
drivers
There's no need to keep one local variable for clock, and
then assign the same to 'clk' member of dwc3_exynos.
Just cleaning it up.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 7109de7..af15ab3 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b
DWC3 controller on Exynos7 SoC has separate control for
AXI UpScaler which connects DWC3 DRD controller to AXI bus.
Get the gate clock for the same to control it across power
cycles.
Suggested-by: Anton Tikhomirov av.tikhomi...@samsung.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
-by: Anton Tikhomirov av.tikhomi...@samsung.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|6 ++
drivers/phy/phy-exynos5-usbdrd.c | 104
2 files changed, 92 insertions(+), 18 deletions(-)
diff
Some Exynos boards have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 32
This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 64 +++
include/dt-bindings/clock/exynos7-clk.h |9 -
2 files changed, 72 insertions
BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7
Adding USB 3.0 DRD controller device node, with its clock
and phy information to enable using the same on Exynos7.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git
Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 43 +++
1 file changed, 43 insertions(+)
diff
these basic required number of
clocks.
--
Best Regards
Vivek Gautam
Samsung RD Institute, Bangalore
India
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.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb
instead. Thanks for pointing it out.
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 30
not required now.
Vivek Gautam (4):
dwc3: exynos: Add support for SCLK present on Exynos7
phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support
phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS
.../devicetree/bindings/phy/samsung
This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 30
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers
On Tue, Oct 7, 2014 at 7:41 PM, Felipe Balbi ba...@ti.com wrote:
On Tue, Oct 07, 2014 at 03:49:33PM +0530, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek
On Fri, Aug 29, 2014 at 12:58 AM, Felipe Balbi ba...@ti.com wrote:
On Thu, Aug 28, 2014 at 01:31:59PM +0530, Vivek Gautam wrote:
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam
On Tue, Sep 2, 2014 at 8:07 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Sep 01, 2014 at 01:30:21PM +0530, Vivek Gautam wrote:
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi dfo...@gmail.com wrote:
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present
Hi Felipe,
On Fri, Aug 29, 2014 at 12:46 AM, Felipe Balbi ba...@ti.com wrote:
hi,
On Thu, Aug 28, 2014 at 01:31:58PM +0530, Vivek Gautam wrote:
@@ -457,11 +458,19 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
clk_prepare_enable(phy_drd-ref_clk);
/* Enable VBUS
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi dfo...@gmail.com wrote:
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
+++ b/drivers/phy/Kconfig
@@ -186,7 +186,7 @@ config
.html
The series is based on usb-next branch.
Vivek Gautam (5):
usb: dwc3: exynos: Add support for SCLK present on Exynos7
phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support
phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
usb: dwc3: Adding Kconfig dependency for Exynos7
phy
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 27
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers
Hi,
On Wed, Jun 4, 2014 at 12:41 AM, Paul Zimmerman
paul.zimmer...@synopsys.com wrote:
From: linux-usb-ow...@vger.kernel.org
[mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Tuesday, June 03, 2014 3:40 AM
Putting together the code related to getting
Putting together the code related to getting the 'IORESOURCE_MEM'
and assigning the same to dwc-xhci_resources, for increasing
the readability.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Changes from v1:
- Fixed issue with 'res-start' as pointed out by Paul Zimmerman
Putting together the code related to getting the 'IORESOURCE_MEM'
and assigning the same to dwc-xhci_resources, for increasing
the readability.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Based on 'next' branch of Felipe's usb tree.
Also cleanly applies to 'usb-next' branch
Hi,
On Thu, Apr 24, 2014 at 6:08 AM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hi,
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate
Hi Jingoo,
On Thu, Apr 24, 2014 at 6:56 AM, Jingoo Han jg1@samsung.com wrote:
On Thursday, April 24, 2014 9:33 AM, Jingoo Han wrote:
On Thursday, April 24, 2014 9:18 AM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To: linux-...@vger.kernel.org; linux-samsung
Hi,
On Wed, Apr 23, 2014 at 4:27 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ohci-exynos.c | 47
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Anton Tikhomirov av.tikhomi...@samsung.com
---
Based on 'usb-next' branch of Greg's USB tree.
Also cleanly applies on 'next' branch of Balbi's USB tree
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ehci-exynos.c | 47
Hi,
On Wed, Apr 16, 2014 at 7:42 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Hi,
On Tue, Apr 15, 2014 at 06:24:11PM +0530, Vivek Gautam wrote:
I had seen your patches in the mailing list, but i don't see any
updated version of these patches.
Are you planning to work
Hi Heikki,
On Tue, Dec 10, 2013 at 7:25 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Giving life to this thread after long time.
Hi,
On Tue, Dec 10, 2013 at 04:25:25PM +0530, Vivek Gautam wrote:
@@ -170,6 +189,15 @@ static int xhci_plat_probe(struct platform_device *pdev
= dwc3_event_buffers_setup(dwc);
if (ret) {
dev_err(dwc-dev, failed to setup event buffers\n);
[...]
snip
--
Best Regards
Vivek Gautam
Samsung RD Institute, Bangalore
India
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Hi,
On Wed, Dec 11, 2013 at 1:39 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Hi,
On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
I think setup instead of tune is much more clear and reusable.
I think setup
Hi Kishon,
On Wed, Dec 11, 2013 at 1:47 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Wednesday 11 December 2013 12:08 PM, Vivek Gautam wrote:
Hi,
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Hi,
Thanks for reviewing this.
On Tue, Dec
HCD of XHCI.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/host.c |7 ++
drivers/usb/host/xhci-plat.c | 43 -
include/linux/usb/hcd.h |1 +
3 files changed, 49 insertions(+), 2 deletions(-)
diff --git
-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usb3.c | 107
1 files changed, 107 insertions(+), 0 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
index 2bafc9d..669f998 100644
controller has been reset.
Adding a xHCI quirk for this purpose.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/xhci-plat.c | 19 +++
drivers/usb/host/xhci.h |1 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/xhci
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy-tuning at appropriate
point of time.
Signed-off-by: vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-core.c | 20
include/linux/phy/phy.h |7 +++
2 files
on generic PHY framework
http://lwn.net/Articles/575586/
Vivek Gautam (4):
phy: Add provision for tuning phy.
xhci: Add quirk for DWC3-Exynos controller
xhci: Tune PHY for the DWC3-Exynos host controller
phy-exynos-usb3: Fine tune LOS levels for exynos5420
drivers/phy/phy-core.c
Hi,
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Hi,
Thanks for reviewing this.
On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy
On Tue, Nov 5, 2013 at 11:41 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
Dear Kishon, Roger
On Wed, Oct 16, 2013 at 6:40 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi roger,
On Wednesday 16 October 2013 06:33 PM, Roger Quadros wrote:
Hi Kishon,
Apologies for missing
should get rid of this delay, since things will still work
fine without this.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Hi Felipe,
I remember this change for phy_init including msleep(100) was
suggested by me, after testing the patch-series for PM support
to dwc3.
Sorry
Hi,
On Thu, Sep 12, 2013 at 6:41 PM, Roger Quadros rog...@ti.com wrote:
On 09/12/2013 02:26 PM, Vivek Gautam wrote:
Hi,
On Thu, Sep 12, 2013 at 4:34 PM, Roger Quadros rog...@ti.com wrote:
Hi,
On 09/12/2013 01:47 PM, Vivek Gautam wrote:
On Thu, Sep 12, 2013 at 4:06 PM, Roger Quadros rog
Hi Kishon,
On Mon, Sep 2, 2013 at 9:13 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
power_on and power_off the following APIs are used phy_init(), phy_exit(),
phy_power_on() and phy_power_off().
However using the old
On Thu, Sep 12, 2013 at 3:40 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Thursday 12 September 2013 02:57 PM, Vivek Gautam wrote:
Hi Kishon,
On Mon, Sep 2, 2013 at 9:13 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Adapted dwc3 core to use the Generic PHY Framework. So for init
On Thu, Sep 12, 2013 at 4:06 PM, Roger Quadros rog...@ti.com wrote:
Hi Kishon,
On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
There can be systems which does not have a external usb_phy, so get
usb_phy only if usb-phy property is added in the case of dt boot or if
platform_data
Hi,
On Thu, Sep 12, 2013 at 4:34 PM, Roger Quadros rog...@ti.com wrote:
Hi,
On 09/12/2013 01:47 PM, Vivek Gautam wrote:
On Thu, Sep 12, 2013 at 4:06 PM, Roger Quadros rog...@ti.com wrote:
Hi Kishon,
On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
There can be systems which does
limit the DWC3 mode to depend on corresponding usb-subsystem
and USB_DWC3.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Felipe Balbi ba...@ti.com
Cc: Fengguang Wu fengguang...@intel.com
---
drivers/usb/dwc3/Kconfig |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git
On Tue, Apr 23, 2013 at 11:42 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 23 Apr 2013, Vivek Gautam wrote:
Hi,
On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern st...@rowland.harvard.edu
wrote:
On Tue, 23 Apr 2013, Vivek Gautam wrote:
Alright, so here's my understanding
Hi,
On Thu, Apr 4, 2013 at 8:16 PM, Alan Stern st...@rowland.harvard.edu wrote:
Apologies for delay in replying.
On Thu, 4 Apr 2013, Felipe Balbi wrote:
Some subsystems handle this issue by calling pm_runtime_get_sync()
before probing a driver and pm_runtime_put_sync() after unbinding
Hi,
On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 23 Apr 2013, Vivek Gautam wrote:
Alright, so here's my understanding:
I suggested letting e.g. DWC3 enable the PHY's runtime_pm; Alan said
that it could be done before that so that DWC3 sees
On Thu, Apr 4, 2013 at 12:40 PM, Felipe Balbi ba...@ti.com wrote:
On Thu, Apr 04, 2013 at 10:34:57AM +0530, Vivek Gautam wrote:
Hi Sarah,
On Wed, Apr 3, 2013 at 10:57 PM, Sarah Sharp
sarah.a.sh...@linux.intel.com wrote:
Question: Do you still need this patch for 3.10?
Felipe's 'next
Hi,
On Thu, Apr 4, 2013 at 12:48 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Apr 03, 2013 at 02:14:02PM -0400, Alan Stern wrote:
Lets suppose DWC3 enables runtime_pm on USB 2 type phy,
it will try to go into suspend state and thereby call runtime_suspend(),
if any.
And PHY
Hi Felipe,
On Tue, Apr 2, 2013 at 1:59 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Apr 01, 2013 at 07:24:01PM +0530, Vivek Gautam wrote:
The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal
Hi Kishon,
On Wed, Apr 3, 2013 at 10:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Monday 01 April 2013 07:24 PM, Vivek Gautam wrote:
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across
Hi Felipe,
On Wed, Apr 3, 2013 at 1:45 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Apr 03, 2013 at 11:48:39AM +0530, Vivek Gautam wrote:
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend
Hi,
On Wed, Apr 3, 2013 at 7:26 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Apr 03, 2013 at 04:54:14PM +0300, Felipe Balbi wrote:
+static inline void usb_phy_autopm_enable(struct usb_phy *x)
+{
+ if (!x || !x-dev) {
+ dev_err(x-dev, no PHY or attached
On Wed, Apr 3, 2013 at 7:48 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Apr 03, 2013 at 07:40:44PM +0530, Vivek Gautam wrote:
+static inline void usb_phy_autopm_enable(struct usb_phy *x)
+{
+ if (!x || !x-dev) {
+ dev_err(x-dev, no PHY or attached
On Mon, Apr 01, 2013 at 07:23:59PM +0530, Vivek Gautam wrote:
This patch-series enables runtime power management on xhci-plat,
dwc3-core, dwc3-exynos as well as on Samsung's USB 2.0 type and
USB 3.0 type PHYs.
Based on 'next' branch of Felipe Balbi's USB tree.
Changes from v2:
- Using
Hi,
On Tue, Apr 2, 2013 at 1:53 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend.
Signed-off
Hi,
On Tue, Apr 2, 2013 at 5:40 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Tue, Apr 02, 2013 at 04:04:01PM +0530, Vivek Gautam wrote:
On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need
Hi Balbi,
On Tue, Apr 2, 2013 at 2:02 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Apr 01, 2013 at 07:24:03PM +0530, Vivek Gautam wrote:
+#else
+#define dwc3_runtime_suspend NULL
+#define dwc3_runtime_resume NULL
this #else branch is unnecessary. Look
runtime power management on samsung-usb
into required number to bifurcate functionality.
Vivek Gautam (11):
usb: phy: Add APIs for runtime power management
USB: dwc3: Adjust runtime pm to allow autosuspend
usb: dwc3: Enable runtime pm only after PHYs are initialized
usb: dwc3: Add runtime
By enabling runtime pm in this driver allows users of
xhci-plat to enter into runtime pm. This is not full
runtime pm support (AKA xhci-plat doesn't actually power
anything off when in runtime suspend mode) but,
just basic enablement.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
CC: Doug
Enable autosuspending of Samsung usb2.0 PHY
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/phy/phy-samsung-usb2.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb2.c
b/drivers/usb/phy/phy-samsung-usb2.c
index
Enable autosuspending of Samsung usb3.0 PHY
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/phy/phy-samsung-usb3.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb3.c
b/drivers/usb/phy/phy-samsung-usb3.c
index
Enabling runtime power management on dwc3-exynos
letting dwc3 controller to be autosuspended on exynos
platform when not in use.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
include/linux/usb/phy.h | 141 +++
1 files
Right now it doesn't handle full runtime suspend/resume
functionality. However it allows to handle PHYs' sleep
and wakeup across runtime suspend/resume.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/core.c | 43 +++
1 files
Allow dwc3 to enable auto power management only after its PHYs
are initialized so that any further PHY handling by dwc3's
runtime power management callbacks is fine.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/core.c | 18 +-
1 files changed, 9
The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal. Change the runtime pm code to match the standard
formula and allow runtime pm to function.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
calls as required by common clock framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
CC: Felipe Balbi ba...@ti.com
CC: Kukjin Kim kgene@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c |6 +++---
1
of 3.9rc2 tag).
Also based on: usb: dwc3: set dma_mask for dwc3_omap device by Kishon
in which DMA mask for dwc3-core is being set from its parent.
Vivek Gautam (2):
usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev
usb: dwc3: exynos: use clk_prepare_enable and clk_disable_unprepare
On Thu, Mar 14, 2013 at 4:21 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Thu, Mar 14, 2013 at 04:14:57PM +0530, Vivek Gautam wrote:
@@ -170,7 +155,6 @@ static int dwc3_exynos_remove(struct platform_device
*pdev)
{
struct dwc3_exynos *exynos = platform_get_drvdata(pdev
Hi Balbi,
On Sat, Mar 2, 2013 at 6:55 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
Now that machines may select the mode of working of DWC3 (HOST only,
GADGET only or DUAL_ROLE), lets set DWC3 mode based on that
rather than fixing it to whatever DWC3 hardware says.
This way we can skip
On Wed, Mar 13, 2013 at 2:44 PM, Felipe Balbi ba...@ti.com wrote:
On Wed, Mar 13, 2013 at 02:42:22PM +0530, Vivek Gautam wrote:
Hi Balbi,
On Sat, Mar 2, 2013 at 6:55 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Now that machines may select the mode of working of DWC3 (HOST only
Hi,
On Sat, Mar 2, 2013 at 9:23 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Sat, 2 Mar 2013, Vivek Gautam wrote:
By enabling runtime pm in this driver allows users of
xhci-plat to enter into runtime pm. This is not full
runtime pm support (AKA xhci-plat doesn't actually power
management of usb PHYs in dwc3 core
driver instead of in any glue layer.
- Splitting the patch [PATCH 4/4] usb: phy: samsung: Enable runtime power
management on samsung-usb
to required number to bifurcate functionality.
Vivek Gautam (10):
usb: phy: Add APIs for runtime power management
Exynos5250 has external PLL (XusbXTI) for USB 3.0 PHY's
ref_pad_clk. So use this clock based on availability of
gpio to power control this PLL, otherwise use internal
clock only from XXTI.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/phy/samsung-usb3phy.c | 14
Allow dwc3 to enable auto power management only after its PHYs
are initialized so that any further PHY handling by dwc3's
runtime power management callbacks is fine.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/core.c |8
1 files changed, 4 insertions
Enabling runtime power management on dwc3-exynos
letting dwc3 controller to be autosuspended on exynos
platform when not in use.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff
By enabling runtime pm in this driver allows users of
xhci-plat to enter into runtime pm. This is not full
runtime pm support (AKA xhci-plat doesn't actually power
anything off when in runtime suspend mode) but,
just basic enablement.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
CC: Doug
Enable autosuspending of Samsung usb3.0 PHY
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/phy/samsung-usb3phy.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/samsung-usb3phy.c
b/drivers/usb/phy/samsung-usb3phy.c
index
The PHY controller can choose between ref_pad_clk (XusbXTI-external PLL),
or EXTREFCLK (XXTI-internal clock crystal) to generate the required clock.
Adding the provision for ref_pad_clk here.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/phy/samsung-usb3phy.c | 46
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
include/linux/usb/phy.h | 26 ++
1 files changed, 26 insertions
Right now it doesn't handle full runtime suspend/resume
functionality. However it allows to handle PHYs' sleep
and wakeup across runtime suspend/resume.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/core.c | 27 +++
1 files changed, 27
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