Colin Cross ccr...@android.com writes:
On Tue, Mar 13, 2012 at 5:28 PM, Colin Cross ccr...@android.com wrote:
On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman khil...@ti.com wrote:
[...]
Checking the ready_count seemed like an easy way to do this, but did you
have any other mechanisms in mind
On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman khil...@ti.com wrote:
Hi Colin,
On 12/21/2011 01:09 AM, Colin Cross wrote:
To use coupled cpuidle states, a cpuidle driver must:
[...]
Provide a struct cpuidle_state.enter function for each state
that affects multiple cpus. This
On Wed, Dec 21, 2011 at 4:12 AM, Arjan van de Ven ar...@linux.intel.com wrote:
On 12/21/2011 10:55 AM, Colin Cross wrote:
On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven ar...@linux.intel.com
wrote:
On 12/21/2011 10:40 AM, Colin Cross wrote:
this smells fundamentally racey to me; you can
On Tue, Mar 13, 2012 at 5:28 PM, Colin Cross ccr...@android.com wrote:
On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman khil...@ti.com wrote:
Hi Colin,
On 12/21/2011 01:09 AM, Colin Cross wrote:
To use coupled cpuidle states, a cpuidle driver must:
[...]
Provide a struct
On 3/13/2012 4:52 PM, Kevin Hilman wrote:
Checking the ready_count seemed like an easy way to do this, but did you
have any other mechanisms in mind for CPUs to communicate that they've
exited/aborted?
this indeed is the tricky part (which I warned about earlier);
I've spent quite a lot of
On Tue, Mar 13, 2012 at 7:04 PM, Arjan van de Ven ar...@linux.intel.com wrote:
On 3/13/2012 4:52 PM, Kevin Hilman wrote:
Checking the ready_count seemed like an easy way to do this, but did you
have any other mechanisms in mind for CPUs to communicate that they've
exited/aborted?
this indeed
On Wed, Feb 1, 2012 at 10:07 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Feb 01, 2012 at 05:30:15PM +, Colin Cross wrote:
On Wed, Feb 1, 2012 at 6:59 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Feb 01, 2012 at 12:13:26PM +, Vincent Guittot wrote:
Hi Colin,
Sorry for this late reply
On 27 January 2012 18:32, Colin Cross ccr...@android.com wrote:
On Fri, Jan 27, 2012 at 12:54 AM, Vincent Guittot
vincent.guit...@linaro.org wrote:
On 20 January 2012 21:40, Colin Cross ccr...@android.com wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel
On Wed, Feb 01, 2012 at 12:13:26PM +, Vincent Guittot wrote:
[...]
In your patch, you put in safe state (WFI for most of platform) the
cpus that become idle and these cpus are woken up each time a new cpu
of the cluster becomes idle. Then, the cluster state is chosen and the
cpus
On Wed, Feb 1, 2012 at 6:59 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Feb 01, 2012 at 12:13:26PM +, Vincent Guittot wrote:
[...]
In your patch, you put in safe state (WFI for most of platform) the
cpus that become idle and these cpus are woken up each time a new
On Wed, Feb 01, 2012 at 05:30:15PM +, Colin Cross wrote:
On Wed, Feb 1, 2012 at 6:59 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Feb 01, 2012 at 12:13:26PM +, Vincent Guittot wrote:
[...]
In your patch, you put in safe state (WFI for most of platform) the
On 01/25/2012 03:04 PM, Daniel Lezcano wrote:
On 01/20/2012 09:40 PM, Colin Cross wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a generic way the cpu
dependencies.
What is the status of this
On 20 January 2012 21:40, Colin Cross ccr...@android.com wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a generic way the cpu
dependencies.
What is the status of this patchset ?
I can't do
On Fri, Jan 27, 2012 at 12:54 AM, Vincent Guittot
vincent.guit...@linaro.org wrote:
On 20 January 2012 21:40, Colin Cross ccr...@android.com wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a
On 01/20/2012 09:40 PM, Colin Cross wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a generic way the cpu
dependencies.
What is the status of this patchset ?
I can't do much with it right now,
On 12/21/2011 01:09 AM, Colin Cross wrote:
On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
will
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a generic way the cpu
dependencies.
What is the status of this patchset ?
I can't do much with it right now, because I don't have any devices
that can
On Wed, Jan 4, 2012 at 1:41 AM, Kevin Hilman khil...@ti.com wrote:
Colin Cross ccr...@android.com writes:
This patch series implements an alternative solution, where each
cpu will wait in the WFI state until all cpus are ready to enter
a coupled state, at which point the coupled state
Colin Cross ccr...@android.com writes:
This patch series implements an alternative solution, where each
cpu will wait in the WFI state until all cpus are ready to enter
a coupled state, at which point the coupled state function will
be called on all cpus at approximately the same time.
This
On Thu, Dec 22, 2011 at 1:12 AM, Colin Cross ccr...@android.com wrote:
On Wed, Dec 21, 2011 at 11:36 AM, Arjan van de Ven
ar...@linux.intel.com wrote:
.. or it enters WFI, and a physical device sends it an interrupt,
at which point it exits.
None of the cpus will return to the idle loop
On 12/22/2011 9:35 AM, Shilimkar, Santosh wrote:
Indeed. The SOCs, Arch's which does support low power
state independently and doesn't need any co-ordination between CPU's
will continue to work same way as before with this series.
btw I think you misunderstand; I don't object to a need for
On Thu, Dec 22, 2011 at 2:23 PM, Arjan van de Ven ar...@linux.intel.com wrote:
On 12/22/2011 9:35 AM, Shilimkar, Santosh wrote:
Indeed. The SOCs, Arch's which does support low power
state independently and doesn't need any co-ordination between CPU's
will continue to work same way as before
On 12/21/2011 1:09 AM, Colin Cross wrote:
On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
On Wed, Dec 21, 2011 at 1:02 AM, Arjan van de Ven ar...@linux.intel.com wrote:
On 12/21/2011 1:09 AM, Colin Cross wrote:
On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be
On 12/21/2011 10:40 AM, Colin Cross wrote:
this smells fundamentally racey to me; you can get an interrupt one
cycle after you think you're done, but before the last guy enters WFI...
how do you solve that issue ?
All the cpus have interrupts off when they increment the counter, so
they
On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven ar...@linux.intel.com wrote:
On 12/21/2011 10:40 AM, Colin Cross wrote:
this smells fundamentally racey to me; you can get an interrupt one
cycle after you think you're done, but before the last guy enters WFI...
how do you solve that issue ?
On 12/21/2011 10:55 AM, Colin Cross wrote:
On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven ar...@linux.intel.com
wrote:
On 12/21/2011 10:40 AM, Colin Cross wrote:
this smells fundamentally racey to me; you can get an interrupt one
cycle after you think you're done, but before the last guy
On Wed, Dec 21, 2011 at 4:12 AM, Arjan van de Ven ar...@linux.intel.com wrote:
On 12/21/2011 10:55 AM, Colin Cross wrote:
On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven ar...@linux.intel.com
wrote:
On 12/21/2011 10:40 AM, Colin Cross wrote:
this smells fundamentally racey to me; you can
.. or it enters WFI, and a physical device sends it an interrupt,
at which point it exits.
None of the cpus will return to the idle loop until all cpus have
decremented the ready counter back to 0, so they can't wrap around
again.
yikes, so you IPI all the cpus on the first exit.
that
On Wed, Dec 21, 2011 at 11:36 AM, Arjan van de Ven
ar...@linux.intel.com wrote:
.. or it enters WFI, and a physical device sends it an interrupt,
at which point it exits.
None of the cpus will return to the idle loop until all cpus have
decremented the ready counter back to 0, so they can't
On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
will corrupt the gic state unless the other cpu
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