* Roger Quadros rog...@ti.com [150731 03:24]:
One more observation I've had is that using irqchip modelling for
the 2 NAND events causes a performance impact.
Using mtd_oobtest I see the following on dra7-evm
1) v4.2-rc4 with prefetch-polled (no IRQs used)
mtd_speedtest: eraseblock
On 29/07/15 15:06, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
On 29/07/15 17:08, nick wrote:
On 2015-07-29 09:52 AM, Roger Quadros wrote:
On 29/07/15 15:13, nick wrote:
On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren
On 29/07/15 18:26, nick wrote:
On 2015-07-29 11:12 AM, Roger Quadros wrote:
On 29/07/15 17:08, nick wrote:
On 2015-07-29 09:52 AM, Roger Quadros wrote:
On 29/07/15 15:13, nick wrote:
On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt
On 29/07/15 15:13, nick wrote:
On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
in the GPMC driver and complicating it with irqchip modeling.
I don't think it's a
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
in the GPMC driver and
On 13/07/15 16:32, nick wrote:
On 2015-07-13 09:21 AM, Roger Quadros wrote:
On 13/07/15 16:15, nick wrote:
On 2015-07-13 09:12 AM, Roger Quadros wrote:
On 13/07/15 16:03, nick wrote:
On 2015-07-13 09:01 AM, Tony Lindgren wrote:
* nick xerofo...@gmail.com [150713 05:54]:
On
On 13/07/15 16:15, nick wrote:
On 2015-07-13 09:12 AM, Roger Quadros wrote:
On 13/07/15 16:03, nick wrote:
On 2015-07-13 09:01 AM, Tony Lindgren wrote:
* nick xerofo...@gmail.com [150713 05:54]:
On 2015-07-13 08:40 AM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
* nick xerofo...@gmail.com [150713 05:54]:
On 2015-07-13 08:40 AM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
What is the best map we should use for irqchip?
Some Socs have 4 WAIT pins, some have 3 and some have 2.
Should we start with 0,1,2, for the wait
On 13/07/15 16:03, nick wrote:
On 2015-07-13 09:01 AM, Tony Lindgren wrote:
* nick xerofo...@gmail.com [150713 05:54]:
On 2015-07-13 08:40 AM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
What is the best map we should use for irqchip?
Some Socs have 4 WAIT pins,
* Roger Quadros rog...@ti.com [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
in the GPMC driver and complicating it with irqchip modeling.
I don't think it's a good idea to allow external drivers to
tinker
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
in the GPMC driver and complicating it with irqchip modeling.
Let's manage the interrupt registers directly in the NAND driver
and get rid of irqchip model from GPMC driver.
Get rid
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