From: Hiroshi DOYU <hiroshi.d...@nokia.com>
The L2 pagetable should align on 1KB since the lower 10 bits of L2
pagetable address are not used by DSP H/W.
Signed-off-by: Hiroshi DOYU <hiroshi.d...@nokia.com>
---
drivers/dsp/bridge/wmd/tiomap3430.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c
b/drivers/dsp/bridge/wmd/tiomap3430.c
index 2ab585d..5a858bd 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -1080,8 +1080,7 @@ static DSP_STATUS WMD_DEV_Create(OUT struct
WMD_DEV_CONTEXT **ppDevContext,
pPtAttrs->L2NumPages = ((DMMPOOLSIZE >> 20) + 6);
pPtAttrs->L2size = HW_MMU_COARSE_PAGE_SIZE *
pPtAttrs->L2NumPages;
- align_size = 4; /* Make it u32 aligned */
- /* we like to get aligned on L1 table size */
+ align_size = 1 << 10; /* L2 pagetable alignement */
pg_tbl_va = (u32)MEM_AllocPhysMem(pPtAttrs->L2size,
align_size, &pg_tbl_pa);
pPtAttrs->L2TblAllocPa = pg_tbl_pa;
--
1.6.0.4
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