On 09/08/2014 06:41 PM, Tony Lindgren wrote:
> * Sebastian Andrzej Siewior [140905 12:28]:
>> This problem has not been seen on DRA7 or beaglebone (OMAP3). I am not
>> sure if this is UART-IP core specific or DMA engine.
>
> Maybe check this comment for future reference too because
> beaglebone a
* Sebastian Andrzej Siewior [140905 12:28]:
> This problem has not been seen on DRA7 or beaglebone (OMAP3). I am not
> sure if this is UART-IP core specific or DMA engine.
Maybe check this comment for future reference too because
beaglebone and bealeboard do different things for PM.. Do
you mean
At least on AM335x the following problem exists: Even if the TX FIFO is
empty and a TX transfer is programmed (and started) the UART does not
trigger the DMA transfer.
After $TRESHOLD number of bytes have been written to the FIFO manually the
UART reevaluates the whole situation and decides that no
