* Tony Lindgren t...@atomide.com [150323 08:58]:
* Tero Kristo t-kri...@ti.com [150323 06:25]:
This code is generating these compile time warnings for me:
CC drivers/clk/ti/fapll.o
drivers/clk/ti/fapll.c: In function ‘ti_fapll_synth_set_rate’:
drivers/clk/ti/fapll.c:394:5:
On 03/24/2015 06:37 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150323 08:58]:
* Tero Kristo t-kri...@ti.com [150323 06:25]:
This code is generating these compile time warnings for me:
CC drivers/clk/ti/fapll.o
drivers/clk/ti/fapll.c: In function
On 03/23/2015 12:35 AM, Tony Lindgren wrote:
We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.
Let's also add a define
* Tero Kristo t-kri...@ti.com [150323 06:25]:
On 03/23/2015 12:35 AM, Tony Lindgren wrote:
+static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
+unsigned long rate,
+unsigned long parent_rate)
+{
+u32
We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.
Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.
