[PATCH 2/5] phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support

Exynos7 SoC has now separate gate control for 125MHz pipe3 phy clock, as well as 60MHz utmi phy clock. So get the same and control in the phy-exynos5-usbdrd driver. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt|4

Re: [PATCH 2/5] phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support

On Thu, Aug 28, 2014 at 09:01:57AM +0100, Vivek Gautam wrote: Exynos7 SoC has now separate gate control for 125MHz pipe3 phy clock, as well as 60MHz utmi phy clock. So get the same and control in the phy-exynos5-usbdrd driver. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com ---