On Thu, Jan 29, 2009 at 10:57:24PM -0700, Paul Walmsley wrote:
On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
Final point... this is only called from the function below, which also
checks that clk and clk-dpll_data are both non-NULL. So these checks
are unnecessary.
Okay. Do you
On Tue, Jan 27, 2009 at 07:12:47PM -0700, Paul Walmsley wrote:
+/* Non-CORE DPLL rate set code */
+
+/*
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel:
On Thu, 29 Jan 2009, Russell King - ARM Linux wrote:
On Tue, Jan 27, 2009 at 07:12:47PM -0700, Paul Walmsley wrote:
+/* Non-CORE DPLL rate set code */
+
+/*
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL
Add non-CORE DPLL rate set code and M,N programming for OMAP3.
Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework.
You may see some warnings on rate sets from the freqsel code. The
table that TI presented in the 3430 TRM Rev F does not cover Fint
75, which definitely occurs in
Since it's been posted to lists, comments are going to be made...
On Tue, Jan 27, 2009 at 07:12:47PM -0700, Paul Walmsley wrote:
+ /*
+ * According to the 12-5 CDP code from TI, Limitation 2.5
+ * on 3430ES1 prevents us from changing DPLL multipliers or dividers
+ * on
On Wed, Jan 28, 2009 at 10:10:56PM +, Russell King - ARM Linux wrote:
Since it's been posted to lists, comments are going to be made...
On Tue, Jan 27, 2009 at 07:12:47PM -0700, Paul Walmsley wrote:
+ /*
+* According to the 12-5 CDP code from TI, Limitation 2.5
+* on
