On Wed, Jan 28, 2009 at 12:08:26PM -0700, Paul Walmsley wrote:
static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
u16 freqsel;
struct dpll_data *dd;
+ int ret;
So 'ret' is a new variable...
if (!clk || !rate)
return
On Wed, Jan 28, 2009 at 12:08:26PM -0700, Paul Walmsley wrote:
This patch causes a DPLL to enter bypass when it is instructed to set
its rate to that of its bypass clock. Previously this was only possible
after setting the DPLL rate, then disabling and re-enabling it.
The more I think about
Hello Russell,
this E-mail responds to your comments on patches C 04 through C 08.
My understanding is that you'd like me to:
1. Compress patches C 04 through C 09;
2. Modify omap3_noncore_dpll_enable() to move the if (!ret)
clk-rate = rate outside and below the conditional;
3. Remove
