Hi Paul,
On 08/01/2012 10:36 AM, Paul Walmsley wrote:
Hi Jon et al,
Here's what I'm planning to queue here. The only changes from what Jon
posted are the patch changelog and some checkpatch fixes. If anyone
has any final comments, please let me know.
- Paul
From: Paul Walmsley
Hi Jon,
On Mon, 8 Oct 2012, Jon Hunter wrote:
I was looking at what got merged and it appears that the above code was
added to the omap2 clkdm enable/disable functions and not omap3. I believe
that is a mistake? If so the below fixes this.
Yep looks like either a mismerge or a victim of a
On Wed, Aug 1, 2012 at 9:06 PM, Paul Walmsley p...@pwsan.com wrote:
Hi Jon et al,
Here's what I'm planning to queue here. The only changes from what Jon
posted are the patch changelog and some checkpatch fixes. If anyone
has any final comments, please let me know.
- Paul
From: Paul
Hi Jon,
On Tue, 31 Jul 2012, Jon Hunter wrote:
Sorry for all the emails. However, I wanted to get this out to you as
I am due to be out for a couple weeks.
So I have updated your patch [1] with the following changes ...
1. Re-based on top of your omap3 clock domain fix [2]
2. Modified
Hi Jon et al,
Here's what I'm planning to queue here. The only changes from what Jon
posted are the patch changelog and some checkpatch fixes. If anyone
has any final comments, please let me know.
- Paul
From: Paul Walmsley p...@pwsan.com
Date: Wed, 1 Aug 2012 09:11:20 -0600
Subject: [PATCH]
Hi Paul,
On 08/01/2012 10:08 AM, Paul Walmsley wrote:
Hi Jon,
On Tue, 31 Jul 2012, Jon Hunter wrote:
Sorry for all the emails. However, I wanted to get this out to you as
I am due to be out for a couple weeks.
So I have updated your patch [1] with the following changes ...
1.
Hi Paul,
On 08/01/2012 10:36 AM, Paul Walmsley wrote:
Hi Jon et al,
Here's what I'm planning to queue here. The only changes from what Jon
posted are the patch changelog and some checkpatch fixes. If anyone
has any final comments, please let me know.
- Paul
From: Paul Walmsley
Hi Paul,
On 07/30/2012 11:36 PM, Jon Hunter wrote:
Hi Paul,
On 07/30/2012 06:26 PM, Jon Hunter wrote:
[...]
1. When HWMOD attempts to disable the clock domain for OMAP2/3 devices
we simply return without doing anything. Not sure if it is safe to
remove this but I can do some
Hi Paul,
On 07/12/2012 04:17 PM, Paul Walmsley wrote:
[snip]
@@ -170,6 +201,18 @@ static int omap2_clkdm_clk_enable(struct clockdomain
*clkdm)
if (!clkdm-clktrctrl_mask)
return 0;
+ /*
+ * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+ *
Hi Paul,
On 07/31/2012 01:16 PM, Jon Hunter wrote:
[snip]
So scratch item #1 above. As Rajendra pointed out in another thread this
is not right. The only other comment I have with your patch is maybe we
need to add the following to prevent the EMU PD being idled during
boot-up if enabled
Hi Paul,
On 07/16/2012 01:38 PM, Paul Walmsley wrote:
Hi Jon,
On Mon, 16 Jul 2012, Jon Hunter wrote:
Yes I see that makes sense. However, patch #7 has already changed the
mapping of the flags. I had intended that patch #7 and #8 would be
applied together. However, I could see that patch
Hi Paul,
On 07/30/2012 06:26 PM, Jon Hunter wrote:
[...]
1. When HWMOD attempts to disable the clock domain for OMAP2/3 devices
we simply return without doing anything. Not sure if it is safe to
remove this but I can do some more testing on OMAP2/3.
commit
Hi Paul,
On 07/16/2012 01:38 PM, Paul Walmsley wrote:
Hi Jon,
On Mon, 16 Jul 2012, Jon Hunter wrote:
Yes I see that makes sense. However, patch #7 has already changed the
mapping of the flags. I had intended that patch #7 and #8 would be
applied together. However, I could see that patch
Hi Will,
On 07/13/2012 09:00 AM, Will Deacon wrote:
Jon,
[cutting out realms of context!]
On Fri, Jul 13, 2012 at 02:54:59PM +0100, Jon Hunter wrote:
Another proposal I also thought of is re-working the flags to describe
the HW mode to be used when turning on the CLKDM, when the CLKDM is
Hi Paul,
On 07/13/2012 04:00 PM, Paul Walmsley wrote:
[...]
Unfortunately, although this works it does make the flags a bit less
clearer. The upside is the solution is simpler.
Yeah, the problem is the clockdomain CLKDM_CAN_* flags are just intended
to represent the available bits from
Hi Jon,
On Mon, 16 Jul 2012, Jon Hunter wrote:
Yes I see that makes sense. However, patch #7 has already changed the
mapping of the flags. I had intended that patch #7 and #8 would be
applied together. However, I could see that patch #7 can be taken just
to eliminate using the SW_SLEEP
Hi Paul,
On 07/16/2012 01:38 PM, Paul Walmsley wrote:
Hi Jon,
On Mon, 16 Jul 2012, Jon Hunter wrote:
Yes I see that makes sense. However, patch #7 has already changed the
mapping of the flags. I had intended that patch #7 and #8 would be
applied together. However, I could see that patch
Hi Paul,
On 07/12/2012 04:17 PM, Paul Walmsley wrote:
Hello Jon
On Thu, 7 Jun 2012, Jon Hunter wrote:
By removing the CLKDM_CAN_ENABLE_AUTO flag, the EMU clock domain will always
remain on and hence, this will break low-power modes. The EMU clock domain
only
support the SW_WKUP and
Jon,
[cutting out realms of context!]
On Fri, Jul 13, 2012 at 02:54:59PM +0100, Jon Hunter wrote:
Another proposal I also thought of is re-working the flags to describe
the HW mode to be used when turning on the CLKDM, when the CLKDM is
active and when the CLKDM is shut down. So instead of
Hi Will,
On 07/13/2012 09:00 AM, Will Deacon wrote:
Jon,
[cutting out realms of context!]
Thanks! My inbox thanks you too ;-)
On Fri, Jul 13, 2012 at 02:54:59PM +0100, Jon Hunter wrote:
Another proposal I also thought of is re-working the flags to describe
the HW mode to be used when
Hi Jon
On Fri, 13 Jul 2012, Jon Hunter wrote:
On 07/12/2012 04:17 PM, Paul Walmsley wrote:
On Thu, 7 Jun 2012, Jon Hunter wrote:
Hmm, it would be nice if we could keep the CLKDM_CAN_* flags matching the
hardware capabilities. Looking at the 4430 TRM Rev X Table 3-744
Hello Jon
On Thu, 7 Jun 2012, Jon Hunter wrote:
By removing the CLKDM_CAN_ENABLE_AUTO flag, the EMU clock domain will always
remain on and hence, this will break low-power modes. The EMU clock domain
only
support the SW_WKUP and HW_AUTO transition modes (for more details refer to
the
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