On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for
additional parameters. Have a look at:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
First get the regmap, then the 1st
On 10/01/2014 10:45 AM, Roger Quadros wrote:
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for
additional parameters. Have a look at:
On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote:
On 10/01/2014 10:45 AM, Roger Quadros wrote:
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for
additional parameters. Have a
On 10/01/2014 11:06 AM, Roger Quadros wrote:
On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote:
On 10/01/2014 10:45 AM, Roger Quadros wrote:
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any
On 10/01/2014 01:01 PM, Marc Kleine-Budde wrote:
On 10/01/2014 11:06 AM, Roger Quadros wrote:
On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote:
On 10/01/2014 10:45 AM, Roger Quadros wrote:
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but
On 10/01/2014 12:12 PM, Roger Quadros wrote:
On 10/01/2014 01:01 PM, Marc Kleine-Budde wrote:
On 10/01/2014 11:06 AM, Roger Quadros wrote:
On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote:
On 10/01/2014 10:45 AM, Roger Quadros wrote:
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote:
On
Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P
What on earth were the HW engineers thinking
Let's test my RNG on the bit-placement of this register :)
...if we just have the instance parameter in the syscon phandle, we have
to put the mapping
On 10/01/2014 01:43 PM, Wolfram Sang wrote:
Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P
What on earth were the HW engineers thinking
Let's test my RNG on the bit-placement of this register :)
:D
...if we just have the instance parameter
On 10/01/2014 12:57 PM, Roger Quadros wrote:
...if we just have the instance parameter in the syscon phandle, we have
to put the mapping into the driver, which makes IMHO no sense, because
you have to touch the driver, if there is another SoC with the DCAN core.
My guess is that TI won't
Is it OK to create a new platform_data structure for CAN and put the type and
raminit start/stop
bits there?
I'd say yes, don't see a reason not to.
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On 10/01/2014 12:43 PM, Wolfram Sang wrote:
compatible = commodore,c64ultra, bosch,d_can;
\o/
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On 09/30/2014 03:26 PM, Wolfram Sang wrote:
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared
On 09/30/2014 04:52 PM, Wolfram Sang wrote:
+- ti,raminit-syscon : Handle to system control region that contains
the
+RAMINIT register. If specified, the second memory
resource
+in the reg property must index into the RAMINIT
+
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.
On 09/30/2014 04:26 PM, Wolfram Sang wrote:
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared
On 09/30/2014 04:45 PM, Marc Kleine-Budde wrote:
On 09/30/2014 03:26 PM, Wolfram Sang wrote:
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
As just TI is using this out of band RAMINIT mechanism, should it be
ti,syscon or just syscon?
Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we
need an (optional) way to describe that. However, accessing syscon
registers in general is not TI specific and a generic way
On 09/30/2014 04:02 PM, Roger Quadros wrote:
On 09/30/2014 04:45 PM, Marc Kleine-Budde wrote:
On 09/30/2014 03:26 PM, Wolfram Sang wrote:
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx
+- ti,raminit-syscon : Handle to system control region that contains
the
+RAMINIT register. If specified, the second memory
resource
+in the reg property must index into the RAMINIT
+register within the syscon region
On 09/30/2014 04:19 PM, Wolfram Sang wrote:
As just TI is using this out of band RAMINIT mechanism, should it be
ti,syscon or just syscon?
Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we
need an (optional) way to describe that. However, accessing syscon
registers
On Tue, Sep 30, 2014 at 04:22:08PM +0200, Marc Kleine-Budde wrote:
On 09/30/2014 04:19 PM, Wolfram Sang wrote:
As just TI is using this out of band RAMINIT mechanism, should it be
ti,syscon or just syscon?
Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we
On 09/30/2014 04:49 PM, Wolfram Sang wrote:
On Tue, Sep 30, 2014 at 04:22:08PM +0200, Marc Kleine-Budde wrote:
On 09/30/2014 04:19 PM, Wolfram Sang wrote:
As just TI is using this out of band RAMINIT mechanism, should it be
ti,syscon or just syscon?
Yes, only TI uses this out-of-band
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for
additional parameters. Have a look at:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
First get the regmap, then the 1st argument is the offset in the regmap,
the 2nd and 3rd could be the bits.
So, for one
On 09/30/2014 05:25 PM, Wolfram Sang wrote:
Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for
additional parameters. Have a look at:
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
First get the regmap, then the 1st argument is the offset in the regmap,
the 2nd
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.
Provides a more generic mechanism to specify the RAMINIT
register location
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