On Sat, Feb 21, 2015 at 06:11:29PM +0100, Thomas Niederprüm wrote:
> This patch fixes faulty behaviour in a setup where the input clock for the
> SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be
> master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must
> not be
This patch fixes faulty behaviour in a setup where the input clock for the
SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be
master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must
not be configured as output pin. Otherwise the input clock is messed up
horribly.