Re: [PATCH v3] gpio/omap: implement irq mask/disable with proper semantic.

2013-04-26 Thread Jon Hunter
On 04/22/2013 03:54 AM, Andreas Fenkart wrote: > When a gpio interrupt is masked, the gpio event will still be latched in > the interrupt status register so when you unmask it later you may get an > interrupt straight away. However, if the interrupt is disabled then gpio > events occurring will no

Re: [PATCH v3] gpio/omap: implement irq mask/disable with proper semantic.

2013-04-25 Thread Jon Hunter
On 04/22/2013 03:54 AM, Andreas Fenkart wrote: > When a gpio interrupt is masked, the gpio event will still be latched in > the interrupt status register so when you unmask it later you may get an > interrupt straight away. However, if the interrupt is disabled then gpio > events occurring will no

Re: [PATCH v3] gpio/omap: implement irq mask/disable with proper semantic.

2013-04-25 Thread Jon Hunter
On 04/22/2013 03:54 AM, Andreas Fenkart wrote: > When a gpio interrupt is masked, the gpio event will still be latched in > the interrupt status register so when you unmask it later you may get an > interrupt straight away. However, if the interrupt is disabled then gpio > events occurring will no

Re: [PATCH v3] gpio/omap: implement irq mask/disable with proper semantic.

2013-04-23 Thread Kevin Hilman
Andreas Fenkart writes: > When a gpio interrupt is masked, the gpio event will still be latched in > the interrupt status register so when you unmask it later you may get an > interrupt straight away. However, if the interrupt is disabled then gpio > events occurring will not be latched/stored. >

[PATCH v3] gpio/omap: implement irq mask/disable with proper semantic.

2013-04-22 Thread Andreas Fenkart
When a gpio interrupt is masked, the gpio event will still be latched in the interrupt status register so when you unmask it later you may get an interrupt straight away. However, if the interrupt is disabled then gpio events occurring will not be latched/stored. Signed-off-by: Andreas Fenkart --