Re: [PATCH v3 4/7] ARM: dts: dra7-clock: Add l3init_960m_gfclk clock gate

On 05/05/2014 12:54 PM, Roger Quadros wrote: This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs. Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812.

[PATCH v3 4/7] ARM: dts: dra7-clock: Add l3init_960m_gfclk clock gate

This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs. Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL Use l3init_960m_gfclk as parent of