Not that this is particularly related to DVFS, but:
On Thu, 5 May 2011, Colin Cross wrote:
> On Thu, May 5, 2011 at 2:08 PM, Cousson, Benoit wrote:
>
> > Colin Cross wrote:
>
> >> omap_hwmod is entirely omap specific, and any generic solution cannot
> >> be based on it.
> >
> > For the moment,
On Fri, May 6, 2011 at 6:08 AM, Cousson, Benoit wrote:
[]
>
> Devices will indeed never care about voltage directly, but that will happen
> indirectly because of:
> - voltage domains dependency: Changing the MPU or IVA voltage domain might
> force the CORE voltage to increase its voltage due to HW
On Thu, May 5, 2011 at 2:08 PM, Cousson, Benoit wrote:
> On 5/5/2011 8:11 AM, Colin Cross wrote:
>>
>> On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoit wrote:
>>>
>>> (Cc folks with some DVFS interest)
>>>
>>> Hi Colin,
>>>
>>> On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are app
On 5/5/2011 8:11 AM, Colin Cross wrote:
On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoit wrote:
(Cc folks with some DVFS interest)
Hi Colin,
On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are approaching a common clock management implementation,
I was thinking it might be the right pla
On Wed, May 04, 2011 at 11:50:52PM -0700, Colin Cross wrote:
> True, that was an oversimplificaiton. I meant the minimum voltage that
> scales with clock frequencies only depends on the clock frequency, not
> the device. Devices do need to be able to specify a higher minimum
> voltage, and the re
On Wed, May 4, 2011 at 11:35 PM, Paul Walmsley wrote:
> On Wed, 4 May 2011, Colin Cross wrote:
>
>> Imagine a chip where a clock can feed devices A, B, and C. If the
>> devices are always clocked at the same rate, and can't gate their
>> clocks, the minimum voltage that can be applied to a rail i
On Wed, 4 May 2011, Colin Cross wrote:
> Imagine a chip where a clock can feed devices A, B, and C. If the
> devices are always clocked at the same rate, and can't gate their
> clocks, the minimum voltage that can be applied to a rail is
> determined ONLY by the rate of the clock.
That's not so
On Thu, 5 May 2011, Cousson, Benoit wrote:
> Those kinds of exceptions are somehow the rules for an OMAP4 device.
> Most scalable devices are using some internal dividers or even internal
> PLL to control the scalable clock rate (DSS, HSI, MMC, McBSP... the
> OMAP4430 Data Manual [1] is providi
On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoit wrote:
> (Cc folks with some DVFS interest)
>
> Hi Colin,
>
> On Fri, 22 Apr 2011, Colin Cross wrote:
>>
>> Now that we are approaching a common clock management implementation,
>> I was thinking it might be the right place to put a common dvfs
>> i
(Cc folks with some DVFS interest)
Hi Colin,
On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are approaching a common clock management implementation,
I was thinking it might be the right place to put a common dvfs
implementation as well.
It is very common for SoC manufacturers to provide
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