a quick followup on this:
On Thu, 11 Dec 2008, Paul Walmsley wrote:
> With voltage change:
> MPU @ 83MHz: 130 ticks (3.97 ms) worst-case
It recently occurred to me that part of this 130 tick time is due to the
udelay()s in the SmartReflex code. My test code did not update
loops_per_jiffy wh
Tero Kristo writes:
> This patch set provides DVFS support for OMAP3. First 16 patches contain
> clock framework modifications from Paul Walmsley, which are needed for VDD2
> OPP clock control to work properly. Rest of the patches are misc fixes for
> DVFS control, providing locking interface for
Hello,
For anyone interested, here are some worst case measurements for CORE DVFS
transition times with patches 1-16.
The test board was a 3430SDP ES2.0 GP. Tests were run both with and
without changing the VDD2 voltage; and at two different MPU frequencies.
No voltage change:
MPU @ 381MHz:
This patch set provides DVFS support for OMAP3. First 16 patches contain
clock framework modifications from Paul Walmsley, which are needed for VDD2
OPP clock control to work properly. Rest of the patches are misc fixes for
DVFS control, providing locking interface for OPPs and providing support
fo
