On Mon, 7 Oct 2013, Mike Turquette wrote:
Well it used to be that calling clk_set_rate(dpll, bypass_rate) would
put it in bypass, I don't know if that is still the case. But you are
right that having the implicit assumption that 'bypass rate' == 'DPLL in
bypass' is not safe since a bootloader
On Tue, 10 Sep 2013, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer nodes
clocks. I just think the check in the clkoutx2_recalc is wrong, and should be
enhanced to actually check what is the target mode for the clock once it is
enabled. Maybe
Quoting Paul Walmsley (2013-10-07 01:21:16)
On Tue, 10 Sep 2013, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes
clocks. I just think the check in the clkoutx2_recalc is wrong, and should
be
enhanced to actually check what is the
On 27/09/13 14:24, Tero Kristo wrote:
Tero, can you queue this patch? Or who should handle this?
I can't queue anything as I don't have maintainership on any of this
stuff. Paul / Tony should go with this.
Well, I mainly meant preparing a patch with proper description and
sending to
On 13/09/13 14:34, Kristo, Tero wrote:
On 09/13/2013 10:51 AM, Stefan Roese wrote:
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the
On 09/27/2013 11:41 AM, Tomi Valkeinen wrote:
On 13/09/13 14:34, Kristo, Tero wrote:
On 09/13/2013 10:51 AM, Stefan Roese wrote:
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes
Quoting Tero Kristo (2013-09-13 04:34:54)
On 09/13/2013 10:51 AM, Stefan Roese wrote:
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the clkoutx2_recalc is wrong,
and should be enhanced to actually check what is the target mode for
On 09/13/2013 10:51 AM, Stefan Roese wrote:
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the clkoutx2_recalc is wrong,
and should be enhanced to
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the clkoutx2_recalc is wrong,
and should be enhanced to actually check what is the target mode for the
clock once it is enabled. Maybe
On 28.08.2013 13:40, Tero Kristo wrote:
On 08/28/2013 01:14 PM, Tomi Valkeinen wrote:
On 28/08/13 12:48, Tero Kristo wrote:
On 08/28/2013 12:22 PM, Tomi Valkeinen wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
v3.11-rc7 + DSS DT patches.
I guess you are
On 09/10/2013 02:33 PM, Stefan Roese wrote:
On 28.08.2013 13:40, Tero Kristo wrote:
On 08/28/2013 01:14 PM, Tomi Valkeinen wrote:
On 28/08/13 12:48, Tero Kristo wrote:
On 08/28/2013 12:22 PM, Tomi Valkeinen wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
could try clk_enable for the clock before doing clk_set_rate.
Hmm, so is it required to enable the clock before setting the rate? If
On 10.09.2013 14:12, Tero Kristo wrote:
I debugged this a bit and found that this issue (dpll4_m4x2_ck clock is
not 2 times dpll4_m4_ck) results from this code:
arch/arm/mach-omap2/dpll3xxx.c:
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
could try clk_enable for the clock before doing clk_set_rate.
Hmm, so is it required to enable the clock before setting the rate? If
so, I think I'm using the clocks wrong in all the
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
could try clk_enable for the clock before doing clk_set_rate.
Hmm, so is it required to enable
On 09/10/2013 03:40 PM, Tomi Valkeinen wrote:
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
could try clk_enable for the clock before doing
Quoting Tero Kristo (2013-09-10 06:17:45)
On 09/10/2013 03:40 PM, Tomi Valkeinen wrote:
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
On Tue, Sep 10, 2013 at 2:17 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Tero Kristo (2013-09-10 06:17:45)
On 09/10/2013 03:40 PM, Tomi Valkeinen wrote:
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
v3.11-rc7 + DSS DT patches.
It looks to me that when setting the rate of a clock, its child clock's
rate is not updated correctly. Here's pieces of boot log (full log
attached):
Here my code prints the current clocks.
On 08/28/2013 12:22 PM, Tomi Valkeinen wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
v3.11-rc7 + DSS DT patches.
I guess you are not using the clock DT patches? Just making sure I
didn't break anything. :)
It looks to me that when setting the rate of a
On 28/08/13 12:48, Tero Kristo wrote:
On 08/28/2013 12:22 PM, Tomi Valkeinen wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
v3.11-rc7 + DSS DT patches.
I guess you are not using the clock DT patches? Just making sure I
didn't break anything. :)
No, plain
On 08/28/2013 01:14 PM, Tomi Valkeinen wrote:
On 28/08/13 12:48, Tero Kristo wrote:
On 08/28/2013 12:22 PM, Tomi Valkeinen wrote:
Hi,
I'm seeing odd clock behavior with Beagle, booting with DT. I'm using
v3.11-rc7 + DSS DT patches.
I guess you are not using the clock DT patches? Just making
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