Hi,
On 02/18/2014 11:43 AM, Paolo Pisati wrote:
HDMI codec dummy entries for Panda/ES.
Signed-off-by: Paolo Pisati paolo.pis...@canonical.com
---
Depends on 0f7f3d1 ASoC: hdmi-codec: Add devicetree binding with
documentation, eligible for a 3.14-rcX fix.
On 02/18/2014 08:27 AM, Tero Kristo wrote:
On 02/17/2014 06:13 PM, Florian Vaussard wrote:
Hi,
On 02/17/2014 01:29 PM, Tero Kristo wrote:
On 02/17/2014 01:27 PM, Florian Vaussard wrote:
Add the gpmc_fck clock, derived from l3_ick, and reference it from
the GPMC node to get it correctly
The GPMC clock is derived from l3_ick. The simplest solution is
to reference directly l3_ick to provide the GPMC fck in order to
get correct timings. The real management of the clock is left to
hwmod.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
---
arch/arm/boot/dts/omap4.dtsi | 2
Hello,
Trying to get my SMSC9221 working on OMAP4 with DT,
I faced a misconfigured gpmc_fck (dummy clock set to 0)
resulting in serveral division-by-zero, misconfigured
timings and driver lost in the La La Land.
To solve this, patch 1 removes gpmc_fck from the dummy
clocks, and patch 2 adds the
When arch/arm/mach-omap2/gpmc.c calls clk_get(..., fck), it will
get a dummy clock and try to use it. As the rate is configured to zero,
this will result in several divisions by zero, and misconfigured
timings, with devices on the bus being lost in the La La Land.
It is better to remove gpmc_fck
On Wed, Feb 19, 2014 at 10:15:24AM +0200, Peter Ujfalusi wrote:
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05..f4aeaa1 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++
On 02/19/2014 12:54 PM, Paolo Pisati wrote:
On Wed, Feb 19, 2014 at 10:15:24AM +0200, Peter Ujfalusi wrote:
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05..f4aeaa1 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++
Hi,
On 02/12/2014 11:46 AM, Kishon Vijay Abraham I wrote:
On Wednesday 29 January 2014 08:17 PM, Heikki Krogerus wrote:
Hi,
On Tue, Jan 28, 2014 at 10:30:36AM -0600, Felipe Balbi wrote:
On Tue, Jan 28, 2014 at 05:32:30PM +0200, Heikki Krogerus wrote:
On Mon, Jan 27, 2014 at 10:05:20AM
Few cleanups to reduce code indent,
Add pbias_regulator support and adapt omap_hsmmc to use pbias regulator
to configure required voltage on mmc1 pad(SD card) i/o rails on OMAP SoCs.
Balaji T K (7):
mmc: omap_hsmmc: use devm_regulator API
mmc: omap_hsmmc: handle vcc and vcc_aux independently
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git
Enable REGULATOR_PBIAS needed for SD card on most OMAPs.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/configs/omap2plus_defconfig |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig
b/arch/arm/configs/omap2plus_defconfig
index
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 37 +
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git
pbias register controls internal power supply to sd card i/o pads
in most OMAPs (OMAP2-5, DRA7).
Control bits for selecting voltage level and
enabling/disabling are in the same PBIAS register.
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
Acked-by: Mark Brown
remove pbias workaround
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c | 20 +---
1 files changed, 1 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
Add pbias regulator node as a child of system control
module - syscon.
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/dra7.dtsi | 17 +
arch/arm/boot/dts/omap2430.dtsi | 17 +
handle vcc and vcc_aux independently to reduce indent.
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c | 54 +++--
1 files changed, 25 insertions(+), 29 deletions(-)
diff --git
On 02/19/2014 11:15 AM, Florian Vaussard wrote:
Hello,
Trying to get my SMSC9221 working on OMAP4 with DT,
I faced a misconfigured gpmc_fck (dummy clock set to 0)
resulting in serveral division-by-zero, misconfigured
timings and driver lost in the La La Land.
To solve this, patch 1 removes
* Laurent Pinchart laurent.pinch...@ideasonboard.com [140218 07:05]:
Hi Igor,
On Tuesday 18 February 2014 16:03:44 Igor Grinberg wrote:
On 02/18/14 14:47, Laurent Pinchart wrote:
On Monday 10 February 2014 22:54:40 Laurent Pinchart wrote:
The camera sensor will soon require regulators
On Sun, 16 Feb 2014, Vaibhav Bedia wrote:
Use the correct register offset for issuing the
reset command in OMAP5. Since dev_inst is set dynamically
OMAP4 should not be affected by this change.
Signed-off-by: Vaibhav Bedia vaibhav.be...@gmail.com
Thanks, queued for v3.14-rc with Lokesh's
On Wed, 19 Feb 2014, Paul Walmsley wrote:
On Sun, 16 Feb 2014, Vaibhav Bedia wrote:
Use the correct register offset for issuing the
reset command in OMAP5. Since dev_inst is set dynamically
OMAP4 should not be affected by this change.
Signed-off-by: Vaibhav Bedia
On Mon, 17 Feb 2014, Lokesh Vutla wrote:
Add restart hook so that AM4372 builds can restart the platform.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Thanks, queued for v3.15.
- Paul
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On Wed, 5 Feb 2014, Illia Smyrnov wrote:
Commit 313a76e (ARM: OMAP2+: hwmod: Fix SOFTRESET logic) introduced
softreset bit cleaning right after set one. It is caused L3 error for
OMAP4 ISS because ISS register write occurs when ISS reset process is in
progress. Avoid this situation by
On Fri, 7 Feb 2014, Dave Gerlach wrote:
Since commit 65aa94b204d (ARM: OMAP4: clockdomain/CM code: Update supported
transition modes), on OMAP4, all CLKDMs support HW_AUTO so this is used
instead of SW_SLEEP for the idling of clockdomains. However, additional
SoCs now leverage the OMAP4
On Wed, 19 Feb 2014, Paul Walmsley wrote:
On Fri, 7 Feb 2014, Dave Gerlach wrote:
Since commit 65aa94b204d (ARM: OMAP4: clockdomain/CM code: Update supported
transition modes), on OMAP4, all CLKDMs support HW_AUTO so this is used
instead of SW_SLEEP for the idling of clockdomains.
Just FYI. Queued for v3.15 unless someone complains.
- Paul
-- Forwarded message --
Date: Fri, 7 Feb 2014 16:20:59 -0600
From: Dave Gerlach d-gerl...@ti.com
To: linux-omap@vger.kernel.org
Cc: Tony Lindgren t...@atomide.com, Paul Walmsley p...@pwsan.com,
Rajendra Nayak
On Fri, 10 Jan 2014, Suman Anna wrote:
The spinlock module's SYSCONFIG register on DRA7xx does not
support smart wakeup, and also does not have the CLKACTIVITY
field. The sysc data for spinlock module has been appropriately
fixed up to reflect the same.
Cc: Ambresh K ambr...@ti.com
On Fri, 10 Jan 2014, Suman Anna wrote:
AM43xx has a spinlock module which is identical to the
one present on AM33xx. Register the spinlock ocp_if link
so that the spinlock hwmod and associated omap_device can
be instantiated, and the runtime pm API could be used by
the OMAP hwspinlock
On Thu, 30 Jan 2014, Tomi Valkeinen wrote:
If CLK_SET_RATE_PARENT is set for a clkoutx2 clock, calling
clk_set_rate() on the clock skips the x2 multiplier as there are no
set_rate and round_rate functions defined for the clkoutx2.
This results in getting double the requested clock rates,
On Wed, Feb 19, 2014 at 1:25 PM, Paul Walmsley p...@pwsan.com wrote:
Just FYI. Queued for v3.15 unless someone complains.
No complains but i wanted to point out that with some additional
changes it's possible
to consolidate AM335x (and AM437x) very nicely with the rest of OMAP4+
PRM/CM code.
On Wed, 19 Feb 2014, Vaibhav Bedia wrote:
On Wed, Feb 19, 2014 at 1:25 PM, Paul Walmsley p...@pwsan.com wrote:
Just FYI. Queued for v3.15 unless someone complains.
No complains but i wanted to point out that with some additional
changes it's possible
to consolidate AM335x (and
On Fri, 17 Jan 2014, Tomi Valkeinen wrote:
Printing with unsigned long rates with %ld gives wrong result if the
rate is high enough. Fix this by using %lu.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
Thanks, queued for v3.15.
There's a series here that converts the OMAP clock code
On 02/19/2014 05:22 PM, Tero Kristo wrote:
On 02/19/2014 11:15 AM, Florian Vaussard wrote:
Hello,
Trying to get my SMSC9221 working on OMAP4 with DT,
I faced a misconfigured gpmc_fck (dummy clock set to 0)
resulting in serveral division-by-zero, misconfigured
timings and driver lost in the
On Fri, 17 Jan 2014, Tomi Valkeinen wrote:
omap2_dpll_round_rate() doesn't actually round the given rate, even if
the name and the description so hints. Instead it only tries to find an
exact rate match, or if that fails, return ~0 as an error.
In the past, we had rate tolerance code, which
On Wed, Feb 19, 2014 at 2:22 PM, Paul Walmsley p...@pwsan.com wrote:
On Wed, 19 Feb 2014, Vaibhav Bedia wrote:
On Wed, Feb 19, 2014 at 1:25 PM, Paul Walmsley p...@pwsan.com wrote:
Just FYI. Queued for v3.15 unless someone complains.
No complains but i wanted to point out that with some
On Wed, 19 Feb 2014, Vaibhav Bedia wrote:
After spending a lot of time looking at the code and PRCM specs for the
different chips i had come to the conclusion that in reality the Catalog
parts had the same hardware minus intelligence ;)
Did you look at the RTL?
The control bits are the same
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Tony,
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git
Paul,
On 02/19/2014 03:22 PM, Paul Walmsley wrote:
[...]
-
Illia Smyrnov (1):
ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
Suman Anna (1):
ARM: DRA7: hwmod data: correct the sysc data for spinlock
Tomi
On Wed, 19 Feb 2014, Nishanth Menon wrote:
Paul,
On 02/19/2014 03:22 PM, Paul Walmsley wrote:
[...]
-
Illia Smyrnov (1):
ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
Suman Anna (1):
ARM: DRA7:
On Wed, 5 Feb 2014, Nishanth Menon wrote:
omap3_noncore_dpll_set_rate forces a reparent to the same clk_ref
for every call that takes place. This is an can be done only if a change
is detected.
Signed-off-by: Nishanth Menon n...@ti.com
Queued for v3.15 with Tero's ack unless the patch is
On Tue, Feb 04, 2014 at 12:36:21PM +0100, Pavel Machek wrote:
+#define BQ24261_MIN_CV 3500
+#define BQ24261_MAX_CV 4440
Other defines use uV as an unit :-(.
uV is used if the value is read from psy class. For register configurations
uses mV. Will change the name to reflect mV
+ /* If
On Tue, Feb 04, 2014 at 12:36:40PM +0100, Pavel Machek wrote:
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -22,6 +22,19 @@ config POWER_SUPPLY_CHARGER
drivers to keep the charging logic outside and the charger driver
just need to abstract the charger hardware.
v1: introduced feature as a framework within power supply class driver with
separate files for battid framework and charging framework
v2: fixed review comments, moved macros and inline functions to power_supply.h
v3: moved the feature as a separate driver, combined battid framework and
Add new power supply properties for input current, charge termination
current, min and max temperature
POWER_SUPPLY_PROP_TEMP_MIN - minimum operatable temperature
POWER_SUPPLY_PROP_TEMP_MAX - maximum operatable temperature
POWER_SUPPLY_PROP_INLMT - input current limit programmed by charger.
As per Product Safety Engineering (PSE) specification for battery charging, the
battery characteristics and thereby the charging rates can vary on different
temperature zones. This patch introduces a PSE compliant charging algorithm with
maintenance charging support. The algorithm can be selected
This patch introduces BQ24261 charger driver. The driver makes use of power
supply charging driver to setup charging. So the driver does hardware
abstraction and handles h/w specific corner cases. The charging logic resides
with power supply charging driver
Signed-off-by: Jenny TC
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