[PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Cc: Tony Lindgren t...@atomide.com Cc: Rob Herring robh...@kernel.org Cc: Pawel Moll pawel.m...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Kumar Gala ga...@codeaurora.org Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d43..b179e80 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,6 +75,8 @@ config SOC_DRA7XX select ARM_GIC select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI + select ARCH_SUPPORTS_MSI config ARCH_OMAP2PLUS bool -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 15/18] ARM: dts: dra7: Add dt data for PCIe controller
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Jingoo Han jg1@samsung.com
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 69 +++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index eaeccaf..1239f0d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1036,6 +1036,75 @@
};
};
+ axi@0 {
+ compatible = simple-bus;
+ #size-cells = 1;
+ #address-cells = 1;
+ ranges = 0x5100 0x5100 0x3000
+ 0x00x2000 0x1000;
+ pcie@5100 {
+ compatible = ti,dra7-pcie;
+ reg = 0x5100 0x2000, 0x51002000 0x14c,
0x1000 0x2000;
+ reg-names = rc_dbics, ti_conf, config;
+ interrupts = 0 232 0x4, 0 233 0x4;
+ #address-cells = 3;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x8100 0 0 0x03000 0
0x0001
+ 0x8200 0 0x20013000 0x13000 0
0xffed000;
+ #interrupt-cells = 1;
+ num-lanes = 1;
+ ti,hwmods = pcie1;
+ phys = pcie1_phy;
+ phy-names = pcie-phy0;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie1_intc 1,
+ 0 0 0 2 pcie1_intc 2,
+ 0 0 0 3 pcie1_intc 3,
+ 0 0 0 4 pcie1_intc 4;
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ };
+ };
+ };
+
+ axi@1 {
+ compatible = simple-bus;
+ #size-cells = 1;
+ #address-cells = 1;
+ ranges = 0x5180 0x5180 0x3000
+ 0x00x3000 0x1000;
+ status = disabled;
+ pcie@5100 {
+ compatible = ti,dra7-pcie;
+ reg = 0x5180 0x2000, 0x51802000 0x14c,
0x1000 0x2000;
+ reg-names = rc_dbics, ti_conf, config;
+ interrupts = 0 355 0x4, 0 356 0x4;
+ #address-cells = 3;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x8100 0 0 0x03000 0
0x0001
+ 0x8200 0 0x30013000 0x13000 0
0xffed000;
+ #interrupt-cells = 1;
+ num-lanes = 1;
+ ti,hwmods = pcie2;
+ phys = pcie2_phy;
+ phy-names = pcie-phy0;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie2_intc 1,
+ 0 0 0 2 pcie2_intc 2,
+ 0 0 0 3 pcie2_intc 3,
+ 0 0 0 4 pcie2_intc 4;
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ };
+ };
+ };
+
sata: sata@4a141100 {
compatible = snps,dwc-ahci;
reg = 0x4a14 0x1100, 0x4a141100 0x7;
--
1.7.9.5
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[TEMP PATCH v2 18/18] ARM: dts: dra7: Add *resets* property for PCIe dt node
Added *resets* and *reset-names* properies for PCIe dt node. The documention for this node can be found @ ../bindings/pci/ti-pci.txt. Cc: Dan Murphy dmur...@ti.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/boot/dts/dra7.dtsi |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1239f0d..03494b2 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1055,6 +1055,8 @@ #interrupt-cells = 1; num-lanes = 1; ti,hwmods = pcie1; + resets = prm_resets device_reset; + reset-names = reset; phys = pcie1_phy; phy-names = pcie-phy0; interrupt-map-mask = 0 0 0 7; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[TEMP PATCH v2 17/18] PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
drivers/pci/host/pci-dra7xx.c| 10 ++
2 files changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index d07d2eb..3649c2e 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -22,6 +22,8 @@ PCIe Designware Controller
num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+ - resets: phandle used if reset is handled be soc
+ - reset-names: name given to the phandle
Example:
axi {
@@ -45,6 +47,8 @@ axi {
ti,hwmods = pcie1;
phys = pcie1_phy;
phy-names = pcie-phy0;
+ resets = prm_resets device_reset;
+ reset-names = reset;
interrupt-map-mask = 0 0 0 7;
interrupt-map = 0 0 0 1 pcie_intc 1,
0 0 0 2 pcie_intc 2,
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 8fb3a2e..17f5e6a 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -22,6 +22,7 @@
#include linux/platform_device.h
#include linux/pm_runtime.h
#include linux/resource.h
+#include linux/reset.h
#include linux/types.h
#include pcie-designware.h
@@ -332,6 +333,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
struct device *dev = pdev-dev;
struct device_node *np = dev-of_node;
char name[10];
+ struct reset_control *rstc;
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -355,6 +357,14 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
if (!base)
return -ENOMEM;
+ rstc = devm_reset_control_get(dev, reset);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ return ret;
+
phy_count = of_property_count_strings(np, phy-names);
if (phy_count 0) {
dev_err(dev, unable to find the strings\n);
--
1.7.9.5
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[PATCH v2 12/18] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e1bd052..3d8c9c2 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,7 +1165,7 @@
reg = 0x021c, 0x0220;
};
- optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ optfclk_pciephy1_32khz: optfclk_pciephy_32khz@4a0093b0 {
compatible = ti,gate-clock;
clocks = sys_32k_ck;
#clock-cells = 0;
@@ -1183,7 +1183,7 @@
ti,max-div = 2;
};
- optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ optfclk_pciephy1_clk: optfclk_pciephy_clk@4a0093b0 {
compatible = ti,gate-clock;
clocks = apll_pcie_ck;
#clock-cells = 0;
@@ -1191,7 +1191,7 @@
ti,bit-shift = 9;
};
- optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = ti,gate-clock;
clocks = optfclk_pciephy_div;
#clock-cells = 0;
--
1.7.9.5
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[PATCH v2 14/18] ARM: dts: dra7: Add dt data for PCIe PHY
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3c7e7f2..eaeccaf 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -912,6 +912,45 @@
clock-names = sysclk;
#phy-cells = 0;
};
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = ti,phy-pipe3-pcie;
+ reg = 0x4A094000 0x80, /* phy_rx */
+ 0x4A094400 0x64; /* phy_tx */
+ reg-names = phy_rx, phy_tx;
+ ctrl-module = omap_control_pcie1phy;
+ clocks = dpll_pcie_ref_ck,
+dpll_pcie_ref_m2ldo_ck,
+optfclk_pciephy1_32khz,
+optfclk_pciephy1_clk,
+optfclk_pciephy1_div_clk,
+optfclk_pciephy_div;
+ clock-names = dpll_ref, dpll_ref_m2,
+ wkupclk, refclk,
+ div-clk, phy-div;
+ #phy-cells = 0;
+ ti,hwmods = pcie1-phy;
+ };
+
+ pcie2_phy: pciephy@4a095000 {
+ compatible = ti,phy-pipe3-pcie;
+ reg = 0x4A095000 0x80, /* phy_rx */
+ 0x4A095400 0x64; /* phy_tx */
+ reg-names = phy_rx, phy_tx;
+ ctrl-module = omap_control_pcie1phy;
+ clocks = dpll_pcie_ref_ck,
+dpll_pcie_ref_m2ldo_ck,
+optfclk_pciephy2_32khz,
+optfclk_pciephy2_clk,
+optfclk_pciephy2_div_clk,
+optfclk_pciephy_div;
+ clock-names = dpll_ref, dpll_ref_m2,
+ wkupclk, refclk,
+ div-clk, phy-div;
+ #phy-cells = 0;
+ ti,hwmods = pcie2-phy;
+ status = disabled;
+ };
};
omap_dwc3_1@4888 {
--
1.7.9.5
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[PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3d8c9c2..a9ff0dc 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
ti,bit-shift = 8;
};
+ optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {
+ compatible = ti,gate-clock;
+ clocks = sys_32k_ck;
+ #clock-cells = 0;
+ reg = 0x13b4;
+ ti,bit-shift = 8;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = ti,divider-clock;
clocks = apll_pcie_ck;
@@ -1191,6 +1199,14 @@
ti,bit-shift = 9;
};
+ optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {
+ compatible = ti,gate-clock;
+ clocks = apll_pcie_ck;
+ #clock-cells = 0;
+ reg = 0x13b4;
+ ti,bit-shift = 9;
+ };
+
optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = ti,gate-clock;
clocks = optfclk_pciephy_div;
@@ -1199,6 +1215,14 @@
ti,bit-shift = 10;
};
+ optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {
+ compatible = ti,gate-clock;
+ clocks = optfclk_pciephy_div;
+ #clock-cells = 0;
+ reg = 0x13b4;
+ ti,bit-shift = 10;
+ };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = 0;
compatible = fixed-factor-clock;
--
1.7.9.5
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[PATCH v2 11/18] ARM: dts: dra7: Add dt data for PCIe PHY control module
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f0ca46d..3c7e7f2 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -803,6 +803,23 @@
status = disabled;
};
+ omap_control_pcie1phy: omap-control-pciephy@0x4a003c40 {
+ compatible = ti,control-phy-pcie;
+ reg = 0x4a003c40 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
+ reg-names = power, control_sma, pcie_pcs;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ };
+
+ omap_control_pcie2phy: omap-control-pciephy@0x4a003c44 {
+ compatible = ti,control-phy-pcie;
+ reg = 0x4a003c44 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
+ reg-names = power, control_sma, pcie_pcs;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ status = disabled;
+ };
+
omap_control_usb2phy1: control-phy@4a002300 {
compatible = ti,control-phy-usb2;
reg = 0x4a002300 0x4;
--
1.7.9.5
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[PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for programming
the outbound translation window the *base* should be programmed as 0x000_.
Whenever we try to write to say 0x2000_, it will be translated to whatever
we have programmed in the translation window with base as 0x000_.
This is needed when the dt node is modelled something like below
axi {
compatible = simple-bus;
#size-cells = 1;
#address-cells = 1;
ranges = 0x00x2000 0x1000 // 28-bit bus
0x5100 0x5100 0x3000;
pcie@5100 {
reg = 0x1000 0x2000, 0x51002000 0x14c, 0x5100 0x2000;
reg-names = config, ti_conf, rc_dbics;
#address-cells = 3;
#size-cells = 2;
ranges = 0x8100 0 0 0x03000 0 0x0001
0x8200 0 0x20013000 0x13000 0 0xffed000;
};
};
Here the CPU address for configuration space is 0x20013000 and the controller
address for configuration space is 0x13000. The controller address should be
used while programming the ATU (in order for translation to happen properly in
DRA7xx).
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pcie-designware.c | 49
drivers/pci/host/pcie-designware.h |4 +++
2 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 603b386..9dfd2d4 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -397,8 +397,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
struct of_pci_range range;
struct of_pci_range_parser parser;
struct resource *cfg_res;
- u32 val;
- int i;
+ u32 val, na, ns;
+ const __be32 *addrp;
+ int i, index;
+
+ /* Find the address cell size and the number of cells in order to get
+* the untranslated address.
+*/
+ of_property_read_u32(np, #address-cells, na);
+ ns = of_n_size_cells(np);
cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, config);
if (cfg_res) {
@@ -406,6 +413,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp-config.cfg1_size = resource_size(cfg_res)/2;
pp-cfg0_base = cfg_res-start;
pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+
+ /* Find the untranslated configuration space address */
+ index = of_property_match_string(np, reg-names, config);
+ addrp = of_get_address(np, index, false, false);
+ pp-cfg0_mod_addr = of_read_number(addrp, ns);
+ pp-cfg1_mod_addr = pp-cfg0_mod_addr + pp-config.cfg0_size;
} else {
dev_err(pp-dev, missing *config* reg space\n);
}
@@ -431,12 +444,20 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp-config.io_size = resource_size(pp-io);
pp-config.io_bus_addr = range.pci_addr;
pp-io_base = range.cpu_addr;
+
+ /* Find the untranslated IO space address */
+ pp-io_mod_addr = of_read_number(parser.range -
+parser.np + na, ns);
}
if (restype == IORESOURCE_MEM) {
of_pci_range_to_resource(range, np, pp-mem);
pp-mem.name = MEM;
pp-config.mem_size = resource_size(pp-mem);
pp-config.mem_bus_addr = range.pci_addr;
+
+ /* Find the untranslated MEM space address */
+ pp-mem_mod_addr = of_read_number(parser.range -
+ parser.np + na, ns);
}
if (restype == 0) {
of_pci_range_to_resource(range, np, pp-cfg);
@@ -444,6 +465,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp-config.cfg1_size = resource_size(pp-cfg)/2;
pp-cfg0_base = pp-cfg.start;
pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
+
+ /* Find the untranslated configuration space address */
+ pp-cfg0_mod_addr =
[PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 44993ec..e1bd052 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = 0x021c, 0x0220;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ compatible = ti,gate-clock;
+ clocks = sys_32k_ck;
+ #clock-cells = 0;
+ reg = 0x13b0;
+ ti,bit-shift = 8;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = ti,divider-clock;
clocks = apll_pcie_ck;
--
1.7.9.5
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[PATCH v2 09/18] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 1282a42..a51fa7f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = pcie,
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = pcie1,
+ .class = dra7xx_pcie_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .main_clk = l4_root_clk_div,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = pcie2,
+ .class = dra7xx_pcie_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .main_clk = l4_root_clk_div,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2388,6 +2425,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg - pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_pcie1_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg - pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_pcie2_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg - pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = dra7xx_l4_cfg_hwmod,
@@ -2751,6 +2804,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
dra7xx_l4_cfg__ocp2scp3,
+ dra7xx_l4_cfg__pcie1,
+ dra7xx_l4_cfg__pcie2,
dra7xx_l4_cfg__pcie1_phy,
dra7xx_l4_cfg__pcie2_phy,
dra7xx_l3_main_1__qspi,
--
1.7.9.5
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[PATCH v2 08/18] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch/arm/mach-omap2/prm7xx.h |4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b9bb476..1282a42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = pcie-phy,
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = pcie1-phy,
+ .class = dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .main_clk = l4_root_clk_div,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = pcie2-phy,
+ .class = dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .main_clk = l4_root_clk_div,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg - pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_pcie1_phy_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg - pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_pcie2_phy_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b30,
@@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
dra7xx_l4_cfg__ocp2scp3,
+ dra7xx_l4_cfg__pcie1_phy,
+ dra7xx_l4_cfg__pcie2_phy,
dra7xx_l3_main_1__qspi,
dra7xx_l4_cfg__sata,
dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
+#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET0x00b4
+#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET
[PATCH v2 05/18] PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 59 +++
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile|1 +
drivers/pci/host/pci-dra7xx.c| 460 ++
4 files changed, 530 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
create mode 100644 drivers/pci/host/pci-dra7xx.c
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
new file mode 100644
index 000..d07d2eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -0,0 +1,59 @@
+TI PCI Controllers
+
+PCIe Designware Controller
+ - compatible: Should be ti,dra7-pcie
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be ti-conf for the TI specific registers
+ The second entry must be rc-dbics for the designware pcie
+ registers
+ The third entry must be config for the PCIe configurationspace
+ - phys : list of PHY specifiers (used by generic PHY framework)
+ - phy-names : must be pcie-phy0, pcie-phy1, pcie-phyN.. based on the
+ number of PHYs as specified in *phys* property.
+ - ti,hwmods : Name of the hwmod associated to the pcie, pcieX,
+ where X is the instance number of the pcie from the HW spec.
+ - interrupts : Two interrupt entries must be specified. The first one is for
+ main interrupt line and the second for MSI interrupt line.
+ - #address-cells,
+ #size-cells,
+ #interrupt-cells,
+ device_type,
+ ranges,
+ num-lanes,
+ interrupt-map-mask,
+ interrupt-map : as specified in ../designware-pcie.txt
+
+Example:
+axi {
+ compatible = simple-bus;
+ #size-cells = 1;
+ #address-cells = 1;
+ ranges = 0x5100 0x5100 0x3000
+ 0x00x2000 0x1000;
+ pcie@5100 {
+ compatible = ti,dra7-pcie;
+ reg = 0x5100 0x2000, 0x51002000 0x14c, 0x1000 0x2000;
+ reg-names = rc_dbics, ti_conf, config;
+ interrupts = 0 232 0x4, 0 233 0x4;
+ #address-cells = 3;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x8100 0 0 0x03000 0 0x0001
+ 0x8200 0 0x20013000 0x13000 0 0xffed000;
+ #interrupt-cells = 1;
+ num-lanes = 1;
+ ti,hwmods = pcie1;
+ phys = pcie1_phy;
+ phy-names = pcie-phy0;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ };
+ };
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..58ccb414 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -1,6 +1,16 @@
menu PCI host controller drivers
depends on PCI
+config PCI_DRA7XX
+ bool TI DRA7xx PCIe controller
+ select PCIE_DW
+ depends on OF HAS_IOMEM TI_PIPE3
+ help
+Enables support for the PCIE controller present in DRA7xx SoC. There
+are two instances of PCIE controller in DRA7xx. This controller can
+act both as EP and RC. This reuses the same Designware core as used
+by other SoCs.
+
config PCI_MVEBU
bool Marvell EBU PCIe controller
depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..5216f55 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
new file mode 100644
index 000..8fb3a2e
--- /dev/null
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -0,0 +1,460 @@
+/*
+ * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
+ *
+ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Authors: Kishon Vijay
[PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 55e95c5..44993ec 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = ti,mux-clock;
- clocks = dpll_pcie_ref_ck, pciesref_acs_clk_ck;
+ clocks = dpll_pcie_ref_m2ldo_ck, pciesref_acs_clk_ck;
#clock-cells = 0;
reg = 0x021c 0x4;
ti,bit-shift = 7;
--
1.7.9.5
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[PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ The configuration address space should also be specified here.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
int __init dw_pcie_host_init(struct pcie_port *pp)
{
struct device_node *np = pp-dev-of_node;
+ struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+ struct resource *cfg_res;
u32 val;
int i;
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, config);
+ if (cfg_res) {
+ pp-config.cfg0_size = resource_size(cfg_res)/2;
+ pp-config.cfg1_size = resource_size(cfg_res)/2;
+ pp-cfg0_base = cfg_res-start;
+ pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+ } else {
+ dev_err(pp-dev, missing *config* reg space\n);
+ }
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+ pp-cfg0_base = pp-cfg.start;
+ pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
}
}
@@ -441,8 +456,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp-cfg0_base = pp-cfg.start;
- pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
pp-mem_base = pp-mem.start;
pp-va_cfg0_base = devm_ioremap(pp-dev, pp-cfg0_base,
--
1.7.9.5
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[PATCH v2 01/18] phy: phy-omap-pipe3: Add support for PCIe PHY
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c | 99 +-
2 files changed, 84 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 9ce458f..cf3de7e 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -56,8 +56,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
- ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3, ti,phy-pipe3-sata or
+ ti,phy-pipe3-pcie. ti,omap-usb3 is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in reg.
@@ -69,6 +69,10 @@ Required properties:
* wkupclk - wakeup clock.
* sysclk - system clock.
* refclk - reference clock.
+ * dpll_ref - external dpll ref clk
+ * dpll_ref_m2 - external dpll ref clk
+ * phy-div - divider for apll
+ * div-clk - apll clock
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 5913676..d43019d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -80,6 +80,7 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
};
@@ -215,6 +216,9 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
+ if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
+ return 0;
+
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
if (val PLL_IDLE) {
@@ -238,8 +242,11 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
- /* SATA DPLL can't be powered down due to Errata i783 */
- if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata))
+ /* SATA DPLL can't be powered down due to Errata i783 and PCIe
+* does not have internal DPLL
+*/
+ if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata) ||
+ of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
return 0;
/* Put DPLL in IDLE mode */
@@ -286,32 +293,41 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *control_node;
struct platform_device *control_pdev;
const struct of_device_id *match;
-
- match = of_match_device(of_match_ptr(ti_pipe3_id_table), pdev-dev);
- if (!match)
- return -EINVAL;
+ struct clk *clk;
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(pdev-dev, unable to alloc mem for TI PIPE3 PHY\n);
return -ENOMEM;
}
+ phy-dev= pdev-dev;
- phy-dpll_map = (struct pipe3_dpll_map *)match-data;
- if (!phy-dpll_map) {
- dev_err(pdev-dev, no DPLL data\n);
- return -EINVAL;
- }
+ if (!of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table),
+ pdev-dev);
+ if (!match)
+ return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pll_ctrl);
- phy-pll_ctrl_base = devm_ioremap_resource(pdev-dev, res);
- if (IS_ERR(phy-pll_ctrl_base))
- return PTR_ERR(phy-pll_ctrl_base);
+ phy-dpll_map = (struct pipe3_dpll_map *)match-data;
+ if (!phy-dpll_map) {
+ dev_err(pdev-dev, no DPLL data\n);
+ return -EINVAL;
+ }
- phy-dev= pdev-dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ pll_ctrl);
+ phy-pll_ctrl_base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(phy-pll_ctrl_base))
+ return PTR_ERR(phy-pll_ctrl_base);
- if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
+ if (IS_ERR(phy-sys_clk)) {
+ dev_err(pdev-dev, unable to get sysclk\n);
+ return -EINVAL;
+
[PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock
From: Keerthy j-keer...@ti.com Add divider table to optfclk_pciephy_div clock. The Documentation for divider clock can be found at ../clock/ti/divider.txt Cc: Rajendra Nayak rna...@ti.com Cc: Tero Kristo t-kri...@ti.com Cc: Paul Walmsley p...@pwsan.com Signed-off-by: Keerthy j-keer...@ti.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/boot/dts/dra7xx-clocks.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c767687..55e95c5 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = apll_pcie_ck; #clock-cells = 0; reg = 0x021c; + ti,dividers = 2, 1; ti,bit-shift = 8; ti,max-div = 2; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 00/18] PCIe support for DRA7xx
This patch series adds support for PCIe in DRA7xx including drivers and dt data. PCIe in DRA7xx uses desingware IP and hence this re-uses the pcie desingware driver (pcie-designware.c) by Jingoo. The last couple of patches are marked as *TEMP* since the TI reset driver [1] is not yet merged and is in RFC. Tested broadcom PCIe card and XIO2000 bridge along with DGE530T ethernet card. Changes from v1: * removed external clock support fro APLL since the clock framework patches are still in RFC. * The configuration address space should be given in *reg* and made the corresponding driver changes in pcie-designware.c * Used untraslated address while programming ATU since that is needed for DRA7. With this PCIe should be made the child node of axi. * Used a new irq domain for PCIe legacy interrupts. * Added clocks and dt data for the second instance of PCIe controller (with status = disabled). Changes from RFC: * Added external clock support for PCIE APLL * Miscellaneous cleanups in Documentation, macro naming etc.. [1] - http://www.spinics.net/lists/linux-omap/msg106411.html Keerthy (2): ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I (16): phy: phy-omap-pipe3: Add support for PCIe PHY phy: pipe3: insert delay to enumerate in GEN2 mode PCI: designware: Configuration space should be specified in 'reg' PCI: designware: use untranslated address while programming ATU PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY ARM: dts: dra7: Add dt data for PCIe PHY control module ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance ARM: dts: dra7: Add dt data for PCIe PHY ARM: dts: dra7: Add dt data for PCIe controller ARM: OMAP: Enable PCI for DRA7 PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe ARM: dts: dra7: Add *resets* property for PCIe dt node .../devicetree/bindings/pci/designware-pcie.txt|1 + Documentation/devicetree/bindings/pci/ti-pci.txt | 63 +++ Documentation/devicetree/bindings/phy/ti-phy.txt | 20 +- arch/arm/boot/dts/dra7.dtsi| 127 ++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 39 +- arch/arm/mach-omap2/Kconfig|2 + arch/arm/mach-omap2/cm2_7xx.h |4 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 + arch/arm/mach-omap2/prm7xx.h |4 + drivers/pci/host/Kconfig | 10 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-dra7xx.c | 470 drivers/pci/host/pcie-designware.c | 66 ++- drivers/pci/host/pcie-designware.h |4 + drivers/phy/phy-omap-control.c | 52 ++- drivers/phy/phy-ti-pipe3.c | 101 - include/linux/phy/omap_control_phy.h | 10 + 17 files changed, 1041 insertions(+), 45 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt create mode 100644 drivers/pci/host/pci-dra7xx.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 02/18] phy: pipe3: insert delay to enumerate in GEN2 mode
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++---
drivers/phy/phy-omap-control.c | 52 +-
drivers/phy/phy-ti-pipe3.c |4 +-
include/linux/phy/omap_control_phy.h | 10 +
4 files changed, 71 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cf3de7e..36bb6c9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,15 +9,17 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
+ ti,control-phy-pcie - for pcie to support external clock for pcie and to
+ set PCS delay value.
+ e.g. PCIE PHY in DRA7x
ti,control-phy-usb2-dra7 - if it has power down register like USB2 PHY on
DRA7 platform.
ti,control-phy-usb2-am437 - if it has power down register like USB2 PHY on
AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of otghs_control for control-phy-otghs or power register
- for other types.
- - reg-names: should be otghs_control control-phy-otghs and power for
- other types.
+ - reg : register ranges as listed in the reg-names property
+ - reg-names: otghs_control for control-phy-otghs
+ power, pcie_pcs and control_sma for control-phy-pcie
+ power for all other types
omap_control_usb: omap-control-usb@4a002300 {
compatible = ti,control-phy-otghs;
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 311b4f9..9487bf1 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -27,6 +27,41 @@
#include linux/phy/omap_control_phy.h
/**
+ * omap_control_pcie_pcs - set the PCS delay count
+ * @dev: the control module device
+ * @id: index of the pcie PHY (should be 1 or 2)
+ * @delay: 8 bit delay value
+ */
+void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
+{
+ u32 val;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err(%s: invalid device\n, __func__);
+ return;
+ }
+
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, %s: invalid control phy device\n, __func__);
+ return;
+ }
+
+ if (control_phy-type != OMAP_CTRL_TYPE_PCIE) {
+ dev_err(dev, %s: unsupported operation\n, __func__);
+ return;
+ }
+
+ val = readl(control_phy-pcie_pcs);
+ val = ~(OMAP_CTRL_PCIE_PCS_MASK
+ (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
+ val |= delay (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
+ writel(val, control_phy-pcie_pcs);
+}
+EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
+
+/**
* omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
@@ -61,6 +96,7 @@ void omap_control_phy_power(struct device *dev, int on)
val |= OMAP_CTRL_DEV_PHY_PD;
break;
+ case OMAP_CTRL_TYPE_PCIE:
case OMAP_CTRL_TYPE_PIPE3:
rate = clk_get_rate(control_phy-sys_clk);
rate = rate/100;
@@ -211,6 +247,7 @@ EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
+static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
static const enum omap_control_phy_type dra7usb2_data =
OMAP_CTRL_TYPE_DRA7USB2;
static const enum omap_control_phy_type am437usb2_data =
OMAP_CTRL_TYPE_AM437USB2;
@@ -228,6 +265,10 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
+ .compatible = ti,control-phy-pcie,
+ .data = pcie_data,
+ },
+ {
.compatible = ti,control-phy-usb2-dra7,
.data = dra7usb2_data,
},
@@ -279,7 +320,8 @@ static int omap_control_phy_probe(struct platform_device
*pdev)
}
}
- if (control_phy-type == OMAP_CTRL_TYPE_PIPE3) {
+ if (control_phy-type ==
Re: [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index cb31d43..b179e80 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -75,6 +75,8 @@ config SOC_DRA7XX
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
+ select MIGHT_HAVE_PCI
+ select ARCH_SUPPORTS_MSI
Hi Kishon,
Please, don't select ARCH_SUPPORTS_MSI, because this kconfig
option was already removed in v3.12 by the commit ebd97be635
('PCI: remove ARCH_SUPPORTS_MSI kconfig option'). So, there is
NO need to select 'ARCH_SUPPORTS_MSI'.
Best regards,
Jingoo Han
config ARCH_OMAP2PLUS
bool
--
1.7.9.5
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RE: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-omap@vger.kernel.org; linux-
p...@vger.kernel.org; linux-ker...@vger.kernel.org
Cc: a...@arndb.de; t...@atomide.com; jg1@samsung.com;
kis...@ti.com; Jason Gunthorpe; Bjorn Helgaas; Mohit KUMAR DCG; Marek
Vasut
Subject: [PATCH v2 03/18] PCI: designware: Configuration space should be
specified in 'reg'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ The configuration address space should also be specified here.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops
msi_domain_ops = { int __init dw_pcie_host_init(struct pcie_port *pp) {
struct device_node *np = pp-dev-of_node;
+ struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+ struct resource *cfg_res;
u32 val;
int i;
+ cfg_res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, config);
+ if (cfg_res) {
+ pp-config.cfg0_size = resource_size(cfg_res)/2;
+ pp-config.cfg1_size = resource_size(cfg_res)/2;
+ pp-cfg0_base = cfg_res-start;
+ pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+ } else {
+ dev_err(pp-dev, missing *config* reg space\n);
+ }
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+ pp-cfg0_base = pp-cfg.start;
+ pp-cfg1_base = pp-cfg.start + pp-
config.cfg0_size;
- As you are getting cfg address space as MEM resource, so remove above code
that
gets the configuration space from dt range. Also correct dt for pcie cfg space
for the platforms
based on this driver.
Otherwise looks fine to me.
Thanks
Mohit
}
}
@@ -441,8 +456,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp-cfg0_base = pp-cfg.start;
- pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
pp-mem_base = pp-mem.start;
pp-va_cfg0_base = devm_ioremap(pp-dev, pp-cfg0_base,
--
1.7.9.5
--
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Re: [PATCH 1/2] ARM: OMAP2+: remove unused omap4-keypad file and code
On Mon, May 19, 2014 at 09:18:15AM -0700, Tony Lindgren wrote: * Dmitry Torokhov dmitry.torok...@gmail.com [140518 22:38]: On Sat, May 17, 2014 at 11:24:10PM +0200, Joachim Eastwood wrote: This has been unused since omap4 board files went away. Signed-off-by: Joachim Eastwood manab...@gmail.com Tony, can I merge both through my tree? Yes I don't have anything touching the omap4_keyboard_init areas that I can think of: Acked-by: Tony Lindgren t...@atomide.com Applied both, thank you. -- Dmitry -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v14 0/6] mmc: omap_hsmmc: Enable SDIO IRQ
Hi Balaji, Tony, Ulf, all
v14
- drop all ifdef/endif introduced by v13
-- rely on pinctrl_lookup_state to prevent ifdef CONFIG_PM
-- benefit: all code is compile tested no matter the configuration
-- drawback: require wake_irq/pinctrl configuration even when
runtime suspend is not configured
- drop runtime state from debugfs output
- rebased onto current mmc-next 06732b84b4cf
v13
- fix compile breaks if !CONFIG_PM
- additional patch: install dummy pm runtime hooks if !CONFIG_PM_RUNTIME
v12
- drop !CONFIG_OF compile break only exists when
#undef CONFIG_OF after include headers 1/7(Sebastian Reichel)
- do not emit falling back to polling if wake_irq not specified
since MMC does not need it, and it might confuse users
only emit if pinmux default/idle is not present or claiming
the irq failed 2/7(Balaji)
- dropped out-of-tree patches 6/7(Balaji)
- mention ti,am33xx-hsmmc compatible section in bindings
documentation 1/5
v11
- split !CONFIG_OF compile break into separate patch
- enable IWE/CLKEXTFREE in CON/HCTL register needed for omap4
- '' vs '' in omap_hsmmc_resume, 1/5 (Andreas Müller)
- #define DLEV_DAT instead of BIT(21) 2/5 (Balaji)
- pinctrl_pm_select_default_state() removed, 4/5 (Balaji)
- drop _irqsave/_irqrestore from omap_hsmmc_wake_irq handler since it
can't be preempted by same priority omap_hsmmc_irq handler 1/5(Joel Fernandes)
- replace devres_open_group by explicit devm_free calls 1/5 (Balaji)
- disable_irq_nosync wake_irq since we handle it thread safe 1/5 (Balaji)
- drop 'gpio_dat1' pinctrl states and rework documentation 5/5 (Balaji)
v10
- bug fix on multi-core, untested
- incorporated changes from Balaji
- use devres / RAII mechanism to configure wake_up /
sdio irq capabilities
- drop pinctrl state 'active'
rely on driver-model states 'default', 'idle'
- add specific 'gpio_dat1' state for am335x SWAKEUP hack
- reorganized patches; +1 patch multi-core bugfix / +1 for pinctrl
- rebased 455c6fdbd21916 / cherry-picks from mmc-next
v9
- extended comment about why wake-irq is needed
- drop double '(' ')' around card_detect_irq
- drop final '.' in in subject line of patch
v8
- rebased on top of Tony Lindgrent...@atomide.com changes
- improved changelog describing the earlier work
- improved wakeup irq setup
- works for am3730 es platform now
- my changes on top:
- compile tested with #undef CONFIG_OF
- disable wake_irq in handler to prevent infinite loop
- fixed typo and added comment about wake-irq
v7
- rebase on 3.14.0-rc3-49726-g77e15ec
- split omap_hsmmc_pin_init due to regression on omap-3730 platform
v6
- rebase on Linux 3.13-rc3
- reformatting debugfs
v5
- fix compile error introduced by last minute one line fix
v4:
- switch to interrupts-extended format
- drop ti,swakeup-missing flag convert to comaptible section
v3:
- removed gpio_irq from platform_data
v2:
- incorparated changes as suggested by reviewers
- simplified workaround for am335x, gpio will now only wake
the module from runtime suspend, not handle the sdio irq
itself
Andreas Fenkart (6):
mmc: omap_hsmmc: Enable SDIO interrupt
mmc: omap_hsmmc: Extend debugfs by SDIO IRQ handling, runtime state
mmc: omap_hsmmc: enable wakeup event for sdio OMAP4
mmc: omap_hsmmc: abort runtime suspend if pending sdio irq detected
mmc: omap_hsmmc: switch default/idle pinctrl states in runtime hooks
mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on
AM335x
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 54
drivers/mmc/host/omap_hsmmc.c | 283 ++--
include/linux/platform_data/mmc-omap.h |1 +
3 files changed, 317 insertions(+), 21 deletions(-)
--
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[PATCH v14 4/6] mmc: omap_hsmmc: abort runtime suspend if pending sdio irq detected
On multicores, an sdio irq handler could be running in parallel to
runtime suspend. In the worst case it could be waiting for the spinlock
held by the runtime suspend. When runtime suspend is complete and the
functional clock (fclk) turned off, the irq handler will continue and
cause a SIGBUS on the first register access.
Acked-by: Balaji T K balaj...@ti.com
Signed-off-by: Andreas Fenkart afenk...@gmail.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index b8be438..2408ec9 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -107,6 +107,9 @@
#define SRD(1 26)
#define SOFTRESET (1 1)
+/* PSTATE */
+#define DLEV_DAT(x)(1 (20 + (x)))
+
/* Interrupt masks for IE and ISE register */
#define CC_EN (1 0)
#define TC_EN (1 1)
@@ -2397,6 +2400,7 @@ static int omap_hsmmc_runtime_suspend(struct device *dev)
{
struct omap_hsmmc_host *host;
unsigned long flags;
+ int ret = 0;
host = platform_get_drvdata(to_platform_device(dev));
omap_hsmmc_context_save(host);
@@ -2408,14 +2412,29 @@ static int omap_hsmmc_runtime_suspend(struct device
*dev)
/* disable sdio irq handling to prevent race */
OMAP_HSMMC_WRITE(host-base, ISE, 0);
OMAP_HSMMC_WRITE(host-base, IE, 0);
- OMAP_HSMMC_WRITE(host-base, STAT, STAT_CLEAR);
+
+ if (!(OMAP_HSMMC_READ(host-base, PSTATE) DLEV_DAT(1))) {
+ /*
+* dat1 line low, pending sdio irq
+* race condition: possible irq handler running on
+* multi-core, abort
+*/
+ dev_dbg(dev, pending sdio irq, abort suspend\n);
+ OMAP_HSMMC_WRITE(host-base, STAT, STAT_CLEAR);
+ OMAP_HSMMC_WRITE(host-base, ISE, CIRQ_EN);
+ OMAP_HSMMC_WRITE(host-base, IE, CIRQ_EN);
+ pm_runtime_mark_last_busy(dev);
+ ret = -EBUSY;
+ goto abort;
+ }
WARN_ON(host-flags HSMMC_WAKE_IRQ_ENABLED);
enable_irq(host-wake_irq);
host-flags |= HSMMC_WAKE_IRQ_ENABLED;
}
+abort:
spin_unlock_irqrestore(host-irq_lock, flags);
- return 0;
+ return ret;
}
static int omap_hsmmc_runtime_resume(struct device *dev)
--
1.7.10.4
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[PATCH v14 5/6] mmc: omap_hsmmc: switch default/idle pinctrl states in runtime hooks
These are predefined states of the driver model. When not present,
as if not set in the device tree, they become no-ops.
Explicitly selecting the default state is not needed since the
device core layer sets pin mux to default state before probe.
This is not the simplest implementation, on AM335x at least, we could
switch to idle at any point in the suspend hook, only the default state
needs to be set before writing to the irq registers or an IRQ might get
lost.
Acked-by: Balaji T K balaj...@ti.com
Signed-off-by: Andreas Fenkart afenk...@gmail.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 2408ec9..0febb17 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1998,7 +1998,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
const struct of_device_id *match;
dma_cap_mask_t mask;
unsigned tx_req, rx_req;
- struct pinctrl *pinctrl;
const struct omap_mmc_of_data *data;
void __iomem *base;
@@ -,11 +2221,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
omap_hsmmc_disable_irq(host);
- pinctrl = devm_pinctrl_get_select_default(pdev-dev);
- if (IS_ERR(pinctrl))
- dev_warn(pdev-dev,
- pins are not configured from the driver\n);
-
/*
* For now, only support SDIO interrupt if we have a separate
* wake-up interrupt configured from device tree. This is because
@@ -2428,10 +2422,15 @@ static int omap_hsmmc_runtime_suspend(struct device
*dev)
goto abort;
}
+ pinctrl_pm_select_idle_state(dev);
+
WARN_ON(host-flags HSMMC_WAKE_IRQ_ENABLED);
enable_irq(host-wake_irq);
host-flags |= HSMMC_WAKE_IRQ_ENABLED;
+ } else {
+ pinctrl_pm_select_idle_state(dev);
}
+
abort:
spin_unlock_irqrestore(host-irq_lock, flags);
return ret;
@@ -2455,9 +2454,14 @@ static int omap_hsmmc_runtime_resume(struct device *dev)
host-flags = ~HSMMC_WAKE_IRQ_ENABLED;
}
+ pinctrl_pm_select_default_state(host-dev);
+
+ /* irq lost, if pinmux incorrect */
OMAP_HSMMC_WRITE(host-base, STAT, STAT_CLEAR);
OMAP_HSMMC_WRITE(host-base, ISE, CIRQ_EN);
OMAP_HSMMC_WRITE(host-base, IE, CIRQ_EN);
+ } else {
+ pinctrl_pm_select_default_state(host-dev);
}
spin_unlock_irqrestore(host-irq_lock, flags);
return 0;
--
1.7.10.4
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[PATCH v14 1/6] mmc: omap_hsmmc: Enable SDIO interrupt
There have been various patches floating around for enabling
the SDIO IRQ for hsmmc, but none of them ever got merged.
Probably the reason for not merging the SDIO interrupt patches
has been the lack of wake-up path for SDIO on some omaps that
has also needed remuxing the SDIO DAT1 line to a GPIO making
the patches complex.
This patch adds the minimal SDIO IRQ support to hsmmc for
omaps that do have the wake-up path. For those omaps, the
DAT1 line need to have the wake-up enable bit set, and the
wake-up interrupt is the same as for the MMC controller.
This patch has been tested on am3730 es1.2 with mwifiex
connected to MMC3 with mwifiex waking to Ethernet traffic
from off-idle mode. Note that for omaps that do not have
the SDIO wake-up path, this patch will not work for idle
modes and further patches for remuxing DAT1 to GPIO are
needed.
Based on earlier patches [1][2] by David Vrabel
david.vra...@csr.com, Steve Sakoman st...@sakoman.com
For now, only support SDIO interrupt if we are booted with
a separate wake-irq configued via device tree. This is
because omaps need the wake-irq for idle states, and some
omaps need special quirks. And we don't want to add new
legacy mux platform init code callbacks any longer as we
are moving to DT based booting anyways.
To use it, you need to specify the wake-irq using the
interrupts-extended property.
[1]
http://www.sakoman.com/cgi-bin/gitweb.cgi?p=linux.git;a=commitdiff_plain;h=010810d22f6f49ac03da4ba384969432e0320453
[2] http://comments.gmane.org/gmane.linux.kernel.mmc/20446
Acked-by: Balaji T K balaj...@ti.com
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index ce80561..0233ba7 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -12,6 +12,7 @@ Required properties:
Should be ti,omap3-hsmmc, for OMAP3 controllers
Should be ti,omap3-pre-es3-hsmmc for OMAP3 controllers pre ES3.0
Should be ti,omap4-hsmmc, for OMAP4 controllers
+ Should be ti,am33xx-hsmmc, for AM335x controllers
- ti,hwmods: Must be mmcn, n is controller instance starting 1
Optional properties:
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6b6fe1e..129569d 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -29,6 +29,7 @@
#include linux/timer.h
#include linux/clk.h
#include linux/of.h
+#include linux/of_irq.h
#include linux/of_gpio.h
#include linux/of_device.h
#include linux/omap-dmaengine.h
@@ -36,6 +37,7 @@
#include linux/mmc/core.h
#include linux/mmc/mmc.h
#include linux/io.h
+#include linux/irq.h
#include linux/gpio.h
#include linux/regulator/consumer.h
#include linux/pinctrl/consumer.h
@@ -106,6 +108,7 @@
#define TC_EN (1 1)
#define BWR_EN (1 4)
#define BRR_EN (1 5)
+#define CIRQ_EN(1 8)
#define ERR_EN (1 15)
#define CTO_EN (1 16)
#define CCRC_EN(1 17)
@@ -140,7 +143,6 @@
#define VDD_3V0300 /* 30 uV */
#define VDD_165_195(ffs(MMC_VDD_165_195) - 1)
-#define AUTO_CMD23 (1 1)/* Auto CMD23 support */
/*
* One controller can have multiple slots, like on some omap boards using
* omap.c controller driver. Luckily this is not currently done on any known
@@ -194,6 +196,7 @@ struct omap_hsmmc_host {
u32 sysctl;
u32 capa;
int irq;
+ int wake_irq;
int use_dma, dma_ch;
struct dma_chan *tx_chan;
struct dma_chan *rx_chan;
@@ -206,6 +209,9 @@ struct omap_hsmmc_host {
int req_in_progress;
unsigned long clk_rate;
unsigned intflags;
+#define AUTO_CMD23 (1 0)/* Auto CMD23 support */
+#define HSMMC_SDIO_IRQ_ENABLED (1 1)/* SDIO irq enabled */
+#define HSMMC_WAKE_IRQ_ENABLED (1 2)
struct omap_hsmmc_next next_data;
struct omap_mmc_platform_data *pdata;
};
@@ -510,27 +516,40 @@ static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host)
static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
struct mmc_command *cmd)
{
- unsigned int irq_mask;
+ u32 irq_mask = INT_EN_MASK;
+ unsigned long flags;
if (host-use_dma)
- irq_mask = INT_EN_MASK ~(BRR_EN | BWR_EN);
- else
- irq_mask = INT_EN_MASK;
+ irq_mask = ~(BRR_EN | BWR_EN);
/* Disable timeout for erases */
if (cmd-opcode == MMC_ERASE)
irq_mask = ~DTO_EN;
+
[PATCH v14 3/6] mmc: omap_hsmmc: enable wakeup event for sdio OMAP4
From: Balaji T K balaj...@ti.com
To detect sdio irqs properly without spurious events,
OMAP4 needs IWE in CON and CTPL, CLKEXTFREE in HCTL to be set
Tested-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Balaji T K balaj...@ti.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 332d3d2..b8be438 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -94,7 +94,10 @@
#define BCE(1 1)
#define FOUR_BIT (1 1)
#define HSPE (1 2)
+#define IWE(1 24)
#define DDR(1 19)
+#define CLKEXTFREE (1 16)
+#define CTPL (1 11)
#define DW8(1 5)
#define OD 0x1
#define STAT_CLEAR 0x
@@ -687,6 +690,9 @@ static int omap_hsmmc_context_restore(struct
omap_hsmmc_host *host)
capa = VS18;
}
+ if (host-mmc-caps MMC_CAP_SDIO_IRQ)
+ hctl |= IWE;
+
OMAP_HSMMC_WRITE(host-base, HCTL,
OMAP_HSMMC_READ(host-base, HCTL) | hctl);
@@ -1684,19 +1690,23 @@ static void omap_hsmmc_init_card(struct mmc_host *mmc,
struct mmc_card *card)
static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct omap_hsmmc_host *host = mmc_priv(mmc);
- u32 irq_mask;
+ u32 irq_mask, con;
unsigned long flags;
spin_lock_irqsave(host-irq_lock, flags);
+ con = OMAP_HSMMC_READ(host-base, CON);
irq_mask = OMAP_HSMMC_READ(host-base, ISE);
if (enable) {
host-flags |= HSMMC_SDIO_IRQ_ENABLED;
irq_mask |= CIRQ_EN;
+ con |= CTPL | CLKEXTFREE;
} else {
host-flags = ~HSMMC_SDIO_IRQ_ENABLED;
irq_mask = ~CIRQ_EN;
+ con = ~(CTPL | CLKEXTFREE);
}
+ OMAP_HSMMC_WRITE(host-base, CON, con);
OMAP_HSMMC_WRITE(host-base, IE, irq_mask);
/*
@@ -1746,6 +1756,8 @@ static int omap_hsmmc_configure_wake_irq(struct
omap_hsmmc_host *host)
goto err;
}
+ OMAP_HSMMC_WRITE(host-base, HCTL,
+OMAP_HSMMC_READ(host-base, HCTL) | IWE);
return 0;
err:
--
1.7.10.4
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[PATCH v14 2/6] mmc: omap_hsmmc: Extend debugfs by SDIO IRQ handling, runtime state
Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current
state of data lines, incl. SDIO IRQ pending
Signed-off-by: Andreas Fenkart afenk...@gmail.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 129569d..332d3d2 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -56,6 +56,7 @@
#define OMAP_HSMMC_RSP54 0x0118
#define OMAP_HSMMC_RSP76 0x011C
#define OMAP_HSMMC_DATA0x0120
+#define OMAP_HSMMC_PSTATE 0x0124
#define OMAP_HSMMC_HCTL0x0128
#define OMAP_HSMMC_SYSCTL 0x012C
#define OMAP_HSMMC_STAT0x0130
@@ -1815,13 +1816,23 @@ static int omap_hsmmc_regs_show(struct seq_file *s,
void *data)
struct mmc_host *mmc = s-private;
struct omap_hsmmc_host *host = mmc_priv(mmc);
- seq_printf(s, mmc%d:\n ctx_loss:\t%d\n\nregs:\n,
- mmc-index, host-context_loss);
+ seq_printf(s, mmc%d:\n, mmc-index);
+ seq_printf(s, sdio irq mode\t%s\n,
+ (mmc-caps MMC_CAP_SDIO_IRQ) ? interrupt : polling);
- pm_runtime_get_sync(host-dev);
+ if (mmc-caps MMC_CAP_SDIO_IRQ) {
+ seq_printf(s, sdio irq \t%s\n,
+ (host-flags HSMMC_SDIO_IRQ_ENABLED) ? enabled
+ : disabled);
+ }
+ seq_printf(s, ctx_loss:\t%d\n, host-context_loss);
+ pm_runtime_get_sync(host-dev);
+ seq_puts(s, \nregs:\n);
seq_printf(s, CON:\t\t0x%08x\n,
OMAP_HSMMC_READ(host-base, CON));
+ seq_printf(s, PSTATE:\t\t0x%08x\n,
+ OMAP_HSMMC_READ(host-base, PSTATE));
seq_printf(s, HCTL:\t\t0x%08x\n,
OMAP_HSMMC_READ(host-base, HCTL));
seq_printf(s, SYSCTL:\t\t0x%08x\n,
--
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[PATCH v14 6/6] mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x
The am335x can't detect pending cirq in PM runtime suspend.
This patch reconfigures dat1 as a GPIO before going to suspend.
SDIO interrupts are detected with the GPIO, the GPIO will only wake
the module from suspend, SDIO irq detection will still happen through the
IP block.
Idea of remuxing the pins by Tony Lindgren. Code contributions from
Tony Lindgren and Balaji T K balaj...@ti.com
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index 0233ba7..76bf087 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -57,3 +57,56 @@ Examples:
edma 25;
dma-names = tx, rx;
};
+
+[workaround for missing swakeup on am33xx]
+
+This SOC is missing the swakeup line, it will not detect SDIO irq
+while in suspend.
+
+ --
+ | PRCM |
+ --
+ ^ |
+ swakeup | | fclk
+ | v
+ ----- -
+ | card | -- CIRQ -- | hsmmc | -- IRQ -- | CPU |
+ ----- -
+
+In suspend the fclk is off and the module is disfunctional. Even register reads
+will fail. A small logic in the host will request fclk restore, when an
+external event is detected. Once the clock is restored, the host detects the
+event normally. Since am33xx doesn't have this line it never wakes from
+suspend.
+
+The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make
+this work, we need to set the named pinctrl states default and idle.
+Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio
+dat1. The MMC driver will then toggle between idle and default state during
+runtime.
+
+In summary:
+1. select matching 'compatible' section, see example below.
+2. specify pinctrl states default and idle, sleep is optional.
+3. specify the gpio irq used for detecting sdio irq in suspend
+
+If configuration is incomplete, a warning message is emitted falling back to
+polling. Also check the sdio irq mode in /sys/kernel/debug/mmc0/regs. Mind
+not every application needs SDIO irq, e.g. MMC cards.
+
+ mmc1: mmc@48060100 {
+ compatible = ti,am33xx-hsmmc;
+ ...
+ pinctrl-names = default, idle, sleep
+ pinctrl-0 = mmc1_pins;
+ pinctrl-1 = mmc1_idle;
+ pinctrl-2 = mmc1_sleep;
+ ...
+ interrupts-extended = intc 64 gpio2 28 0;
+ };
+
+ mmc1_idle : pinmux_cirq_pin {
+ pinctrl-single,pins =
+ 0x0f8 0x3f /* GPIO2_28 */
+ ;
+ };
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0febb17..35ac2e4 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1754,15 +1754,33 @@ static int omap_hsmmc_configure_wake_irq(struct
omap_hsmmc_host *host)
* and need to remux SDIO DAT1 to GPIO for wake-up from idle.
*/
if (host-pdata-controller_flags OMAP_HSMMC_SWAKEUP_MISSING) {
- ret = -ENODEV;
- devm_free_irq(host-dev, host-wake_irq, host);
- goto err;
+ struct pinctrl *p = devm_pinctrl_get(host-dev);
+ if (!p) {
+ ret = -ENODEV;
+ goto err_free_irq;
+ }
+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
+ dev_info(host-dev, missing default pinctrl state\n);
+ devm_pinctrl_put(p);
+ ret = -EINVAL;
+ goto err_free_irq;
+ }
+
+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
+ dev_info(host-dev, missing idle pinctrl state\n);
+ devm_pinctrl_put(p);
+ ret = -EINVAL;
+ goto err_free_irq;
+ }
+ devm_pinctrl_put(p);
}
OMAP_HSMMC_WRITE(host-base, HCTL,
OMAP_HSMMC_READ(host-base, HCTL) | IWE);
return 0;
+err_free_irq:
+ devm_free_irq(host-dev, host-wake_irq, host);
err:
dev_warn(host-dev, no SDIO IRQ support, falling back to polling\n);
host-wake_irq = 0;
--
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On 5/29/2014 12:23 AM, Greg KH wrote: On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote: SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h These are .h files, but where is the api functions that use these structures defined at? This is like template/wrappers, smart card phy driver will write API functions. And smartcard controller will call these functions. With proposed approach, smartcard controller can communicate with any smart card phy (TI/NxP) without change in code. Using DT entry smartcard and PHY will gets connected with each other. Refer diagram given @Documentation/sc_phy.txt. confused, greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/5] misc: tda8026: Add NXP TDA8026 PHY driver
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:14PM +0530, Satish Patel wrote:
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave device.
The driver also exposes the phy interface
(defined@include/linux/sc_phy.h) for SmartCard controller.
Controller uses this interface to communicate with smart card
inserted to the phy's slot.
Note: gpio irq is not validated as I do not have device with that.
I have validated interrupt with dedicated interrupt line on my device.
Signed-off-by: Satish Patel satish.pa...@ti.com
---
Documentation/devicetree/bindings/misc/tda8026.txt | 19 +
drivers/misc/Kconfig |7 +
drivers/misc/Makefile |1 +
drivers/misc/tda8026.c | 1258
4 files changed, 1285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt
create mode 100644 drivers/misc/tda8026.c
diff --git a/Documentation/devicetree/bindings/misc/tda8026.txt
b/Documentation/devicetree/bindings/misc/tda8026.txt
new file mode 100644
index 000..f115c9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/tda8026.txt
@@ -0,0 +1,19 @@
+TDA8026 smart card slot interface
+
+This is an i2c based smart card interface device forming the electrical
+interface between a microcontroller and smart cards. This device supports
+asynchronous cards (micro controller-based IC cards) as well as synchronous
+cards (mainly memory cards)
+
+Required properties:
+- compatible: nxp,tda8026
+- shutdown-gpio = GPIO pin mapping for SDWNN pin
+- reg = i2c interface address
+
+
+Example:
+tda8026: tda8026@48 {
+compatible = nxp,tda8026;
+reg = 0x48;
+shutdown-gpio = gpio5 19 GPIO_ACTIVE_HIGH;/* Bank5, pin19 */
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8baff0e..80b21d7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -515,6 +515,13 @@ config SRAM
the genalloc API. It is supposed to be used for small on-chip SRAM
areas found on many SoCs.
+config NXP_TDA8026_PHY
+tristate NXP PHY Driver for Smart Card PHY
+depends on I2C=y
+help
+ If you say yes here you get support for the TDA8026 Smart card PHY
+ with I2C interface.
+
source drivers/misc/c2port/Kconfig
source drivers/misc/eeprom/Kconfig
source drivers/misc/cb710/Kconfig
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 7eb4b69..f262c0b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SRAM)+= sram.o
obj-y += mic/
obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO)+= echo/
+obj-$(CONFIG_NXP_TDA8026_PHY) += tda8026.o
diff --git a/drivers/misc/tda8026.c b/drivers/misc/tda8026.c
new file mode 100644
index 000..38df33e
--- /dev/null
+++ b/drivers/misc/tda8026.c
@@ -0,0 +1,1258 @@
+/*
+ * tda8026.c - TDA8026 PHY driver for NXP Smart card PHY
+ *
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/moduleparam.h
+#include linux/interrupt.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/mfd/core.h
+#include linux/notifier.h
+#include linux/sc_phy.h
+#include linux/of_gpio.h
+#include linux/of_device.h
+#include linux/delay.h
I think you just broke the build if this driver is enabled now right?
Not good :(
Before sending, I have applied these patches to v3.15-rc7 and build
with both the option ti-usim tda8026 as module, as well as part of
kernel. Any specific tree you would like me to rebase these patches against.
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private data structure
+ * @set_config: called to set phy's configuration
+ * @get_config: called to get phy's configuration
+ * @activate_card: perform smart card activation
+ * @deactivate_card: perform smart card de-activation
+ * @warm_reset: execute smart card warm reset sequence
+ * @register_card_activity_cb: register call back to phy device.
+ * This call back will be called on card insert or remove event
+ *
+ * smart card controller uses this interface to communicate with
+ * smart card via phy.Some smart card phy has multiple slots for
+ * cards. This inerface also enables controller to communicate with
+ * one or more smart card connected over phy.
+ */
+struct sc_phy {
+ /* phy's device pointer */
+ struct device *dev;
So this is the parent, right? Why not embed a struct device into this
structure as well, further streaching out the device tree.
Do you mean to use dev-p for pdata ?
I have kept it outside, to give easeness/pragmatic focal for new phy
driver development. Driver can make this pointer null and use above pointer.
+
+ /* phy's private data */
+ void *pdata;
If you do the above, then this pointer is not needed.
+
+ /* notify data, passed by interface user as a part of
+* register_notify API. Data should be passed back when
+* notification raised to the interface user
+*/
+ void *notify_data;
What makes this different from the pdata?
pdata is phy's private data, while notify_data is something phy will
send to smart card controller on some event, like card
remove/insert/timeout etc..
+
+ int (*set_config)(struct sc_phy *phy, u8 slot,
+ enum sc_phy_config attr, int value);
+ int (*get_config)(struct sc_phy *phy, u8 slot, enum
+ sc_phy_config attr);
+ int (*activate_card)(struct sc_phy *phy, u8 slot);
+ int (*deactivate_card)(struct sc_phy *phy, u8 slot);
+ int (*get_syncatr)(struct sc_phy *phy, u8 slot, u8 len, char *atr);
+ int (*warm_reset)(struct sc_phy *phy, u8 slot);
+ int (*register_notify)(struct sc_phy *phy,
+struct notifier_block *nb, void *notify_data);
+ int (*unregister_notify)(struct sc_phy *phy,
+ struct notifier_block *nb);
+};
+
+#endif /* __SC_PHY_H__ */
--
1.7.9.5
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hi,
On Thursday 29 May 2014 12:41 PM, Mohit KUMAR DCG wrote:
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-omap@vger.kernel.org; linux-
p...@vger.kernel.org; linux-ker...@vger.kernel.org
Cc: a...@arndb.de; t...@atomide.com; jg1@samsung.com;
kis...@ti.com; Jason Gunthorpe; Bjorn Helgaas; Mohit KUMAR DCG; Marek
Vasut
Subject: [PATCH v2 03/18] PCI: designware: Configuration space should be
specified in 'reg'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+The configuration address space should also be specified here.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops
msi_domain_ops = { int __init dw_pcie_host_init(struct pcie_port *pp) {
struct device_node *np = pp-dev-of_node;
+struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+struct resource *cfg_res;
u32 val;
int i;
+cfg_res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, config);
+if (cfg_res) {
+pp-config.cfg0_size = resource_size(cfg_res)/2;
+pp-config.cfg1_size = resource_size(cfg_res)/2;
+pp-cfg0_base = cfg_res-start;
+pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+} else {
+dev_err(pp-dev, missing *config* reg space\n);
+}
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+pp-cfg0_base = pp-cfg.start;
+pp-cfg1_base = pp-cfg.start + pp-
config.cfg0_size;
- As you are getting cfg address space as MEM resource, so remove above code
that
gets the configuration space from dt range. Also correct dt for pcie cfg
space for the platforms
based on this driver.
Ok. Will send that as a separate patch converting all platforms to use MEM
resource.
Thanks
Kishon
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Re: [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
Hi,
On Thursday 29 May 2014 12:18 PM, Jingoo Han wrote:
On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index cb31d43..b179e80 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -75,6 +75,8 @@ config SOC_DRA7XX
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
+select MIGHT_HAVE_PCI
+select ARCH_SUPPORTS_MSI
Hi Kishon,
Please, don't select ARCH_SUPPORTS_MSI, because this kconfig
option was already removed in v3.12 by the commit ebd97be635
('PCI: remove ARCH_SUPPORTS_MSI kconfig option'). So, there is
NO need to select 'ARCH_SUPPORTS_MSI'.
Thanks for spotting it. Will remove it.
Thanks
Kishon
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Re: [PATCH v14 2/6] mmc: omap_hsmmc: Extend debugfs by SDIO IRQ handling, runtime state
On Thursday 29 May 2014 01:58 PM, Andreas Fenkart wrote:
Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current
state of data lines, incl. SDIO IRQ pending
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Thanks Andreas for fixing compilation with !CONFIG_PM[_RUNTIME],
Acked-by: Balaji T K balaj...@ti.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 129569d..332d3d2 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -56,6 +56,7 @@
#define OMAP_HSMMC_RSP54 0x0118
#define OMAP_HSMMC_RSP76 0x011C
#define OMAP_HSMMC_DATA 0x0120
+#define OMAP_HSMMC_PSTATE 0x0124
#define OMAP_HSMMC_HCTL 0x0128
#define OMAP_HSMMC_SYSCTL 0x012C
#define OMAP_HSMMC_STAT 0x0130
@@ -1815,13 +1816,23 @@ static int omap_hsmmc_regs_show(struct seq_file *s,
void *data)
struct mmc_host *mmc = s-private;
struct omap_hsmmc_host *host = mmc_priv(mmc);
- seq_printf(s, mmc%d:\n ctx_loss:\t%d\n\nregs:\n,
- mmc-index, host-context_loss);
+ seq_printf(s, mmc%d:\n, mmc-index);
+ seq_printf(s, sdio irq mode\t%s\n,
+ (mmc-caps MMC_CAP_SDIO_IRQ) ? interrupt : polling);
- pm_runtime_get_sync(host-dev);
+ if (mmc-caps MMC_CAP_SDIO_IRQ) {
+ seq_printf(s, sdio irq \t%s\n,
+ (host-flags HSMMC_SDIO_IRQ_ENABLED) ? enabled
+ : disabled);
+ }
+ seq_printf(s, ctx_loss:\t%d\n, host-context_loss);
+ pm_runtime_get_sync(host-dev);
+ seq_puts(s, \nregs:\n);
seq_printf(s, CON:\t\t0x%08x\n,
OMAP_HSMMC_READ(host-base, CON));
+ seq_printf(s, PSTATE:\t\t0x%08x\n,
+ OMAP_HSMMC_READ(host-base, PSTATE));
seq_printf(s, HCTL:\t\t0x%08x\n,
OMAP_HSMMC_READ(host-base, HCTL));
seq_printf(s, SYSCTL:\t\t0x%08x\n,
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Re: [PATCH v14 6/6] mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x
On Thursday 29 May 2014 01:58 PM, Andreas Fenkart wrote:
The am335x can't detect pending cirq in PM runtime suspend.
This patch reconfigures dat1 as a GPIO before going to suspend.
SDIO interrupts are detected with the GPIO, the GPIO will only wake
the module from suspend, SDIO irq detection will still happen through the
IP block.
Idea of remuxing the pins by Tony Lindgren. Code contributions from
Tony Lindgren and Balaji T K balaj...@ti.com
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
Acked-by: Balaji T K balaj...@ti.com
Hi Chris/Ulf,
Can you please queue this series for 3.16
Thanks and Regards,
Balaji T K
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index 0233ba7..76bf087 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -57,3 +57,56 @@ Examples:
edma 25;
dma-names = tx, rx;
};
+
+[workaround for missing swakeup on am33xx]
+
+This SOC is missing the swakeup line, it will not detect SDIO irq
+while in suspend.
+
+ --
+ | PRCM |
+ --
+ ^ |
+ swakeup | | fclk
+ | v
+ ----- -
+ | card | -- CIRQ -- | hsmmc | -- IRQ -- | CPU |
+ ----- -
+
+In suspend the fclk is off and the module is disfunctional. Even register reads
+will fail. A small logic in the host will request fclk restore, when an
+external event is detected. Once the clock is restored, the host detects the
+event normally. Since am33xx doesn't have this line it never wakes from
+suspend.
+
+The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make
+this work, we need to set the named pinctrl states default and idle.
+Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio
+dat1. The MMC driver will then toggle between idle and default state during
+runtime.
+
+In summary:
+1. select matching 'compatible' section, see example below.
+2. specify pinctrl states default and idle, sleep is optional.
+3. specify the gpio irq used for detecting sdio irq in suspend
+
+If configuration is incomplete, a warning message is emitted falling back to
+polling. Also check the sdio irq mode in /sys/kernel/debug/mmc0/regs. Mind
+not every application needs SDIO irq, e.g. MMC cards.
+
+ mmc1: mmc@48060100 {
+ compatible = ti,am33xx-hsmmc;
+ ...
+ pinctrl-names = default, idle, sleep
+ pinctrl-0 = mmc1_pins;
+ pinctrl-1 = mmc1_idle;
+ pinctrl-2 = mmc1_sleep;
+ ...
+ interrupts-extended = intc 64 gpio2 28 0;
+ };
+
+ mmc1_idle : pinmux_cirq_pin {
+ pinctrl-single,pins =
+ 0x0f8 0x3f /* GPIO2_28 */
+ ;
+ };
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0febb17..35ac2e4 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1754,15 +1754,33 @@ static int omap_hsmmc_configure_wake_irq(struct
omap_hsmmc_host *host)
* and need to remux SDIO DAT1 to GPIO for wake-up from idle.
*/
if (host-pdata-controller_flags OMAP_HSMMC_SWAKEUP_MISSING) {
- ret = -ENODEV;
- devm_free_irq(host-dev, host-wake_irq, host);
- goto err;
+ struct pinctrl *p = devm_pinctrl_get(host-dev);
+ if (!p) {
+ ret = -ENODEV;
+ goto err_free_irq;
+ }
+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
+ dev_info(host-dev, missing default pinctrl state\n);
+ devm_pinctrl_put(p);
+ ret = -EINVAL;
+ goto err_free_irq;
+ }
+
+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
+ dev_info(host-dev, missing idle pinctrl state\n);
+ devm_pinctrl_put(p);
+ ret = -EINVAL;
+ goto err_free_irq;
+ }
+ devm_pinctrl_put(p);
}
OMAP_HSMMC_WRITE(host-base, HCTL,
OMAP_HSMMC_READ(host-base, HCTL) | IWE);
return 0;
+err_free_irq:
+ devm_free_irq(host-dev, host-wake_irq, host);
err:
dev_warn(host-dev, no SDIO IRQ support, falling back to polling\n);
host-wake_irq = 0;
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More
Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote: On 5/29/2014 12:23 AM, Greg KH wrote: On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote: SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h These are .h files, but where is the api functions that use these structures defined at? This is like template/wrappers, smart card phy driver will write API functions. And smartcard controller will call these functions. With proposed approach, smartcard controller can communicate with any smart card phy (TI/NxP) without change in code. Using DT entry smartcard and PHY will gets connected with each other. Refer diagram given @Documentation/sc_phy.txt. confused, I believe the api Greg is wondering about is the notifier which as I commented is not a good design. There is now a phy subsystem. I don't know if it has what you need, but you should look at it to determine if it will work or could be extended to work. Rob -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Cc: Jason Gunthorpe jguntho...@obsidianresearch.com Cc: Bjorn Helgaas bhelg...@google.com Cc: Mohit Kumar mohit.ku...@st.com Cc: Jingoo Han jg1@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/pci/designware-pcie.txt|1 + drivers/pci/host/pcie-designware.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote: On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Cc: Jason Gunthorpe jguntho...@obsidianresearch.com Cc: Bjorn Helgaas bhelg...@google.com Cc: Mohit Kumar mohit.ku...@st.com Cc: Jingoo Han jg1@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/pci/designware-pcie.txt|1 + drivers/pci/host/pcie-designware.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? Because what you end up using is a struct resource to represent the cfg space and the conversion between ranges and resources breaks down for CFG space (we don't have a flag in the resource flags to say this is CFG resource). Specifying it as a *reg* property makes it a MEM resource and no special casing is needed. Best regards, Liviu - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-pci in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- --- .oooO ( ) \ ( Oooo. \_) ( ) ) / (_/ One small step for me ... -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On Thu, May 29, 2014 at 02:26:55PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private data structure
+ * @set_config: called to set phy's configuration
+ * @get_config: called to get phy's configuration
+ * @activate_card: perform smart card activation
+ * @deactivate_card: perform smart card de-activation
+ * @warm_reset: execute smart card warm reset sequence
+ * @register_card_activity_cb: register call back to phy device.
+ * This call back will be called on card insert or remove event
+ *
+ * smart card controller uses this interface to communicate with
+ * smart card via phy.Some smart card phy has multiple slots for
+ * cards. This inerface also enables controller to communicate with
+ * one or more smart card connected over phy.
+ */
+struct sc_phy {
+ /* phy's device pointer */
+ struct device *dev;
So this is the parent, right? Why not embed a struct device into this
structure as well, further streaching out the device tree.
Do you mean to use dev-p for pdata ?
No, use the device itself.
I have kept it outside, to give easeness/pragmatic focal for new phy driver
development. Driver can make this pointer null and use above pointer.
Ick, no, that's not how the driver model works. Each device in the
system needs a struct device, don't try to chain off of an existing
device like this. Make it a real one.
+
+ /* phy's private data */
+ void *pdata;
If you do the above, then this pointer is not needed.
+
+ /* notify data, passed by interface user as a part of
+* register_notify API. Data should be passed back when
+* notification raised to the interface user
+*/
+ void *notify_data;
What makes this different from the pdata?
pdata is phy's private data, while notify_data is something phy will send to
smart card controller on some event, like card remove/insert/timeout etc..
That doesn't make much sense to me, why not just put that in the notify
function callback itself?
Please either use the existing phy layer of the kernel, or make a real
subsystem here, don't try to put a tiny shim on top of an existing
struct device for this driver, that's not how subsystems in Linux are
done.
thanks,
greg k-h
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On Thu, May 29, 2014 at 08:47:31AM -0500, Rob Herring wrote: On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote: On 5/29/2014 12:23 AM, Greg KH wrote: On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote: SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h These are .h files, but where is the api functions that use these structures defined at? This is like template/wrappers, smart card phy driver will write API functions. And smartcard controller will call these functions. With proposed approach, smartcard controller can communicate with any smart card phy (TI/NxP) without change in code. Using DT entry smartcard and PHY will gets connected with each other. Refer diagram given @Documentation/sc_phy.txt. confused, I believe the api Greg is wondering about is the notifier which as I commented is not a good design. That, and the fact that if this really is an api, there are no .c files for it like a normal api is in the kernel. There is now a phy subsystem. I don't know if it has what you need, but you should look at it to determine if it will work or could be extended to work. I agree. Satish, what's wrong with our existing phy layer? greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/5] misc: tda8026: Add NXP TDA8026 PHY driver
On Thu, May 29, 2014 at 02:07:59PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:14PM +0530, Satish Patel wrote:
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave device.
The driver also exposes the phy interface
(defined@include/linux/sc_phy.h) for SmartCard controller.
Controller uses this interface to communicate with smart card
inserted to the phy's slot.
Note: gpio irq is not validated as I do not have device with that.
I have validated interrupt with dedicated interrupt line on my device.
Signed-off-by: Satish Patel satish.pa...@ti.com
---
Documentation/devicetree/bindings/misc/tda8026.txt | 19 +
drivers/misc/Kconfig |7 +
drivers/misc/Makefile |1 +
drivers/misc/tda8026.c | 1258
4 files changed, 1285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt
create mode 100644 drivers/misc/tda8026.c
diff --git a/Documentation/devicetree/bindings/misc/tda8026.txt
b/Documentation/devicetree/bindings/misc/tda8026.txt
new file mode 100644
index 000..f115c9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/tda8026.txt
@@ -0,0 +1,19 @@
+TDA8026 smart card slot interface
+
+This is an i2c based smart card interface device forming the electrical
+interface between a microcontroller and smart cards. This device supports
+asynchronous cards (micro controller-based IC cards) as well as synchronous
+cards (mainly memory cards)
+
+Required properties:
+- compatible: nxp,tda8026
+- shutdown-gpio = GPIO pin mapping for SDWNN pin
+- reg = i2c interface address
+
+
+Example:
+tda8026: tda8026@48 {
+compatible = nxp,tda8026;
+reg = 0x48;
+shutdown-gpio = gpio5 19 GPIO_ACTIVE_HIGH;/* Bank5, pin19 */
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8baff0e..80b21d7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -515,6 +515,13 @@ config SRAM
the genalloc API. It is supposed to be used for small on-chip SRAM
areas found on many SoCs.
+config NXP_TDA8026_PHY
+tristate NXP PHY Driver for Smart Card PHY
+depends on I2C=y
+help
+ If you say yes here you get support for the TDA8026 Smart card
PHY
+ with I2C interface.
+
source drivers/misc/c2port/Kconfig
source drivers/misc/eeprom/Kconfig
source drivers/misc/cb710/Kconfig
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 7eb4b69..f262c0b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SRAM)+= sram.o
obj-y += mic/
obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO)+= echo/
+obj-$(CONFIG_NXP_TDA8026_PHY) += tda8026.o
diff --git a/drivers/misc/tda8026.c b/drivers/misc/tda8026.c
new file mode 100644
index 000..38df33e
--- /dev/null
+++ b/drivers/misc/tda8026.c
@@ -0,0 +1,1258 @@
+/*
+ * tda8026.c - TDA8026 PHY driver for NXP Smart card PHY
+ *
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/moduleparam.h
+#include linux/interrupt.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/mfd/core.h
+#include linux/notifier.h
+#include linux/sc_phy.h
+#include linux/of_gpio.h
+#include linux/of_device.h
+#include linux/delay.h
I think you just broke the build if this driver is enabled now right?
Not good :(
Before sending, I have applied these patches to v3.15-rc7 and build with
both the option ti-usim tda8026 as module, as well as part of kernel. Any
specific tree you would like me to rebase these patches against.
Did you try applying the patches one-by-one and building afterwards
between each one? In looking at this further, I think it will work, but
please test and make sure. You can not break the build with any
individual patch.
thanks,
greg k-h
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Re: [PATCH v3 3/5] char: ti-usim: Add driver for USIM module on AM43xx
On Thu, May 29, 2014 at 03:35:37PM +0530, Satish Patel wrote:
+enum usim_card_mode {
+ USIM_CARD_MODE_ASYNC = 0, /* asynchronous mode */
+ USIM_CARD_MODE_SYNC_TYPE1, /* synchronous mode: Type 1 */
+ USIM_CARD_MODE_SYNC_TYPE2, /* synchronous mode: Type 2 */
+ USIM_CARD_MODE_SYNC_OTHER, /* Any other synchronous type */
+};
+struct usim_data {
+ int slot;
+ int rxexplen;
+ int txlen;
+ unsigned char apdu[256];
+};
You need to use the proper variable types for a structure that is going
to cross the user/kernel boundry in an ioctl :(
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 10:18 AM, Liviu Dudau li...@dudau.co.uk wrote: On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote: On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Cc: Jason Gunthorpe jguntho...@obsidianresearch.com Cc: Bjorn Helgaas bhelg...@google.com Cc: Mohit Kumar mohit.ku...@st.com Cc: Jingoo Han jg1@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/pci/designware-pcie.txt|1 + drivers/pci/host/pcie-designware.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? Because what you end up using is a struct resource to represent the cfg space and the conversion between ranges and resources breaks down for CFG space (we don't have a flag in the resource flags to say this is CFG resource). Specifying it as a *reg* property makes it a MEM resource and no special casing is needed. Best regards, Liviu Just because the kernel doesn’t handle this is NO reason to change the way the DT works. We are probably better of changing of_bus_pci_get_flags() to set IORESOURCE_MEM for cfg type. Will send a patch for this. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote: Just because the kernel doesn’t handle this is NO reason to change the way the DT works. The OF specs do not specify how to process a config type ranges entry, and we all mutually agreed that the only sane interpretation for such a thing would be to describe an ECAM memory space so generic code could potentially make use of it. Since designware is not ECAM it should not use config ranges. This has come up multiple times now, and the above is the consensus. Jason -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ The configuration address space should also be specified here.
Kishon,
I am working on the Keystone PCI driver for which v1 is already posted.
Want to clarify
following.
1. Original text for reg states base addresses and lengths of the pcie
controller,
the phy controller, additional register for the phy controller
and you added
The configuration address space should also be specified here
and the code below added resource name config
Does PCI designware follow some convention? Does it mean after applying
this patch
config name is mandatory or optional? Below code you are not returning
error. Can you
or author of PCI designware clarify what is expected to be present as
mandatory and
what is optional.
Does config refers to RC's config space or EP's config space or both?
The code below divide
the size by 2. So it appears to be RC's + EP's config space. Please clarify.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
int __init dw_pcie_host_init(struct pcie_port *pp)
{
struct device_node *np = pp-dev-of_node;
+ struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+ struct resource *cfg_res;
u32 val;
int i;
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, config);
+ if (cfg_res) {
+ pp-config.cfg0_size = resource_size(cfg_res)/2;
+ pp-config.cfg1_size = resource_size(cfg_res)/2;
+ pp-cfg0_base = cfg_res-start;
+ pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+ } else {
+ dev_err(pp-dev, missing *config* reg space\n);
This should return error -EINVAL.
+ }
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+ pp-cfg0_base = pp-cfg.start;
+ pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
}
}
@@ -441,8 +456,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp-cfg0_base = pp-cfg.start;
- pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
pp-mem_base = pp-mem.start;
pp-va_cfg0_base = devm_ioremap(pp-dev, pp-cfg0_base,
BTW, Please also review my Keystone series so that we could discuss this
topic in that context
as well.
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 11:30 AM, Jason Gunthorpe jguntho...@obsidianresearch.com wrote: On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote: Just because the kernel doesn’t handle this is NO reason to change the way the DT works. The OF specs do not specify how to process a config type ranges entry, and we all mutually agreed that the only sane interpretation for such a thing would be to describe an ECAM memory space so generic code could potentially make use of it. Since designware is not ECAM it should not use config ranges. This has come up multiple times now, and the above is the consensus. Jason Well the designware controller does support ECAM, just that the current in kernel users don’t do cfg space that way. So do we continue to support the current users that use a cfg range for a non-ECAM space? Or break their DT and convert them to using regs? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
On Thu, May 29, 2014 at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Cc: Tony Lindgren t...@atomide.com Cc: Rob Herring robh...@kernel.org Cc: Pawel Moll pawel.m...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Kumar Gala ga...@codeaurora.org Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d43..b179e80 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,6 +75,8 @@ config SOC_DRA7XX select ARM_GIC select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI I believe we moved or intend to move this under MULTI_PLATFORM, so you don't need this. Will D. had a patch, but I don't think I saw a final version to merge. Rob + select ARCH_SUPPORTS_MSI config ARCH_OMAP2PLUS bool -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
On Thu, May 29, 2014 at 06:52:14PM +0100, Rob Herring wrote: On Thu, May 29, 2014 at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Cc: Tony Lindgren t...@atomide.com Cc: Rob Herring robh...@kernel.org Cc: Pawel Moll pawel.m...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Kumar Gala ga...@codeaurora.org Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d43..b179e80 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,6 +75,8 @@ config SOC_DRA7XX select ARM_GIC select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI I believe we moved or intend to move this under MULTI_PLATFORM, so you don't need this. Will D. had a patch, but I don't think I saw a final version to merge. I posted it earlier this week for somebody in arm-soc to pick up (although I don't think they have done yet): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/260238.html Will -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
On Fri 2014-05-16 14:12:31, Tony Lindgren wrote: * Paul Bolle pebo...@tiscali.nl [140515 12:42]: A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related Kconfig symbol was never part of the tree. So we can remove some dead code. Thanks applying into omap-for-v3.16/board. Actually... It seems there are two variant of SX1, and this is very useful piece of documentation how the _other_ variant looks. And if someone is hacking linux on sx1, he can probably figure out #ifdef in .c file... IOW adding the config option might be better solution. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: DRA722: add detection of SoC information.
Add support for DRA72x device DIEID. Currently these devices are
reported as DRA75/74 family of processors.
Signed-off-by: Nishanth Menon n...@ti.com
---
(test using linux-next next-20140529 tag):
before: http://slexy.org/raw/s21Yb8sOhy
after: http://slexy.org/raw/s20Nx96NrY
Applies on:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
branch: omap-for-v3.16/soc
arch/arm/mach-omap2/id.c | 12
arch/arm/mach-omap2/soc.h |1 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 71bf216..801244a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -649,6 +649,18 @@ void __init dra7xxx_check_revision(void)
}
break;
+ case 0xb9bc:
+ switch (rev) {
+ case 0:
+ omap_revision = DRA722_REV_ES1_0;
+ break;
+ default:
+ /* If we have no new revisions */
+ omap_revision = DRA722_REV_ES1_0;
+ break;
+ }
+ break;
+
default:
/* Unknown default to latest silicon rev as default*/
pr_warn(%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n,
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index de2a34c..01ca808 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -462,6 +462,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA7XX_CLASS 0x0700
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 16) | (0x10 8))
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 16) | (0x11 8))
+#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 16) | (0x10 8))
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
--
1.7.9.5
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Re: [PATCH] ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
* Pavel Machek pa...@ucw.cz [140529 12:03]: On Fri 2014-05-16 14:12:31, Tony Lindgren wrote: * Paul Bolle pebo...@tiscali.nl [140515 12:42]: A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related Kconfig symbol was never part of the tree. So we can remove some dead code. Thanks applying into omap-for-v3.16/board. Actually... It seems there are two variant of SX1, and this is very useful piece of documentation how the _other_ variant looks. And if someone is hacking linux on sx1, he can probably figure out #ifdef in .c file... IOW adding the config option might be better solution. Or just a comment saying the same? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
On Thu 2014-05-29 12:17:39, Tony Lindgren wrote: * Pavel Machek pa...@ucw.cz [140529 12:03]: On Fri 2014-05-16 14:12:31, Tony Lindgren wrote: * Paul Bolle pebo...@tiscali.nl [140515 12:42]: A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related Kconfig symbol was never part of the tree. So we can remove some dead code. Thanks applying into omap-for-v3.16/board. Actually... It seems there are two variant of SX1, and this is very useful piece of documentation how the _other_ variant looks. And if someone is hacking linux on sx1, he can probably figure out #ifdef in .c file... IOW adding the config option might be better solution. Or just a comment saying the same? Yes, #if 0 with a comment would do the same trick. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] omap dt fixes and and clocks for v3.16 merge window
On Wed, May 28, 2014 at 10:58:39AM -0700, Tony Lindgren wrote: The following changes since commit d712ff63b18309c939396f593510fbcccbafb9e4: ARM: dts: Enable mcpdm and mcbsp1 on DuoVero (2014-05-19 17:20:31 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.16/dt-part3 for you to fetch changes up to 43369f0fe81044427f6b1eedeb16bf8c74c86d48: Merge branch 'for-v3.16/clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v3.16/dt-v2 (2014-05-28 10:14:48 -0700) Most likely the last pull request from me for omap changes for v3.16 that's dts fixes for clocks and enabling few features that were still being discussed earlier: - A bunch of omap clock related dts fixes queued by Tero Kristo. - Enable parallel nand on am437x that was not merged earlier as I requested more information about the muxing for it. And we need to also enable ecc hardware support for am43xx. - Enable the modem support for n900 that was dropped earlier because we had to fix the related hwmod entry first with patch ARM: OMAP2+: Fix ssi hwmod entry to allow idling. - And finally, add the omap2 clock dts files. These will allow us to enable the dt clocks and drop the legacy clocks for omap2 with a follow-up patch once the related clock driver binding changes are merged. Merged into next/dt. Thanks. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On 5/29/2014 7:17 PM, Rob Herring wrote: On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote: On 5/29/2014 12:23 AM, Greg KH wrote: On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote: SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h These are .h files, but where is the api functions that use these structures defined at? This is like template/wrappers, smart card phy driver will write API functions. And smartcard controller will call these functions. With proposed approach, smartcard controller can communicate with any smart card phy (TI/NxP) without change in code. Using DT entry smartcard and PHY will gets connected with each other. Refer diagram given @Documentation/sc_phy.txt. confused, I believe the api Greg is wondering about is the notifier which as I commented is not a good design. There is now a phy subsystem. I don't know if it has what you need, but you should look at it to determine if it will work or could be extended to work. I have given my comments on notifier, it is required to notify real time events like card insert/remove to the smart card controller. As this interrupts tied to phy (in case phy is present) not with controller. Existing phy subsystem does not support generic operations for the phy. If at all it adds supports for these, in future I am ok to get align with it. Rob -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/5] char: ti-usim: Add driver for USIM module on AM43xx
On 5/29/2014 9:23 PM, Greg Kroah-Hartman wrote:
On Thu, May 29, 2014 at 03:35:37PM +0530, Satish Patel wrote:
+enum usim_card_mode {
+ USIM_CARD_MODE_ASYNC = 0, /* asynchronous mode */
+ USIM_CARD_MODE_SYNC_TYPE1, /* synchronous mode: Type 1 */
+ USIM_CARD_MODE_SYNC_TYPE2, /* synchronous mode: Type 2 */
+ USIM_CARD_MODE_SYNC_OTHER, /* Any other synchronous type */
+};
+struct usim_data {
+ int slot;
+ int rxexplen;
+ int txlen;
+ unsigned char apdu[256];
+};
You need to use the proper variable types for a structure that is going
to cross the user/kernel boundry in an ioctl :(
Do you mean to use __u32 instead int ? make use of types defined in
types.h ? if yes, I will make that change :). Thanks for pointing out.
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On 5/29/2014 9:21 PM, Greg KH wrote:
On Thu, May 29, 2014 at 02:26:55PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private data structure
+ * @set_config: called to set phy's configuration
+ * @get_config: called to get phy's configuration
+ * @activate_card: perform smart card activation
+ * @deactivate_card: perform smart card de-activation
+ * @warm_reset: execute smart card warm reset sequence
+ * @register_card_activity_cb: register call back to phy device.
+ * This call back will be called on card insert or remove event
+ *
+ * smart card controller uses this interface to communicate with
+ * smart card via phy.Some smart card phy has multiple slots for
+ * cards. This inerface also enables controller to communicate with
+ * one or more smart card connected over phy.
+ */
+struct sc_phy {
+ /* phy's device pointer */
+ struct device *dev;
So this is the parent, right? Why not embed a struct device into this
structure as well, further streaching out the device tree.
Do you mean to use dev-p for pdata ?
No, use the device itself.
I have kept it outside, to give easeness/pragmatic focal for new phy driver
development. Driver can make this pointer null and use above pointer.
Ick, no, that's not how the driver model works. Each device in the
system needs a struct device, don't try to chain off of an existing
device like this. Make it a real one.
+
+ /* phy's private data */
+ void *pdata;
If you do the above, then this pointer is not needed.
+
+ /* notify data, passed by interface user as a part of
+* register_notify API. Data should be passed back when
+* notification raised to the interface user
+*/
+ void *notify_data;
What makes this different from the pdata?
pdata is phy's private data, while notify_data is something phy will send to
smart card controller on some event, like card remove/insert/timeout etc..
That doesn't make much sense to me, why not just put that in the notify
function callback itself?
Little correction over here..
Here is brief flow
USIM(Smart Card Controller) register notification callback to smarcard phy.
usim-phy-register_notify(phy handle, callback fn, notify_data);
notify_data : pass back when callback function will be called by PHY
Smartcard PHY - USIM
blocking_notifier_call_chain(notifier, action, notify_data);
action : card insert/remove/overheat etc..
notify data: USIM data passing back (supplied at the time of cb
registration)
Please either use the existing phy layer of the kernel, or make a real
subsystem here, don't try to put a tiny shim on top of an existing
struct device for this driver, that's not how subsystems in Linux are
done.
Why I am not using exiting PHY framework ?
We will be more than happy to adapt generic phy if it
includes/add support for smart card requirements like
1) Some smart card phy (TDA8026-NxP) has multiple slots for smart
cards. This interface enables controller to communicate with specific
smart card inserted to the specific phy's slot.
2) Warm reset to smart card inserted to phy slot.
3) Bit banging of smart card pins to support vendor specific memory
cards.
4) Notification of card insert/remove/overheat etc.
5) synchronous and asynchronous modes for smart card transaction
thanks,
greg k-h
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hi,
On Thursday 29 May 2014 10:02 PM, Murali Karicheri wrote:
On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+The configuration address space should also be specified here.
Kishon,
I am working on the Keystone PCI driver for which v1 is already posted. Want
to
clarify
following.
1. Original text for reg states base addresses and lengths of the pcie
controller,
the phy controller, additional register for the phy controller and
you
added
The configuration address space should also be specified here
and the code below added resource name config
Does PCI designware follow some convention? Does it mean after applying this
patch
config name is mandatory or optional? Below code you are not returning error.
Can you
or author of PCI designware clarify what is expected to be present as
mandatory
and
what is optional.
From whatever I could make out from the comments for my previous version,
'config' is mandatory for all new platforms adding support for PCIe DW. However
since there already exists platforms that use 'ranges', I'm not returning
error. Once all the platforms that use DW is modified to use 'reg', will return
error.
Does config refers to RC's config space or EP's config space or both? The code
below divide
In the case of DRA7, it's the space from where you read the configuration space
contents of the EP (we have separate address space for the configuration space
of RC denoted by *rc_dbics* in this patch series). But there are other
platforms where RC does not have a separate configuration address space.
the size by 2. So it appears to be RC's + EP's config space. Please clarify.
No. divide by 2 is for cfg1 and cfg1 is used by PCIe bridges.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
int __init dw_pcie_host_init(struct pcie_port *pp)
{
struct device_node *np = pp-dev-of_node;
+struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+struct resource *cfg_res;
u32 val;
int i;
+cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
config);
+if (cfg_res) {
+pp-config.cfg0_size = resource_size(cfg_res)/2;
+pp-config.cfg1_size = resource_size(cfg_res)/2;
+pp-cfg0_base = cfg_res-start;
+pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+} else {
+dev_err(pp-dev, missing *config* reg space\n);
This should return error -EINVAL.
ah.. it'll break for other platforms. It should be part of a different patch
once we convert all users to 8reg*.
+}
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+pp-cfg0_base = pp-cfg.start;
+pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
}
