On Tuesday 24 June 2014 20:47:58 Suman Anna wrote:
+static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller
*controller,
+ const struct of_phandle_args *sp)
+{
+ phandle phandle = sp-args[0];
+ struct device_node *node;
+
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when
Hi,
On Tuesday 24 June 2014 03:34 PM, Tomi Valkeinen wrote:
Make the omapdrm driver use the new HDMI ops when possible.
omapdrm will call set_hdmi_mode (when available) to tell the encoder
driver whether the monitor is a DVI or HDMI monitor, and if it's an HDMI
monitor, omapdrm will call
On Wed, Jun 25, 2014 at 02:40:16AM +0100, Felipe Balbi wrote:
Hi,
On Tue, Jun 24, 2014 at 04:11:48PM -0500, Rob Herring wrote:
On Mon, Jun 23, 2014 at 1:20 PM, Felipe Balbi ba...@ti.com wrote:
by providing phandles to rtc, wdt, cpu and dispc nodes,
boards can access them to add
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the
On 25/06/14 14:03, Archit Taneja wrote:
Hi,
On Tuesday 24 June 2014 03:34 PM, Tomi Valkeinen wrote:
Make the omapdrm driver use the new HDMI ops when possible.
omapdrm will call set_hdmi_mode (when available) to tell the encoder
driver whether the monitor is a DVI or HDMI monitor, and if
As this board use external clock for RMII interface we should specify 'rmii'
phy mode and 'rmii-clock-ext' to make ethernet working.
Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com
---
arch/arm/boot/dts/am335x-igep0033.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB
A struct member variable is set to the same value more than once
This was found using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
arch/arm/mach-omap2/usb-tusb6010.c |1 -
1 file changed, 1 deletion(-)
diff
On Wed, Jun 25 2014 at 01:21:17 PM, Rob Herring robherri...@gmail.com wrote:
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have
The SATA and USB PHYs need the 1.8V and 3.3V supplies.
The PHY drivers/framework don't yet support regulator
supply so we have to keep these regulators always-on till
then.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 2 ++
1 file changed, 2 insertions(+)
diff
On Tue, Jun 24, 2014 at 05:04:36PM -0500, Darren Etheridge wrote:
On 06/17/2014 09:17 AM, Guido Martínez wrote:
Use module_init instead of late_initcall, as is the norm for modular
drivers.
module_init was used until 6e8de0bd6a51fdeebd5d975c4fcc426f730b339b
(drm/tilcdc: add encoder slave
On Wed, Jun 25, 2014 at 02:00:42PM +0100, Russell King - ARM Linux wrote:
On Tue, Jun 24, 2014 at 05:04:36PM -0500, Darren Etheridge wrote:
On 06/17/2014 09:17 AM, Guido Martínez wrote:
Use module_init instead of late_initcall, as is the norm for modular
drivers.
module_init was used
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.
First four patches extend existing support for secure
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++
arch/arm/mm/cache-l2x0.c | 46 ++
2 files changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
According to the documentation, TAG_LATENCY_CTRL and DATA_LATENCY_CTRL
registers of L2C-310 can be written only in secure mode, so
l2c_write_sec() should be used to change them, instead of plain
writel_relaxed().
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 16
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git
For certain platforms (e.g. Exynos) it is necessary to read back some
values from registers before they can be written (i.e. SMC calls that
set multiple registers per call), so base address of L2C controller is
needed for .write_sec operation. This patch adds base argument to
.write_sec callback
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec callback
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of
(Ccing Guido back)
Hello Russell, Darren,
On 25 Jun 02:00 PM, Russell King - ARM Linux wrote:
On Tue, Jun 24, 2014 at 05:04:36PM -0500, Darren Etheridge wrote:
On 06/17/2014 09:17 AM, Guido Martínez wrote:
Use module_init instead of late_initcall, as is the norm for modular
drivers.
On Wed, Jun 25, 2014 at 04:13:16PM +0200, Tomasz Figa wrote:
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which
On Wed, Jun 25, 2014 at 11:32:46AM -0300, Ezequiel García wrote:
(Ccing Guido back)
Hello Russell, Darren,
On 25 Jun 02:00 PM, Russell King - ARM Linux wrote:
On Tue, Jun 24, 2014 at 05:04:36PM -0500, Darren Etheridge wrote:
If I recall, the late_initcall stuff was done to try and make
On 24 Jun 05:06 PM, Darren Etheridge wrote:
On 06/17/2014 09:17 AM, Guido Martínez wrote:
The TI tilcdc driver is designed with a notion of submodules. Currently,
at unload time, these submodules are iterated and destroyed.
Now that the tilcdc remove order is fixed, this can be handled
On 25 Jun 04:38 AM, Gupta, Pekon wrote:
From: Ezequiel Garcia
On 24 Jun 05:54 PM, Pekon Gupta wrote:
This patch adds support for LCD4 cape as advertised on
http://elinux.org/CircuitCo:BeagleBone_LCD4
This cape has:
* 480x272 TFT-LCD panel
- LCD panel datasheet and timing
On 24 Jun 05:54 PM, Pekon Gupta wrote:
+gpmc {
+ ranges = 0 0 0 0x0100;/* address range = 16MB (minimum GPMC
partition) */
+ nand@0,0 {
+ status = disabled;
+ reg = 0 0 4; /* device IO registers */
+ pinctrl-names = default;
+
On 25.06.2014 16:37, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 04:13:16PM +0200, Tomasz Figa wrote:
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on
Hi Russell,
On 25 Jun 03:46 PM, Russell King - ARM Linux wrote:
That doesn't make any sense. Using late_initcall for the tilcdc DRM
driver would make the tilcdc DRM get probed before any other regular
module_init driver, including the tda998x encoder.
A module_init() is a
Hi Arnd,
On 06/25/2014 03:39 AM, Arnd Bergmann wrote:
On Tuesday 24 June 2014 20:47:58 Suman Anna wrote:
+static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller
*controller,
+ const struct of_phandle_args *sp)
+{
+ phandle phandle
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros rog...@ti.com
Tested-by: Roger Quadros rog...@ti.com
I used this patch for testing PCIe.
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Please find the
[1] is split into separate series in order for individual subsystem
Maintainers to pick up the patches. This series handles the PCIe
hwmod data for DRA7.
Please find the bootlog with these hwmod patches @ [2]
[1] - https://lkml.org/lkml/2014/5/29/258
[2] - http://paste.ubuntu.com/7701601/
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay
On Tue, 24 Jun 2014, Suman Anna wrote:
OMAP2 devices are devicetree boot only, and the legacy mode
of mailbox device creation should no longer be used, so remove
the mailbox attribute data and the hwmod addr space used for
creating mailboxes in legacy mode.
Cc: Paul Walmsley p...@pwsan.com
On Tue, 24 Jun 2014, Suman Anna wrote:
The legacy-style definition of the hwmod addr space is no longer
required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox
DT nodes have been added, so clean up this data.
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Suman Anna
On 06/25/2014 07:56 AM, Roger Quadros wrote:
The SATA and USB PHYs need the 1.8V and 3.3V supplies.
The PHY drivers/framework don't yet support regulator
supply so we have to keep these regulators always-on till
then.
Signed-off-by: Roger Quadros rog...@ti.com
---
On Wed, Jun 25, 2014 at 1:49 AM, Gupta, Pekon pe...@ti.com wrote:
From: Jason Kridner [mailto:jkrid...@gmail.com]
On Tue, Jun 24, 2014 at 8:24 AM, Pekon Gupta pe...@ti.com wrote:
This patch adds support for LCD4 cape as advertised on
http://elinux.org/CircuitCo:BeagleBone_LCD4
[...]
diff
From: Ezequiel Garcia [mailto:ezequ...@vanguardiasur.com.ar]
On 24 Jun 05:54 PM, Pekon Gupta wrote:
+gpmc {
+ranges = 0 0 0 0x0100;/* address range = 16MB (minimum GPMC
partition) */
+nand@0,0 {
+status = disabled;
+reg = 0 0 4; /* device IO
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