RE: Patches merged to split OMAP2_IO_ADDRESS
-Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Shilimkar, Santosh Sent: Friday, October 09, 2009 10:51 AM To: Tony Lindgren Cc: linux-omap@vger.kernel.org; Paul Walmsley Subject: RE: Patches merged to split OMAP2_IO_ADDRESS -Original Message- From: Tony Lindgren [mailto:t...@atomide.com] Sent: Thursday, October 08, 2009 11:38 PM To: Shilimkar, Santosh Cc: linux-omap@vger.kernel.org; Paul Walmsley Subject: Re: Patches merged to split OMAP2_IO_ADDRESS * Shilimkar, Santosh santosh.shilim...@ti.com [091008 03:59]: Tony, -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Tony Lindgren Sent: Thursday, October 08, 2009 5:55 AM To: linux-omap@vger.kernel.org Cc: Paul Walmsley Subject: Patches merged to split OMAP2_IO_ADDRESS Hi all, I've pushed Santosh' patches to split OMAP2_IO_ADDRESS into *_L3_IO_ADDRESS and *_L4_IO_ADDRESS so we can claim more kernel address space and support over 512MB of memory instead of 256MB. Of course, our goal is to convert everything except the .S files to use ioremap() instead, but that can now be done parallel and in smaller chunks. Please everybody, please convert your code to use ioremap(), there are static mappings already in place so it should work out of the box. I also had add two quick patches to keep things compiling, Paul can you take a look at them? I could not really test them as all the code is not there yet. Will post them as a reply to this thread. Thanks for the merge!! I have boot tested below platforms with latest LO master. 1. OMAP3430 SDP board - BOOT OK 2. OMAP3 BEAGLE - BOOT OK 3. OMAP 4430 SDP - BOOT OK with variation of patch: http://patchwork.kernel.org/patch/50531/ Great. I guess we still have some issues on 24xx with the hwmod, but hopefully we'll get that working again soon. Can somebody with 512MB memory on a board try the current l-o master and make sure things work? Please check the dmesg for no overlaps in virtual address space, then run some memory test like memtester. Boot tested on OMAP4430 with 512MB and dmesg don't show any overlaps. Will run some memory test tomorrow. Run the memmark benchmark on OMAP4430 and not seen any issue. Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop
This small typo written by author causes that McBSP receiver is disabled on
OMAP2430 and OMAP3430 even if only transmitter is stopped. This was noted
with ALSA SoC where simultaneous recording halted if playback was stopped
first.
Signed-off-by: Jarkko Nikula jhnik...@gmail.com
---
arch/arm/plat-omap/mcbsp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 88ac976..e664b91 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -595,7 +595,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
rx = 1;
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
w = OMAP_MCBSP_READ(io_base, RCCR);
- w |= (tx ? RDISABLE : 0);
+ w |= (rx ? RDISABLE : 0);
OMAP_MCBSP_WRITE(io_base, RCCR, w);
}
w = OMAP_MCBSP_READ(io_base, SPCR1);
--
1.6.3.3
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[PATCH v1 1/2] arm: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin virtu...@slind.org
Signed-off-by: Juha Leppanen juha_motorsport...@luukku.com
---
Changes:
v1 -- fixed comments from Juha Leppanen
v0 -- initial implementation, has been sent to linux-omap only
arch/arm/Kconfig.debug|8 +
arch/arm/include/asm/hardware/coresight.h | 164
arch/arm/kernel/Makefile |2 +
arch/arm/kernel/etm.c | 588 +
4 files changed, 762 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/coresight.h
create mode 100644 arch/arm/kernel/etm.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e..ac83c03 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
It does include a timeout to ensure that the system does not
totally freeze when there is nothing connected to read.
+config OC_ETM
+ tristate On-chip ETM and ETB
+ depends on ARCH_OMAP3
+ help
+ Enables the on-chip embedded trace macrocell and embedded trace
+ buffer driver that will allow you to collect traces of the
+ kernel code.
+
config DEBUG_DC21285_PORT
bool Kernel low-level debugging messages via footbridge serial port
depends on DEBUG_LL FOOTBRIDGE
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000..ba22df9
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,164 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+
+#define TRACER_ACCESSED_BIT0
+#define TRACER_RUNNING_BIT 1
+#define TRACER_CYCLE_ACC_BIT 2
+#define TRACER_ACCESSEDBIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
+
+struct tracectx {
+ unsigned int etb_bufsz;
+ void __iomem *etb_regs;
+ void __iomem *etm_regs;
+ unsigned long flags;
+ int ncmppairs;
+ int etm_portsz;
+ struct device *dev;
+ struct mutex mutex;
+};
+
+#define TRACER_TIMEOUT 1
+
+#define etm_writel(t, v, x) \
+ (__raw_writel((v), (t)-etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)-etm_regs + (x)))
+
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID 0xfc8
+#define CSMR_DEVTYPE 0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS 0xff4
+
+#define CSCR_PRSR 0x314
+
+#define UNLOCK_MAGIC 0xc5acce55
+
+/* ETM control register, ETM Architecture, 3.3.1 */
+#define ETMR_CTRL 0
+#define ETMCTRL_POWERDOWN 1
+#define ETMCTRL_PROGRAM(1 10)
+#define ETMCTRL_PORTSEL(1 11)
+#define ETMCTRL_DO_CONTEXTID (3 14)
+#define ETMCTRL_PORTMASK1 (7 4)
+#define ETMCTRL_PORTMASK2 (1 21)
+#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) x) 7) 4) | (!!((x) 8)) 21)
+#define ETMCTRL_DO_CPRT(1 1)
+#define ETMCTRL_DATAMASK (3 2)
+#define ETMCTRL_DATA_DO_DATA (1 2)
+#define ETMCTRL_DATA_DO_ADDR (1 3)
+#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT (1 8)
+#define ETMCTRL_CYCLEACCURATE (1 12)
+
+/* ETM configuration code register */
+#define ETMR_CONFCODE (0x04)
+
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL (0x18)
+
+/* ETM trigger event register */
+#define ETMR_TRIGEVT (0x08)
+
+/* address access type register bits, ETM architecture,
+ * table 3-27 */
+/* - access type */
+#define ETMAAT_IFETCH 0
+#define ETMAAT_IEXEC 1
+#define ETMAAT_IEXECPASS 2
+#define ETMAAT_IEXECFAIL 3
+#define ETMAAT_DLOADSTORE 4
+#define ETMAAT_DLOAD 5
+#define ETMAAT_DSTORE 6
+/* - comparison access size */
+#define ETMAAT_JAVA(0 3)
+#define ETMAAT_THUMB (1 3)
+#define ETMAAT_ARM
[PATCH v1 2/2] OMAP3: add platform devices for ETM and ETB
This enables debug components found in omap3xxx.
Signed-off-by: Alexander Shishkin virtu...@slind.org
---
arch/arm/mach-omap2/Kconfig |7
arch/arm/mach-omap2/Makefile |3 ++
arch/arm/mach-omap2/emu.c| 70 ++
3 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/emu.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 75b1c7e..87bcc2a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -88,3 +88,10 @@ config MACH_OMAP_ZOOM2
config MACH_OMAP_4430SDP
bool OMAP 4430 SDP board
depends on ARCH_OMAP4
+
+config OMAP3_EMU
+ tristate OMAP3 debugging peripherals
+ depends on ARCH_OMAP3 OC_ETM
+ help
+ Say Y here to enable debugging hardware of omap3
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6b7702f..572dd27 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,6 +44,9 @@ obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
+# EMU periferals
+obj-$(CONFIG_OMAP3_EMU)+= emu.o
+
iommu-y+= iommu2.o
iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000..f98874e
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,70 @@
+/*
+ * linux/arch/arm/mach-omap2/emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/io.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE (L4_EMU_34XX_PHYS + 0x1)
+#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
+#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
+
+static struct resource rx51_etb_resource = {
+ .start = ETB_BASE,
+ .end = ETB_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etb_device = {
+ .name = etb,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etb_resource,
+};
+
+static struct resource rx51_etm_resource = {
+ .start = ETM_BASE,
+ .end = ETM_BASE + SZ_4K,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device rx51_etm_device = {
+ .name = etm,
+ .id = -1,
+ .num_resources = 1,
+ .resource = rx51_etm_resource,
+};
+
+static struct platform_device *rx51_trace_devices[] = {
+ rx51_etm_device,
+ rx51_etb_device,
+};
+
+static int __init emu_init(void)
+{
+ platform_add_devices(rx51_trace_devices,
+ ARRAY_SIZE(rx51_trace_devices));
+
+ return 0;
+}
+
+module_init(emu_init);
+
--
1.6.3.3
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Re: [PATCH 1/2] arm/omap3: a driver for on-chip ETM and ETB
2009/10/10 Shilimkar, Santosh santosh.shilim...@ti.com: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of virtu...@slind.org Sent: Thursday, October 08, 2009 3:06 AM To: linux-omap@vger.kernel.org Cc: Alexander Shishkin Subject: [PATCH 1/2] arm/omap3: a driver for on-chip ETM and ETB From: Alexander Shishkin virtu...@slind.org This driver implements /dev/tracebuf and some control files for ETM and ETB in sysfs. Looks like a very useful driver for tracing/debug. Do you have some README link on the usage of this driver ? Well, here's a brief intro into how to collect traces and decode them: http://wiki.github.com/virtuoso/etm2human/quickstart That's not much, but if you have any questions, just email them to me and I'll try to update the page. Regards, -- Alex -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1 1/2] arm: a driver for on-chip ETM and ETB
2009/10/11 Alexander Shishkin virtu...@slind.org:
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Cool, can it at all be interfaced to kernel tracing mechanisms like
ftrace, LTTng...? Or is this entirely orthogonal?
First, these are registered as platform devices, should they not be AMBA
devices (i.e. PrimeCells?) I think that's what they are, and they probably
have device ID:s to be matched in the last words of their 4K pages
do they not?
(...)
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
new file mode 100644
index 000..3e7b431
--- /dev/null
+++ b/arch/arm/kernel/etm.c
@@ -0,0 +1,588 @@
+/*
+ * linux/arch/arm/kernel/etm.c
+ *
+ * Driver for ARM's Embedded Trace Macrocell and Embedded Trace Buffer.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/types.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/sysrq.h
+#include linux/platform_device.h
+#include linux/fs.h
+#include linux/uaccess.h
+#include linux/miscdevice.h
+#include linux/vmalloc.h
+#include linux/mutex.h
+#include asm/hardware/coresight.h
+#include asm/sections.h
+
+MODULE_LICENSE(GPL);
+MODULE_AUTHOR(Alexander Shishkin);
+
+static struct tracectx tracer;
+
+static inline bool trace_isrunning(struct tracectx *t)
+{
+ return !!(t-flags TRACER_RUNNING);
+}
+
+static int etm_setup_address_range(struct tracectx *t, int n,
+ unsigned long start, unsigned long end, int exclude, int data)
+{
+ u32 flags = ETMAAT_ARM | ETMAAT_IGNCONTEXTID | ETMAAT_NSONLY | \
+ ETMAAT_NOVALCMP;
+
+ if (n 1 || n t-ncmppairs)
+ return -EINVAL;
+
+ /* comparators and ranges are numbered starting with 1 as opposed
+ * to bits in a word */
+ n--;
+
+ if (data)
+ flags |= ETMAAT_DLOADSTORE;
+ else
+ flags |= ETMAAT_IEXEC;
+
+ /* first comparator for the range */
+ etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2));
+ etm_writel(t, start, ETMR_COMP_VAL(n * 2));
+
+ /* second comparator is right next to it */
+ etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2 + 1));
+ etm_writel(t, end, ETMR_COMP_VAL(n * 2 + 1));
+
+ flags = exclude ? ETMTE_INCLEXCL : 0;
+ etm_writel(t, flags | (1 n), ETMR_TRACEENCTRL);
+
+ return 0;
+}
+
+static int trace_start(struct tracectx *t)
+{
+ u32 v;
+ unsigned long timeout = TRACER_TIMEOUT;
+
+ etb_unlock(t);
+
+ etb_writel(t, 0, ETBR_FORMATTERCTRL);
+ etb_writel(t, 1, ETBR_CTRL);
+
+ etb_lock(t);
+
+ /* configure etm */
+ v = ETMCTRL_OPTS | ETMCTRL_PROGRAM | ETMCTRL_PORTSIZE(t-etm_portsz);
+
+ if (t-flags TRACER_CYCLE_ACC)
+ v |= ETMCTRL_CYCLEACCURATE;
+
+ etm_unlock(t);
+
+ etm_writel(t, v, ETMR_CTRL);
+
+ while (!(etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM) --timeout)
+ ;
+ if (!timeout) {
+ dev_dbg(t-dev, Waiting for progbit to assert timed out\n);
+ etm_lock(t);
+ return -EFAULT;
+ }
+
+ etm_setup_address_range(t, 1, (unsigned long)_stext,
+ (unsigned long)_etext, 0, 0);
+ etm_writel(t, 0, ETMR_TRACEENCTRL2);
+ etm_writel(t, 0, ETMR_TRACESSCTRL);
+ etm_writel(t, 0x6f, ETMR_TRACEENEVT);
+
+ v = ~ETMCTRL_PROGRAM;
+ v |= ETMCTRL_PORTSEL;
+
+ etm_writel(t, v, ETMR_CTRL);
+
+ timeout = TRACER_TIMEOUT;
+ while (etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM --timeout)
+ ;
+ if (!timeout) {
+ dev_dbg(t-dev, Waiting for progbit to deassert timed
out\n);
+ etm_lock(t);
+ return -EFAULT;
+ }
+
+ etm_lock(t);
+
+ t-flags |= TRACER_RUNNING;
+
+ return 0;
+}
+
+static int trace_stop(struct tracectx *t)
+{
+ unsigned long timeout = TRACER_TIMEOUT;
+
+ etm_unlock(t);
+
+ etm_writel(t, 0x440, ETMR_CTRL);
+ while (!(etm_readl(t, ETMR_CTRL) ETMCTRL_PROGRAM) --timeout)
+ ;
+ if (!timeout) {
+ dev_dbg(t-dev, Waiting for progbit to assert timed out\n);
+ etm_lock(t);
+ return -EFAULT;
+ }
+
+ etm_lock(t);
+
+ etb_unlock(t);
+ etb_writel(t, ETBFF_MANUAL_FLUSH, ETBR_FORMATTERCTRL);
+
+ timeout = TRACER_TIMEOUT;
+ while
Re: [PATCH v1 1/2] arm: a driver for on-chip ETM and ETB
On Mon, Oct 12, 2009 at 12:07:57AM +0200, Linus Walleij wrote: First, these are registered as platform devices, should they not be AMBA devices (i.e. PrimeCells?) I think that's what they are, and they probably have device ID:s to be matched in the last words of their 4K pages do they not? It does look like it's Primecell-like, so it should be using the primecell support so that others can make use of this. As such, it should not be OMAP specific. + clk = clk_get(pdev-dev, emu_core_alwon_ck); + clk_enable(clk); + + clk = clk_get(pdev-dev, emu_per_alwon_ck); + clk_enable(clk); + + clk = clk_get(pdev-dev, emu_mpu_alwon_ck); + clk_enable(clk); + + clk = clk_get(pdev-dev, emu_src_ck); + clk_enable(clk); Are these clocks really generic? It looks a lot like OMAP-specific stuff. Is it possible to hide these behind a single clock inside the platform? like etbclock or so that increase refcount of the others by 1? First obvious problem is that there's no error checking there. Second problem is that this could very well be a generic driver, and OMAP specifics should not be in here. Looking at the Coresight ETM11 documentation, there's: ATCLK - ATB interface clock CLK - main clock PCLKDBG - Debug APB clock or PCLK - APB clock I'm not sure why OMAP seems to have four clocks when the ETM has only three clocks itself. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
