On Thursday 24 April 2014 06:43 PM, Arnd Bergmann wrote:
On Thursday 24 April 2014, Rajendra Nayak wrote:
-- DRA742
- compatible = ti,dra7xx, ti,dra7
+- DRA74x
+ compatible = ti,dra74, ti,dra7
+
+- DRA72x
+ compatible = ti,dra72, ti,dra7
Actually, what I meant was that you should
On Thursday 24 April 2014 10:39 PM, Suman Anna wrote:
Hi Rajendra,
On 04/24/2014 05:06 AM, Nayak, Rajendra wrote:
The only difference from the dra74x devices is the missing .smp entry.
While at it, also fix the use of __initdata (across the file) and replace
them
with __initconst as
On 25/04/14 18:31, Tony Lindgren wrote:
Chances are any mux register in the syscon area already works with
pinctrl-single,pins or pinctrl-single,bits option. The ones in the
padconf area should be already mapped so the driver just has to
request them.
If using the padconf (say
On Mon, Apr 28, 2014 at 09:40:20AM +0530, George Cherian wrote:
CPTS refclk name is hardcoded, which makes it fail in case of DRA7x
Remove the hardcoded clock name for CPTS refclk and get the same from DT.
Patch ordering - doesn't this patch depend on patch #2?
Thanks,
Richard
--
To
On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote:
cpsw_cpts_rft_clk has got the choice of 3 clocksources
-dpll_core_m4_ck
-dpll_core_m5_ck
-dpll_disp_m2_ck
By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck
Hi Balaji, Tony, all
v10
- bug fix on multi-core, untested
- incorporated changes from Balaji
- use devres / RAII mechanism to configure wake_up /
sdio irq capabilities
- drop pinctrl state 'active'
rely on driver-model states 'default', 'idle'
- add specific 'gpio_dat1' state for am335x
on multicores, an sdio irq handler could be running in parallel to
runtime suspend. In the worst case it could be waiting for the spinlock
held by the runtime suspend. When runtime suspend is complete and the
functional clock (fclk) turned off, the irq handler will continue and
cause a SIGBUS on
There have been various patches floating around for enabling
the SDIO IRQ for hsmmc, but none of them ever got merged.
Probably the reason for not merging the SDIO interrupt patches
has been the lack of wake-up path for SDIO on some omaps that
has also needed remuxing the SDIO DAT1 line to a GPIO
The am335x can't detect pending cirq in PM runtime suspend.
This patch reconfigures dat1 as a GPIO before going to suspend.
SDIO interrupts are detected with the GPIO, the GPIO will only wake
the module from suspend, SDIO irq detection will still happen through the
IP block.
Idea of remuxing the
Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current
state of data lines, incl. SDIO IRQ pending
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index
These are predefined states of the driver model. When not present,
as if not set in the device tree, they simple become no-ops.
So it is always safe to call them.
This is not the simplest implementation, on AM335x at least, we could
witch to idle at any point in the suspend hook, only the default
Hi Balaji, Tony, all
v10
- bug fix on multi-core, untested
- incorporated changes from Balaji
- use devres / RAII mechanism to configure wake_up /
sdio irq capabilities
- drop pinctrl state 'active'
rely on driver-model states 'default', 'idle'
- add specific 'gpio_dat1' state for am335x
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should have its own code variant.
while at that
From: Yegor Yefremov yegorsli...@googlemail.com
This patch creates unique DMA channels for the second USB
interface, otherwise the second USB interface is not usable
at all.
Signed-off-by: Yegor Yefremov yegorsli...@googlemail.com
---
arch/arm/boot/dts/am33xx.dtsi | 12 ++--
1 files
On Monday 28 April 2014 11:39:22 Rajendra Nayak wrote:
DRA742 EVM: Software Developement Board for DRA742
compatible = ti,dra7-evm, ti,dra742, ti,dra74, ti,dra7
DRA722 EVM: Software Development Board for DRA722
compatible = ti,dra72-evm, ti,dra722, ti,dra72, ti,dra7
I was also calling
On Monday 28 April 2014 02:20 PM, Arnd Bergmann wrote:
On Monday 28 April 2014 11:39:22 Rajendra Nayak wrote:
DRA742 EVM: Software Developement Board for DRA742
compatible = ti,dra7-evm, ti,dra742, ti,dra74, ti,dra7
DRA722 EVM: Software Development Board for DRA722
compatible =
Commit 4df42de9d3e gpio: omap: add a GPIO_OMAP option instead of using
ARCH_OMAP made it possible to build OMAP kernels without the GPIO driver,
which at least on OMAP2 and OMAP3 causes build errors because of functions
used by the platform power management code:
arch/arm/mach-omap2/built-in.o:
On 04/24/2014 09:52 PM, Greg KH wrote:
On Mon, Apr 14, 2014 at 01:46:11PM +0200, Robert Baldyga wrote:
This patchset adds many improvements to extcon class driver and extcon
provider drivers. It changes extcon API to faster and safer by replaceing
function taking extcon and cable names with
All boards using twl6040 configures the i2c bus to 400KHz. While twl6040's
defaults to normal mode (100KHz). So far twl6040 has no problem with i2c
communication in this configuration it is safer to select fast i2c mode.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Make sure that we patch the ACCCTL register as the first thing when the
driver loads, thus configuring I2C fast mode and i2c access for dual access
registers.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/mfd/twl6040.c | 7 +++
1 file changed, 3 insertions(+), 4
If for some reason the boot loader enabled the audpwron GPIO we will have
pending IRQs to be handled. This seams to break twl6040 for some reason
leading to non working i2c communication (i2c timeouts). Clearing the INTID
register after we requested the audpwron GPIO (and set it to low) will
On 26/04/14 02:53, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [140424 02:53]:
On 18/04/14 18:51, Tony Lindgren wrote:
+ gpio = of_get_gpio(node, 0);
+ if (gpio_is_valid(gpio) || gpio == -ENOENT) {
+ ddata-enable_gpio = gpio;
+ } else {
+
Fix two format string mismatch in display-sysfs.c
Signed-off-by: Masanari Iida standby2...@gmail.com
---
drivers/video/fbdev/omap2/dss/display-sysfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/omap2/dss/display-sysfs.c
On Monday, April 28, 2014 7:54 PM, Masanari Iida wrote:
Fix two format string mismatch in display-sysfs.c
Signed-off-by: Masanari Iida standby2...@gmail.com
---
drivers/video/fbdev/omap2/dss/display-sysfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
The twl4030 PMIC needs to be configured properly for things like
warm reset and deeper idle states so the PMIC manages the regulators
properly based on the hardware triggers from the SoC.
For example, when rebooting an OMAP3530 at 125 MHz, it hangs.
With this patch, TWL4030 will be reset
These settings are based on the Recommended Sleep Sequences for
the Zoom Platform pdf at:
http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
These settings assume most of the regulators are under control of
Linux, and cuts off VDD1 and VDD2 during off-idle as Linux cannot
Add support of AW-NH387 (mwifiex) WiFi/BT chip connected to MMC3.
Signed-off-by: Dmitry Lifshitz lifsh...@compulab.co.il
---
Changes from V1:
* Platform quirk for deasserting PDN and RST GPIOs of WiFi chip replaced by
appropriate regulators in DT.
arch/arm/boot/dts/omap5-cm-t54.dts | 53
Add support for CompuLab CM-T54 CoM and SBC-T54 board:
http://compulab.co.il/products/computer-on-modules/cm-t54/
http://compulab.co.il/products/sbcs/sbc-t54/
SBC-T54 is a single board computer based on OMAP5432 CPU.
It is implemented with a CM-T54 CoM providing most of the
Add support for CM-T54 CoM and SBC-T54 board:
http://compulab.co.il/products/computer-on-modules/cm-t54/
http://compulab.co.il/products/sbcs/sbc-t54/
SBC-T54 is a single board computer based on OMAP5432 CPU.
It is implemented with a CM-T54 CoM providing most of the functions,
and SB-T54 carrier
With the recommended twl4030 configuration added, we can now add
board specific changes as modifications to the recommended
configuration.
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo...@linaro.org
Signed-off-by: Tony Lindgren
Some oscillators can be turned off during off-idle saving few
a little bit power at the cost of the oscillator start up
latency.
If you board can do this, you can now enable it by using the
ti,twl4030-power-idle-osc-off compatible flag.
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Cc:
From: Jarkko Nikula jarkko.nik...@bitmer.com
Machine specific trigger callback allows to do final stream start/stop
related operations in a machine driver after setting up the codec, DMA and
DAI.
One example could be clock management for linked streams case where machine
driver can start/stop
Add ha for HEAD acoustics to the list of DT vendor prefixes.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Thorsten Eisbein thorsten.eisb...@head-acoustics.de
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Jarkko Nikula jarkko.nik...@bitmer.com
HA DSP card which features a HA DSP audio codec is intended to be connected
to TAO-3530 (or BeagleBoard) using McBSP3 for digital audio and I2C bus for
codec control. A GPIO signal from CPU to codec is used to request clock
signals active.
This
From: Jarkko Nikula jarkko.nik...@bitmer.com
This codec driver template represents an I2C controlled multichannel audio
codec that has many typical ASoC codec driver features like volume controls,
mixer stages, mux selection, output power control, in-codec audio routings,
codec bias management
Signed-off-by: Stefan Roese s...@denx.de
Cc: Thorsten Eisbein thorsten.eisb...@head-acoustics.de
---
.../devicetree/bindings/sound/omap3-ha.txt | 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/omap3-ha.txt
diff
:sdp3430: Boot PASS: http://slexy.org/raw/s2Mo7s3ttZ
15: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s2qXj7HFTJ
=
[ INFO: possible recursive locking detected ]
3.15.0-rc2-next-20140428-2-gd0ca5e6 #1 Not tainted
On 4/28/2014 1:25 PM, Richard Cochran wrote:
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should
On 4/28/2014 12:40 PM, Richard Cochran wrote:
On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote:
cpsw_cpts_rft_clk has got the choice of 3 clocksources
-dpll_core_m4_ck
-dpll_core_m5_ck
-dpll_disp_m2_ck
By default dpll_core_m4_ck is selected, witn this as clock
source the
This patch adds qspi nodes for am43xx SOC devices.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Note,
checpatch gives 1 warning on flash compatible string
mx66l51235l. This flash is supported in m25p80 driver and
the driver is used for other flash devices also. Hence, each
flash
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
---
arch/arm/boot/dts/am335x-igep0033.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
---
arch/arm/boot/dts/am335x-evmsk.dts | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 149
Add wkupclk and refclk information to DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
Add USB pinmux information and USB modes
for the USB controllers.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index
Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
Hi,
This series enables the 2 USB ports on the DRA7-evm.
NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port
in host mode. This is due to missing ID pin interrupt in pre ver.E boards.
USB1 port doesn't in peripheral mode out of the box due to missing VBUS
detection
and
The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap4.dtsi | 2 ++
arch/arm/boot/dts/omap5.dtsi | 2 ++
2 files changed, 4
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
Use l3init_960m_gfclk as parent of
As clocks might be named differently on multiple platforms, use a generic
name in the driver and allow device tree node to specify the platform
specific clock name.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-omap-usb2.c | 8
1 file changed, 4 insertions(+), 4
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
---
arch/arm/boot/dts/am335x-evm.dts | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Hi,
This patchset adds DT support in rx51-audio. I tested it on my
Nokia N900 and was able to play a wav file using aplay. I have
not tested the whole functionality, but output via speakers,
headphones and the related enable controls seem to work.
Changes since PATCHv1 [0]:
* drop ASoC:
This patch adds support for the Nokia N900's sound
system.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
arch/arm/boot/dts/omap3-n900.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index
This patch adds device tree support to the Nokia N900 audio driver and
adds documentation for the DT binding.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
.../devicetree/bindings/sound/nokia,rx51.txt | 27 +++
sound/soc/omap/rx51.c | 53
Ping ?
On Monday 21 April 2014 15:06:23 Laurent Pinchart wrote:
From: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
Commit 7b2e1277598e4187c9be3e61fd9b0f0423f97986 (ARM: OMAP3: clock:
Back-propagate rate change from cam_mclk to dpll4_m5) enabled clock
rate back-propagation from
Update the driver to get GPIO numbers from the
devm gpiod API instead of requesting hardcoded
GPIO numbers.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 114 ++
1 file changed, 79 insertions(+), 35 deletions(-)
diff
Add more error messages making it easier to identify problems.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 30cfac0..110deca
This is a preparation for DT based booting where the McBSP id
is set to -1 for all McBSP instances.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/omap-mcbsp.c | 5 +++--
sound/soc/omap/omap-mcbsp.h | 2 +-
sound/soc/omap/rx51.c | 2 +-
3 files changed, 5
Add module alias to support driver autoloading.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 1a3f05c..55713d0
This patch converts the rx51 ASoC module to use
devm_snd_soc_register_card.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
This patch adds support for specifying auxiliary codecs and
codec configuration via device tree phandles.
This change adds new fields to snd_soc_aux_dev and snd_soc_codec_conf
and adds support for the changes to SoC core methods.
Signed-off-by: Pavel Machek pa...@ucw.cz
Signed-off-by: Sebastian
On Sun, Apr 06, 2014 at 01:52:03PM +0200, Sebastian Reichel wrote:
This is an RFC patch adding DT support to the si4713 radio
transmitter i2c driver.
ping?
-- Sebastian
signature.asc
Description: Digital signature
Mark the array and the string const by using static const char * const
foo[] instead of static const char* foo[].
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/sound/soc/omap/rx51.c
On 4/28/2014 2:07 PM, yegorsli...@googlemail.com wrote:
From: Yegor Yefremov yegorsli...@googlemail.com
This patch creates unique DMA channels for the second USB
interface, otherwise the second USB interface is not usable
at all.
MUSB_DMA_NUM_CHANNELS is 15, so if you pass any dma-names 15 (
On 4/28/2014 7:28 PM, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
The series will give dtb build errors
Error: arch/arm/boot/dts/am335x-bone-common.dtsi:186.2-15 syntax error
FATAL ERROR: Unable to parse
On 4/28/2014 8:01 PM, Felipe Balbi wrote:
On Mon, Apr 28, 2014 at 09:40:20AM +0530, George Cherian wrote:
CPTS refclk name is hardcoded, which makes it fail in case of DRA7x
Remove the hardcoded clock name for CPTS refclk and get the same from DT.
Signed-off-by: George Cherian
On Mon, Apr 28, 2014 at 09:40:20AM +0530, George Cherian wrote:
CPTS refclk name is hardcoded, which makes it fail in case of DRA7x
Remove the hardcoded clock name for CPTS refclk and get the same from DT.
Signed-off-by: George Cherian george.cher...@ti.com
---
On 04/28/2014 02:17 PM, Stefan Roese wrote:
From: Jarkko Nikula jarkko.nik...@bitmer.com
This codec driver template represents an I2C controlled multichannel audio
codec that has many typical ASoC codec driver features like volume controls,
mixer stages, mux selection, output power control,
l3-dev is not populated, so populate it and use it to print information
relevant to the device instead of using a generic pr_*.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Ujfalusi peter.ujfal...@ti.com
Tested-by: Darren Etheridge
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock
Currently we use __raw_readl and writel in this driver. Considering
there is no specific need for a memory barrier, replacing writel
with endian-neutral writel_relaxed and replacing __raw_readls with
the corresponding endian-neutral readl_relaxed allows us to have a
standard set of register
L3 error may be triggered using Debug interface (example JTAG) or
due to other errors, for example an opcode fetch (due to function
pointer or stack corruption) or a data access (due to some other
failure). NOC registers contain additional information to help aid
debug information.
With this, we
Current interrupt handler does the first level parse to identify the
slave and then handles the slave even identification, reporting and
clearing of event as well. It is hence logical to split the handler
into two where the primary handler just parses the flagmux till it
identifies a slave and the
The logic between handling CUSTOM_ERROR and STANDARD_ERROR is just the
reporting style.
So make it generic, simplify and standardize the reporting with both
master and target information printed to log.
Handle the register address difference for master code for standard
error and custom error as
From: Sricharan R r.sricha...@ti.com
DRA7xx SoC has the same l3-noc interconnect ip (as OMAP4 and OMAP5), but
AM437x SoC has just 2 modules instead of 3 which other SoCs have.
So, stop using direct access of array indices and use of-match data and
simplify implementation to benefit future usage.
* Lee Jones lee.jo...@linaro.org [140428 04:42]:
These settings are based on the Recommended Sleep Sequences for
the Zoom Platform pdf at:
http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
These settings assume most of the regulators are under control of
Linux,
we do not use iclk directly anymore. And, even if we had to, we
should be using pm_runtime APIs to do the same to be completely SoC
independent.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Ujfalusi peter.ujfal...@ti.com
Tested-by:
From: Afzal Mohammed af...@ti.com
Errors that cannot be cleared (determined by reading REGERR register)
are currently handled by masking it. Documentation states that REGERR
Checks which application/debug error sources are active - it does not
indicate that this is interrupt status - masked out
The following V3 of the series is based on v3.15-rc1 + peter's patch series:
patch #1: https://patchwork.kernel.org/patch/3923141/
(drivers: bus: omap_l3: Convert to use devm_kzalloc)
patch #2: https://patchwork.kernel.org/patch/3923061/
(drivers: bus: omap_l3:
just simplify derefencing that is equivalent.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Ujfalusi peter.ujfal...@ti.com
Tested-by: Darren Etheridge detheri...@ti.com
---
V3: no change
drivers/bus/omap_l3_noc.c |2 +-
1 file
This allows us to encompass target information and flag mux offset that
points to the target information into a singular structure. This saves
us the need to look up two different arrays indexed by module ID for
information.
This allows us to reduce the static target information allocation to
From: Rajendra Nayak rna...@ti.com
On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used
to indicate the source of errors are not continous. Have a way in the
driver to catch these and WARN the user of the flag mux input thats
either undocumented or wrong.
In the similar vein,
* Lee Jones lee.jo...@linaro.org [140428 04:47]:
With the recommended twl4030 configuration added, we can now add
board specific changes as modifications to the recommended
configuration.
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee
This is an embarrassing patch :(.
Texas Corporation does not make OMAP. Texas Instruments Inc does.
For that matter I dont seem to be able to find a Texas Corporation on
the internet either.
While at it, update coverage to the current year and update the template
to remove redundant information
From: Afzal Mohammed af...@ti.com
Add AM4372 information to handle L3 error.
AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.
NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by
Move the L3 master structure out of the static definition to enable
reuse for other SoCs.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Ujfalusi peter.ujfal...@ti.com
Tested-by: Darren Etheridge detheri...@ti.com
---
V3: no change
Currently the target instance information is organized indexed by bit
field offset into multiple arrays.
1. We currently have offsets specific to each target associated with each
clock domains are in seperate arrays:
l3_targ_inst_clk1
l3_targ_inst_clk2
l3_targ_inst_clk3
2. Then they are
From: Rajendra Nayak rna...@ti.com
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
0x4400 0x100 is clk1 and clk2 is the sub clock domain
0x4500 0x1000 is clk3
Add all the
From: Sricharan R r.sricha...@ti.com
Since omap_l3_noc driver is now being used for OMAP5 and reusable with
DRA7 and AM437x, using omap4 specific naming is misleading.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar
On Mon, 28 Apr 2014, Tony Lindgren wrote:
* Lee Jones lee.jo...@linaro.org [140428 04:42]:
These settings are based on the Recommended Sleep Sequences for
the Zoom Platform pdf at:
http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
These settings assume most
Today we get error such as
L3 Custom Error: MASTER MPU TARGET L4PER2
But since the actual instruction triggerring the error Vs the point
at which we report error may not be aligned, it makes sense to try
and provide additional information - example the type of operation
that was attempted to
As per Documentation (OMAP4+), then masterid is infact encoded as
follows:
L3_TARG_STDERRLOG_MSTADDR[7:0] STDERRLOG_MSTADDR stores the NTTP
master address. The master address is the concatenation of Prefix
Initiator ConnID. It is defined on 8 bits. The 6 MSBs are used to
distinguish the different
On Mon, Apr 28, 2014 at 04:49:23PM -0400, Zhuang Jin Can wrote:
Adds a debugfs file snapshot to dump dwc3 requests, trbs and events.
you need to explain what are you trying to provide to our users here.
What problem are you trying to solve ?
As ep0 requests are more complex than others. It's
Hi,
On Mon, Apr 28, 2014 at 05:01:23PM +0300, Roger Quadros wrote:
As clocks might be named differently on multiple platforms, use a generic
name in the driver and allow device tree node to specify the platform
specific clock name.
Signed-off-by: Roger Quadros rog...@ti.com
---
On Mon, Apr 28, 2014 at 05:01:24PM +0300, Roger Quadros wrote:
The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Felipe Balbi
On Mon, Apr 28, 2014 at 05:01:25PM +0300, Roger Quadros wrote:
Add wkupclk and refclk information to DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
1 file changed,
On Mon, Apr 28, 2014 at 05:01:26PM +0300, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
On Mon, Apr 28, 2014 at 05:01:27PM +0300, Roger Quadros wrote:
Add USB pinmux information and USB modes
for the USB controllers.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 24
1 file
* Lee Jones lee.jo...@linaro.org [140428 04:37]:
The twl4030 PMIC needs to be configured properly for things like
warm reset and deeper idle states so the PMIC manages the regulators
properly based on the hardware triggers from the SoC.
For example, when rebooting an OMAP3530 at 125
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