Hi Kishon,
Could you please pick the first 2 patches in this series for phy-next?
They are independent of the rest. Thanks.
cheers,
-roger
On 05/05/2014 12:54 PM, Roger Quadros wrote:
Hi,
This series enables the 2 USB ports on the DRA7-evm.
NOTE: USB1 port is hard coded to work in
On 2 May 2014 16:35, Geert Uytterhoeven ge...@linux-m68k.org wrote:
Hi Ulf,
On Fri, May 2, 2014 at 10:56 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
+static int of_clk_pm_runtime_suspend(struct device *dev)
+{
+ int ret;
+
+ ret = pm_generic_runtime_suspend(dev);
+ if
On 2 May 2014 16:58, Geert Uytterhoeven ge...@linux-m68k.org wrote:
Hi Ulf, Tomasz,
On Fri, May 2, 2014 at 10:13 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
+static int of_clk_register(struct device *dev, struct clk *clk)
+{
+ int error;
+
+ if (!dev-pm_domain) {
+
Hi Tony,
On 04/23/2014 08:30 PM, Roger Quadros wrote:
Hi Tony,
These are the pending HWMOD and DTS patches to get SATA working
on OMAP5-uevm and DRA7-evm. Please queue them for -next. Thanks.
gentle reminder. Thanks.
cheers,
-roger
---
Balaji T K (2):
ARM: dts: omap5: add sata node
When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be
put in bypass mode.
This will fix HPPLL use on boards with 19.2MHz mclk.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/mfd/twl6040.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
On 05/05/2014 12:54 PM, Roger Quadros wrote:
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812.
This codec driver template represents an I2C controlled multichannel audio
codec that has many typical ASoC codec driver features like volume controls,
mixer stages, mux selection, output power control, in-codec audio routings,
codec bias management and DAI link configuration.
This driver is
HA DSP card which features a HA DSP audio codec is intended to be connected
to TAO-3530 (or BeagleBoard) using McBSP3 for digital audio and I2C bus for
codec control. A GPIO signal from CPU to codec is used to request clock
signals active.
This machine driver has a special feature to support
Hello Tony,
From: Gupta, Pekon
*changes v2 - v3*
rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
:master
merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series
Can you please see if this series can be taken in for 3.16 ? As this series
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Depends on sricharan's irq crossbar.
arch/arm/boot/dts/dra7-evm.dts | 80
arch/arm/boot/dts/dra7.dtsi| 14 +++
2 files
Felipe
Thanks for the comments
On 05/05/2014 04:33 PM, Felipe Balbi wrote:
Hi,
On Mon, May 05, 2014 at 03:09:22PM -0500, Dan Murphy wrote:
The TI SoC reset controller support utilizes the
reset controller framework to give device drivers or
function drivers a common set of APIs to call to
Use MATRIX_KEY macro from dt-bindings/input/input.h
to make the keyboard matrix human readable.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
arch/arm/boot/dts/omap3-n900.dts | 103 ---
1 file changed, 52 insertions(+), 51 deletions(-)
diff --git
Tony
Thanks for the comments
On 05/05/2014 05:01 PM, Tony Lindgren wrote:
* Dan Murphy dmur...@ti.com [140505 13:10]:
+
+Required parent properties:
+- compatible : Should be one of,
+ti,omap4-prm for OMAP4 PRM instances
+ti,omap5-prm for OMAP5 PRM instances
+
Hi,
Changes since v1:
- binding documentation and driver has been separated based on Nishanth Menon's
comment
v1 of the driver can be found:
https://lkml.org/lkml/2014/4/3/104
Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual
Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual device the provided clocks can be:
CLK32K_KG and CLK32K_KGAUDIO
or only one:
CLK32K_KG (TPS659039 for example)
Use separate compatible flags for the two 32K clock.
A system which
Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual device the provided clocks can be:
CLK32K_KG and CLK32K_KGAUDIO
or only one:
CLK32K_KG (TPS659039 for example)
Use separate compatible flags for the two 32K clock.
A system which
On 16:24-20140506, Peter Ujfalusi wrote:
Hi,
Changes since v1:
- binding documentation and driver has been separated based on Nishanth
Menon's
comment
v1 of the driver can be found:
https://lkml.org/lkml/2014/4/3/104
Palmas class of devices can provide 32K clock(s) to be used
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock. The Documentation
for divider clock can be found at ../clock/ti/divider.txt
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git
Added *resets* and *reset-names* properies for PCIe dt node.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 23
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt |2 ++
drivers/pci/host/pci-dra7xx.c
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Jingoo
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Rob Herring robh...@kernel.org
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed,
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |8
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Kishon Vijay
Mike,
On 04/24/2014 06:03 PM, Tero Kristo wrote:
On 04/24/2014 12:11 PM, Peter Ujfalusi wrote:
Mike, Tero,
On 04/03/2014 09:29 AM, Peter Ujfalusi wrote:
On 04/02/2014 05:12 PM, Tero Kristo wrote:
On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
ABE DPLL frequency need to be lowered from
On 05/06/2014 08:34 AM, Kishon Vijay Abraham I wrote:
Added *resets* and *reset-names* properies for PCIe dt node.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham
APLL used by PCIE phy can either use external clock as input or the clock
from DPLL. Added support for the APLL to use external clock as input here.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On 05/06/2014 08:34 AM, Kishon Vijay Abraham I wrote:
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
Export an API to be called by PIPE3 PHY to enable external clock for
PCIE PHY. Added a new compatible for PCIE in omap-control in order to
enable it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |9 ++--
This patch series adds support for PCIe in DRA7xx including drivers and dt
data. PCIe in DRA7xx uses desingware IP and hence this re-uses the
pcie desingware driver (pcie-designware.c) by Jingoo.
The last couple of patches are marked as *TEMP* since the TI reset driver [1]
is not yet merged and
On Tuesday, May 06, 2014 at 03:33:51 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
[...]
+#define to_dra7xx_pcie(x)container_of((x), struct dra7xx_pcie, pp)
+
+static inline
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only
Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt numbers with its fixed crossbar input lines.
Cc: Benoit
There is a IRQ crossbar device in the soc, which maps the
irq requests from the peripherals to the mpu interrupt
controller's inputs. The gic provides the support for such
IPs in the form of routable-irqs. So adding the property
here to gic node.
Cc: Benoit Cousson bcous...@baylibre.com
Cc:
On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller can see only
28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example,
On Tuesday 06 May 2014 19:03:51 Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han
* Archit Taneja arc...@ti.com [140505 22:24]:
Hi,
On Monday 21 April 2014 08:40 PM, Tony Lindgren wrote:
* Archit Taneja arc...@ti.com [140420 22:16]:
Hi,
On Friday 18 April 2014 10:48 PM, Tony Lindgren wrote:
* Archit Taneja arc...@ti.com [140416 06:20]:
Add DT node for the ctrl-core
* Sricharan R r.sricha...@ti.com [140506 06:58]:
Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt
* Alex Shi alex@linaro.org [140325 03:54]:
From: Eduardo Valentin eduardo.valen...@ti.com
OMAP4430 devices can reach high temperatures and thus
needs to have cpufreq-cooling on systems running on it.
This patch adds the required cooling device properties
so that cpufreq-cpu0 driver
Hi,
[ I had to manually rewrap your email which came with long lines, please
have a read on Documentation/email-clients.txt ]
On Tue, May 06, 2014 at 08:14:04AM -0500, Dan Murphy wrote:
The TI SoC reset controller support utilizes the
reset controller framework to give device drivers or
* Pekon Gupta pe...@ti.com [140422 00:34]:
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -9,6 +9,7 @@
#include am33xx.dtsi
#include am335x-bone-common.dtsi
+#include am335x-bone-memory-cape.dts
ldo3_reg {
regulator-min-microvolt =
* Pekon Gupta pe...@ti.com [140422 00:34]:
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
Please use the minimum size 16MB GPMC range here, NAND only
has few registers addressable unlike
* Pekon Gupta pe...@ti.com [140422 02:03]:
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0x0800 0x1000;
Here too please use the minimum 16MB GPMC partition for NAND.
+ nand@0,0 {
+ reg = 0 0 0;
* Pekon Gupta pe...@ti.com [140422 02:03]:
MTD NAND partition for file-system should start at offset=0xA0
Applying to omap-for-v3.16/fixes-not-urgent with hex changed to use
lower case like we tend to do.
Hmm, how come you did not fold this into the original patch to the
mainline kernel as
* Darren Etheridge detheri...@ti.com [140422 13:39]:
Add the necessary nodes to enable the LCD controller and the
LCD panel that is attached to the Texas Instruments AM335x
EVMSK platform. Also setup the necessary pin mux within the
DT file to drive the LCD connector and add the correct
* sourav sourav.pod...@ti.com [140506 01:23]:
Hi Tony,
On Monday 28 April 2014 07:12 PM, Sourav Poddar wrote:
This patch adds qspi nodes for am43xx SOC devices.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
This patch has been posted many times before.
If this patch looks OK, can it
On Mon, Apr 28, 2014 at 10:58:29AM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 10:58:32AM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 05:54:33PM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 10:58:31AM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 05:54:34PM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 05:54:32PM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
(acked wrong version previously, sorry)
Acked-by: Felipe
On Mon, Apr 28, 2014 at 10:58:30AM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Acked-by: Felipe Balbi ba...@ti.com
---
On Mon, Apr 28, 2014 at 05:54:35PM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
Cc: Enric Balletbo i Serra eballe...@iseebcn.com
* Rajendra Nayak rna...@ti.com [140429 04:22]:
On Tuesday 29 April 2014 04:48 PM, Arnd Bergmann wrote:
On Tuesday 29 April 2014 16:35:13 Rajendra Nayak wrote:
@@ -393,7 +395,12 @@ IS_OMAP_TYPE(3430, 0x3430)
#if defined(CONFIG_SOC_DRA7XX)
#undef soc_is_dra7xx
+#undef soc_is_dra74x
On Tue, May 06, 2014 at 07:03:51PM +0530, Kishon Vijay Abraham I wrote:
+Example:
+pcie@5100 {
+ compatible = ti,dra7xx-pcie;
+ reg = 0x51002000 0x14c, 0x5100 0x2000;
+ reg-names = ti_conf, rc_dbics;
+ interrupts = 0 232 0x4, 0 233 0x4;
+ #address-cells = 3;
+
* Felipe Balbi ba...@ti.com [140506 09:19]:
On Mon, Apr 28, 2014 at 05:54:32PM -0300, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez gu...@vanguardiasur.com.ar
(acked
* Roger Quadros rog...@ti.com [140430 05:43]:
Hi Benoit Tony,
These patches add I2C touch screen support for am43x-epos-evm
and am437x-gp-evm.
Relevant driver side changes are here.
http://thread.gmane.org/gmane.linux.kernel.input/35803
Please queue this for -next (3.16). Thanks.
* Dave Gerlach d-gerl...@ti.com [140505 12:59]:
The am335x-evmsk and am437x-gp-evm both have a gpio controlled regulator
for DDR3 VTT voltage. This is configured by boot loader and previously
just left at that but it is better to define a fixed regulator to control
the gpio so that the kernel
* Sourav Poddar sourav.pod...@ti.com [140506 04:08]:
These add device tree entry for qspi controller driver on dra7-evm.
Thanks applying into omap-for-v3.16/dt.
Tony
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More
* Sebastian Reichel s...@kernel.org [140506 06:15]:
Use MATRIX_KEY macro from dt-bindings/input/input.h
to make the keyboard matrix human readable.
Thanks applying into omap-for-v3.16/dt.
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to
* Peter Robinson pbrobin...@gmail.com [140503 17:12]:
With ARCH_OMAP2PLUS being separated out into OMAP2/3/4/5 etc all the TI device
tree blobs are built no matter the combination of SoCs that are enabled. This
often causes a bunch of irrelevant .dts to be built on a multi platform
kernel,
1On 6 May 2014 02:15, Tony Lindgren t...@atomide.com wrote:
* Joachim Eastwood manab...@gmail.com [140501 12:08]:
Hello,
This patch set adds support for Variscite OM44 series of system on modules
and boards.
There weren't many comments on v1 of this patch set so I hope this can make
it
Hi,
I'm trying to backport a display driver for an RFBI panel to 2.6.32,
but the dss_pwrdm is complaining about not entering target state:
root@02AA01AB381207S7# cat /sys/kernel/debug/pm_debug/count | grep dss
dss_pwrdm (ON),OFF:0,RET:11,INA:0,ON:12
dss_clkdm-dss_pwrdm (0)
On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one
On 05/06/2014 02:40 PM, Felipe Balbi wrote:
On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The
* Andrew LeCain alec...@google.com [140506 12:10]:
Hi,
I'm trying to backport a display driver for an RFBI panel to 2.6.32,
but the dss_pwrdm is complaining about not entering target state:
Backport from which kernel? The RFBI got removed recently because
of the move of the panels. Probably
Nishanth Menon n...@ti.com wrote on Tue [2014-May-06 14:46:10 -0500]:
On 05/06/2014 02:40 PM, Felipe Balbi wrote:
On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests
Darren Etheridge detheri...@ti.com wrote on Tue [2014-May-06 14:58:04 -0500]:
Nishanth Menon n...@ti.com wrote on Tue [2014-May-06 14:46:10 -0500]:
On 05/06/2014 02:40 PM, Felipe Balbi wrote:
On Tue, May 06, 2014 at 07:26:17PM +0530, Sricharan R wrote:
This adds the irq crossbar device
Sricharan R r.sricha...@ti.com wrote on Tue [2014-May-06 19:26:16 +0530]:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the subsystems are not needed at the same
time, so they have to
On 16:00-20140425, Felipe Balbi wrote:
On Fri, Apr 25, 2014 at 03:58:10PM -0500, Nishanth Menon wrote:
On 04/16/2014 11:35 AM, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [140416 08:18]:
TRM says we *must* write 1 to each bit we're handling
in order to clear the IRQ status and
On Wed, May 07, 2014 at 01:24:23PM +0900, Jingoo Han wrote:
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han jg1@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
---
drivers/i2c/busses/i2c-omap.c |
On Tuesday 06 May 2014 09:58 PM, Tony Lindgren wrote:
* Rajendra Nayak rna...@ti.com [140429 04:22]:
On Tuesday 29 April 2014 04:48 PM, Arnd Bergmann wrote:
On Tuesday 29 April 2014 16:35:13 Rajendra Nayak wrote:
@@ -393,7 +395,12 @@ IS_OMAP_TYPE(3430, 0x3430)
#if
On Wednesday 07 May 2014 03:15 AM, Darren Etheridge wrote:
Sricharan R r.sricha...@ti.com wrote on Tue [2014-May-06 19:26:16 +0530]:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the interrupt
requests lines from the
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