Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Kishon Vijay Abraham I
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
Added *resets* and *reset-names* properies for PCIe dt node.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
drivers/pci/host/pci-dra7xx.c
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc:
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed,
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock. The Documentation
for divider clock can be found at ../clock/ti/divider.txt
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Keerthy j-keer...@ti.com
This patch series adds support for PCIe in DRA7xx including drivers and dt
data. PCIe in DRA7xx uses desingware IP and hence this re-uses the
pcie desingware driver (pcie-designware.c) by Jingoo.
The last couple of patches are marked as *TEMP* since the TI reset driver [1]
is not yet merged and
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros
On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc:
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-omap@vger.kernel.org; linux-
p...@vger.kernel.org;
On Mon, May 19, 2014 at 09:18:15AM -0700, Tony Lindgren wrote:
* Dmitry Torokhov dmitry.torok...@gmail.com [140518 22:38]:
On Sat, May 17, 2014 at 11:24:10PM +0200, Joachim Eastwood wrote:
This has been unused since omap4 board files went away.
Signed-off-by: Joachim Eastwood
Hi Balaji, Tony, Ulf, all
v14
- drop all ifdef/endif introduced by v13
-- rely on pinctrl_lookup_state to prevent ifdef CONFIG_PM
-- benefit: all code is compile tested no matter the configuration
-- drawback: require wake_irq/pinctrl configuration even when
runtime suspend is not configured
-
On multicores, an sdio irq handler could be running in parallel to
runtime suspend. In the worst case it could be waiting for the spinlock
held by the runtime suspend. When runtime suspend is complete and the
functional clock (fclk) turned off, the irq handler will continue and
cause a SIGBUS on
These are predefined states of the driver model. When not present,
as if not set in the device tree, they become no-ops.
Explicitly selecting the default state is not needed since the
device core layer sets pin mux to default state before probe.
This is not the simplest implementation, on AM335x
There have been various patches floating around for enabling
the SDIO IRQ for hsmmc, but none of them ever got merged.
Probably the reason for not merging the SDIO interrupt patches
has been the lack of wake-up path for SDIO on some omaps that
has also needed remuxing the SDIO DAT1 line to a GPIO
From: Balaji T K balaj...@ti.com
To detect sdio irqs properly without spurious events,
OMAP4 needs IWE in CON and CTPL, CLKEXTFREE in HCTL to be set
Tested-by: Andreas Fenkart afenk...@gmail.com
Signed-off-by: Balaji T K balaj...@ti.com
diff --git a/drivers/mmc/host/omap_hsmmc.c
Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current
state of data lines, incl. SDIO IRQ pending
Signed-off-by: Andreas Fenkart afenk...@gmail.com
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 129569d..332d3d2 100644
---
The am335x can't detect pending cirq in PM runtime suspend.
This patch reconfigures dat1 as a GPIO before going to suspend.
SDIO interrupts are detected with the GPIO, the GPIO will only wake
the module from suspend, SDIO irq detection will still happen through the
IP block.
Idea of remuxing the
On 5/29/2014 12:23 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
SmartCard controller uses this interface to communicate with
SmartCard via PHY
Some SmartCard PHY has multiple slots for cards.
This inerface also enables controller to communicate
with one or
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:14PM +0530, Satish Patel wrote:
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave device.
The driver also exposes the phy interface
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private data structure
+ * @set_config: called to set phy's configuration
+ *
Hi,
On Thursday 29 May 2014 12:41 PM, Mohit KUMAR DCG wrote:
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org;
Hi,
On Thursday 29 May 2014 12:18 PM, Jingoo Han wrote:
On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
On Thursday 29 May 2014 01:58 PM, Andreas Fenkart wrote:
Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current
state of data lines, incl. SDIO IRQ pending
Signed-off-by: Andreas Fenkart afenk...@gmail.com
Thanks Andreas for fixing compilation with !CONFIG_PM[_RUNTIME],
On Thursday 29 May 2014 01:58 PM, Andreas Fenkart wrote:
The am335x can't detect pending cirq in PM runtime suspend.
This patch reconfigures dat1 as a GPIO before going to suspend.
SDIO interrupts are detected with the GPIO, the GPIO will only wake
the module from suspend, SDIO irq detection
On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote:
On 5/29/2014 12:23 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
SmartCard controller uses this interface to communicate with
SmartCard via PHY
Some SmartCard PHY has multiple
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote:
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence
On Thu, May 29, 2014 at 02:26:55PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private
On Thu, May 29, 2014 at 08:47:31AM -0500, Rob Herring wrote:
On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote:
On 5/29/2014 12:23 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
SmartCard controller uses this interface to
On Thu, May 29, 2014 at 02:07:59PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:14PM +0530, Satish Patel wrote:
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave
On Thu, May 29, 2014 at 03:35:37PM +0530, Satish Patel wrote:
+enum usim_card_mode {
+ USIM_CARD_MODE_ASYNC = 0, /* asynchronous mode */
+ USIM_CARD_MODE_SYNC_TYPE1, /* synchronous mode: Type 1 */
+ USIM_CARD_MODE_SYNC_TYPE2, /* synchronous mode: Type 2 */
+
On May 29, 2014, at 10:18 AM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote:
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
The configuration address space has so far been specified in *ranges*,
however it should
On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote:
Just because the kernel doesn’t handle this is NO reason to change
the way the DT works.
The OF specs do not specify how to process a config type ranges entry,
and we all mutually agreed that the only sane interpretation for such
a
On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware
On May 29, 2014, at 11:30 AM, Jason Gunthorpe jguntho...@obsidianresearch.com
wrote:
On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote:
Just because the kernel doesn’t handle this is NO reason to change
the way the DT works.
The OF specs do not specify how to process a config
On Thu, May 29, 2014 at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland
On Thu, May 29, 2014 at 06:52:14PM +0100, Rob Herring wrote:
On Thu, May 29, 2014 at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
On Fri 2014-05-16 14:12:31, Tony Lindgren wrote:
* Paul Bolle pebo...@tiscali.nl [140515 12:42]:
A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related
Kconfig symbol was never part of the tree. So we can remove some dead
code.
Thanks applying into omap-for-v3.16/board.
Add support for DRA72x device DIEID. Currently these devices are
reported as DRA75/74 family of processors.
Signed-off-by: Nishanth Menon n...@ti.com
---
(test using linux-next next-20140529 tag):
before: http://slexy.org/raw/s21Yb8sOhy
after: http://slexy.org/raw/s20Nx96NrY
Applies
* Pavel Machek pa...@ucw.cz [140529 12:03]:
On Fri 2014-05-16 14:12:31, Tony Lindgren wrote:
* Paul Bolle pebo...@tiscali.nl [140515 12:42]:
A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related
Kconfig symbol was never part of the tree. So we can remove some dead
On Thu 2014-05-29 12:17:39, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [140529 12:03]:
On Fri 2014-05-16 14:12:31, Tony Lindgren wrote:
* Paul Bolle pebo...@tiscali.nl [140515 12:42]:
A check for CONFIG_SX1_OLD_FLASH was added in v2.6.24. But the related
Kconfig symbol was
On Wed, May 28, 2014 at 10:58:39AM -0700, Tony Lindgren wrote:
The following changes since commit d712ff63b18309c939396f593510fbcccbafb9e4:
ARM: dts: Enable mcpdm and mcbsp1 on DuoVero (2014-05-19 17:20:31 -0700)
are available in the git repository at:
Hello,
My name is Mr. Richard Sun from Hong Kong. I want you to be my partner in a
business project. Contact me back via my private e-mail address for more
details;
richad.t...@yahoo.com.hk
Thank you.
Mr. Richard Sun.
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
On 5/29/2014 7:17 PM, Rob Herring wrote:
On Thu, May 29, 2014 at 3:34 AM, Satish Patel satish.pa...@ti.com wrote:
On 5/29/2014 12:23 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
SmartCard controller uses this interface to communicate with
SmartCard
On 5/29/2014 9:23 PM, Greg Kroah-Hartman wrote:
On Thu, May 29, 2014 at 03:35:37PM +0530, Satish Patel wrote:
+enum usim_card_mode {
+ USIM_CARD_MODE_ASYNC = 0, /* asynchronous mode */
+ USIM_CARD_MODE_SYNC_TYPE1, /* synchronous mode: Type 1 */
+
On 5/29/2014 9:21 PM, Greg KH wrote:
On Thu, May 29, 2014 at 02:26:55PM +0530, Satish Patel wrote:
On 5/29/2014 12:14 AM, Greg KH wrote:
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ *
Hi,
On Thursday 29 May 2014 10:02 PM, Murali Karicheri wrote:
On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used
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