[PATCH v7 RESEND] ARM: omap: edma: add suspend suspend/resume hooks
From: Daniel Mack zon...@gmail.com
This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.
All information can be reconstructed by already known runtime
information.
As we now use some functions that were previously only used from __init
context, annotations had to be dropped.
[n...@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Daniel Mack zon...@gmail.com
Tested-by: Joel Fernandes jo...@ti.com
Acked-by: Joel Fernandes jo...@ti.com
[d-gerl...@ti.com: updated to remove queue_tc_mapping use]
Signed-off-by: Dave Gerlach d-gerl...@ti.com
---
Needed for am335x suspend, but never got picked up. Previously
sent here: http://marc.info/?l=linux-arm-kernelm=138556067416051w=2
arch/arm/common/edma.c | 86 --
1 file changed, 84 insertions(+), 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 8809917..ece1e3d 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -244,6 +244,8 @@ struct edma {
/* list of channels with no even trigger; terminated by -1 */
const s8*noevent;
+ struct edma_soc_info *info;
+
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -295,7 +297,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
~(0x7 bit), queue_no bit);
}
-static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+static void assign_priority_to_queue(unsigned ctlr, int queue_no,
int priority)
{
int bit = queue_no * 4;
@@ -314,7 +316,7 @@ static void __init assign_priority_to_queue(unsigned ctlr,
int queue_no,
* included in that particular EDMA variant (Eg : dm646x)
*
*/
-static void __init map_dmach_param(unsigned ctlr)
+static void map_dmach_param(unsigned ctlr)
{
int i;
for (i = 0; i EDMA_MAX_DMACH; i++)
@@ -1791,15 +1793,95 @@ static int edma_probe(struct platform_device *pdev)
edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
edma_write_array(j, EDMA_QRAE, i, 0x0);
}
+ edma_cc[j]-info = info[j];
arch_num_cc++;
}
return 0;
}
+static int edma_pm_suspend(struct device *dev)
+{
+ int j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *ecc = edma_cc[j];
+
+ disable_irq(ecc-irq_res_start);
+ disable_irq(ecc-irq_res_end);
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int edma_pm_resume(struct device *dev)
+{
+ int i, j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *cc = edma_cc[j];
+
+ s8 (*queue_priority_mapping)[2];
+
+ queue_priority_mapping = cc-info-queue_priority_mapping;
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(j,
+queue_priority_mapping[i][0],
+queue_priority_mapping[i][1]);
+
+ /*
+* Map the channel to param entry if channel mapping logic
+* exist
+*/
+ if (edma_read(j, EDMA_CCCFG) CHMAP_EXIST)
+ map_dmach_param(j);
+
+ for (i = 0; i cc-num_channels; i++) {
+ if (test_bit(i, cc-edma_inuse)) {
+ /* ensure access through shadow region 0 */
+ edma_or_array2(j, EDMA_DRAE, 0, i 5,
+ BIT(i 0x1f));
+
+ setup_dma_interrupt(i,
+ cc-intr_data[i].callback,
+ cc-intr_data[i].data);
+ }
+ }
+
+ enable_irq(cc-irq_res_start);
+ enable_irq(cc-irq_res_end);
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops edma_pm_ops = {
+ .suspend_late = edma_pm_suspend,
+ .resume_early = edma_pm_resume,
+};
+
static struct platform_driver edma_driver = {
.driver = {
.name = edma,
+ .pm = edma_pm_ops,
Re: [PATCH] usb: phy: twl4030-usb: Fix lost interrupts after ID pin goes down
Hi, On Thu, Aug 21, 2014 at 7:48 PM, Tony Lindgren t...@atomide.com wrote: Commit 249751f22380 (usb: phy: twl4030-usb: poll for ID disconnect) added twl4030_id_workaround_work() to deal with lost interrupts after ID pin goes down. However, this currently only works for the insertion. The PHY interrupts are not working after disconnecting an USB-A device from the board, and the deeper idle states for omap are blocked as the USB controller stays busy. The issue can be solved by calling delayed work from twl4030_usb_irq() when ID pin is down and the PHY is not asleep like we already do in twl4030_id_workaround_work(). The way it is supposed to work is that after plugging in the cable twl4030_phy_power_on() sees ID_GROUND and kicks off id_workaround_work every second. When cable is unplugged, twl4030_id_workaround_work() sees changes in STS_HW_CONDITIONS register and triggers events. Doesn't that work for you, why do you need to trigger it from twl4030_usb_irq() too? But as both twl4030_usb_irq() and twl4030_id_workaround_work() already do pretty much the same thing, let's call twl4030_usb_irq() from twl4030_id_workaround_work() instead of adding some more duplicate code. The difference is the sysfs_notify() call, so now every time id_workaround_work triggers (around once per second while the cable is plugged) userspace will now get useless uevent. Haven't actually checked if it really happens though, so I might be wrong. -- Gražvydas -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
No need to invoke callback when the clkdm pointer is NULL. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/powerdomain.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index faebd5f..f391948 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, return -EINVAL; for (i = 0; i PWRDM_MAX_CLKDMS !ret; i++) - ret = (*fn)(pwrdm, pwrdm-pwrdm_clkdms[i]); + if (pwrdm-pwrdm_clkdms[i]) + ret = (*fn)(pwrdm, pwrdm-pwrdm_clkdms[i]); return ret; } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/7] ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate
DRA7 supports only CSWR for CPU, MPU power domains. Core power domain
supports upto INA.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.h |1 +
arch/arm/mach-omap2/powerdomains7xx_data.c | 14 +++---
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index f472711..a754c82 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -39,6 +39,7 @@
#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
+#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
/*
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c
b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 48151d1..287a203 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = {
.name = core_pwrdm,
.prcm_offs= DRA7XX_PRM_CORE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
- .pwrsts = PWRSTS_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts = PWRSTS_INA_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
@@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = {
.name = cpu0_pwrdm,
.prcm_offs= DRA7XX_MPU_PRCM_PRM_C0_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = {
.name = cpu1_pwrdm,
.prcm_offs= DRA7XX_MPU_PRCM_PRM_C1_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = {
.prcm_offs= DRA7XX_PRM_MPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
--
1.7.9.5
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[PATCH 2/7] ARM: OMAP5: powerdomain data: fix powerdomain powerstate
Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomains54xx_data.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c
b/arch/arm/mach-omap2/powerdomains54xx_data.c
index ce1d752..60d7ed8 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = {
.prcm_offs= OMAP54XX_PRM_CORE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
@@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = {
.voltdm = { .name = mpu },
.prcm_offs= OMAP54XX_PRCM_MPU_PRM_C0_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = {
.voltdm = { .name = mpu },
.prcm_offs= OMAP54XX_PRCM_MPU_PRM_C1_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = {
.prcm_offs= OMAP54XX_PRM_MPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .pwrsts_logic_ret = PWRSTS_RET,
.banks= 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
--
1.7.9.5
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[PATCH 5/7] ARM: OMAP4+: PM: Make logic state programmable
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/pm44xx.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 0dda6cf..b377b03 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -29,6 +29,7 @@ u16 pm44xx_errata;
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
+ u32 next_logic_state;
#ifdef CONFIG_SUSPEND
u32 saved_state;
u32 saved_logic_state;
@@ -54,7 +55,7 @@ static int omap4_pm_suspend(void)
/* Set targeted power domain states by suspend */
list_for_each_entry(pwrst, pwrst_list, node) {
omap_set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
- pwrdm_set_logic_retst(pwrst-pwrdm, PWRDM_POWER_OFF);
+ pwrdm_set_logic_retst(pwrst-pwrdm, pwrst-next_logic_state);
}
/*
@@ -121,6 +122,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *unused)
pwrst-pwrdm = pwrdm;
pwrst-next_state = PWRDM_POWER_RET;
+ pwrst-next_logic_state = PWRDM_POWER_OFF;
+
list_add(pwrst-node, pwrst_list);
return omap_set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
--
1.7.9.5
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[PATCH 7/7] ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
Not all SoCs support OFF mode - for example DRA74/72. So, use valid power state during CPU hotplug. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/omap-mpuss-lowpower.c |4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 4001325..e9cdacf 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -298,6 +298,10 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO; + /* Use the achievable power state for the domain */ + power_state = pwrdm_get_valid_lp_state(pm_info-pwrdm, + false, power_state); + if (power_state == PWRDM_POWER_OFF) cpu_state = 1; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/7] ARM: OMAP4+: PM: use only valid low power state for suspend
We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/pm44xx.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index b377b03..0bfce38 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -121,8 +121,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) return -ENOMEM; pwrst-pwrdm = pwrdm; - pwrst-next_state = PWRDM_POWER_RET; - pwrst-next_logic_state = PWRDM_POWER_OFF; + pwrst-next_state = pwrdm_get_valid_lp_state(pwrdm, false, +PWRDM_POWER_RET); + pwrst-next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true, + PWRDM_POWER_OFF); list_add(pwrst-node, pwrst_list); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/7] ARM: OMAP4+: powerdomain fixes
Hi, The following series are various fixes and improvements for powerdomain support in OMAP4+. This is part 1/6 series which eventually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7 Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/powerdomain-fixes git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/powerdomain-fixes An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Nishanth Menon (7): ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate ARM: OMAP5: powerdomain data: fix powerdomain powerstate ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain ARM: OMAP4+: PM: Make logic state programmable ARM: OMAP4+: PM: use only valid low power state for suspend ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug arch/arm/mach-omap2/omap-mpuss-lowpower.c |4 ++ arch/arm/mach-omap2/pm44xx.c|9 +++- arch/arm/mach-omap2/powerdomain.c | 76 ++- arch/arm/mach-omap2/powerdomain.h |4 ++ arch/arm/mach-omap2/powerdomains54xx_data.c | 12 ++--- arch/arm/mach-omap2/powerdomains7xx_data.c | 14 ++--- 6 files changed, 103 insertions(+), 16 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/7] ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.
So, provide a function to easily query valid low power state that the
power domain is allowed to go to.
Based on work originally done by Jean Pihet j-pi...@ti.com
https://patchwork.kernel.org/patch/1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.
Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 73 +
arch/arm/mach-omap2/powerdomain.h |3 ++
2 files changed, 76 insertions(+)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index f391948..831a2bc 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1081,6 +1081,79 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
}
/**
+ * pwrdm_get_valid_lp_state() - Find best match deep power state
+ * @pwrdm: power domain for which we want to find best match
+ * @is_logic_state: Are we looking for logic state match here? Should
+ * be one of PWRDM_xxx macro values
+ * @req_state: requested power state
+ *
+ * Returns: closest match for requested power state. default fallback
+ * is RET for logic state and ON for power state.
+ *
+ * This does a search from the power domain data looking for the
+ * closest valid power domain state that the hardware can achieve.
+ * PRCM definitions for PWRSTCTRL allows us to program whatever
+ * configuration we'd like, and PRCM will actually attempt such
+ * a transition, however if the powerdomain does not actually support it,
+ * we endup with a hung system. The valid power domain states are already
+ * available in our powerdomain data files. So this function tries to do
+ * the following:
+ * a) find if we have an exact match to the request - no issues.
+ * b) else find if a deeper power state is possible.
+ * c) failing which, it tries to find closest higher power state for the
+ * request.
+ */
+u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
+ bool is_logic_state, u8 req_state)
+{
+ u8 pwrdm_states = is_logic_state ? pwrdm-pwrsts_logic_ret :
+ pwrdm-pwrsts;
+ /* For logic, ret is highest and others, ON is highest */
+ u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON;
+ u8 new_pwrst;
+ bool found;
+
+ /* If it is already supported, nothing to search */
+ if (pwrdm_states BIT(req_state))
+ return req_state;
+
+ if (!req_state)
+ goto up_search;
+
+ /*
+* So, we dont have a exact match
+* Can we get a deeper power state match?
+*/
+ new_pwrst = req_state - 1;
+ found = true;
+ while (!(pwrdm_states BIT(new_pwrst))) {
+ /* No match even at OFF? Not available */
+ if (new_pwrst == PWRDM_POWER_OFF) {
+ found = false;
+ break;
+ }
+ new_pwrst--;
+ }
+
+ if (found)
+ goto done;
+
+up_search:
+ /* OK, no deeper ones, can we get a higher match? */
+ new_pwrst = req_state + 1;
+ while (!(pwrdm_states BIT(new_pwrst))) {
+ /* BUG if we have messed up database */
+ BUG_ON(new_pwrst PWRDM_POWER_ON);
+
+ if (new_pwrst == default_pwrst)
+ break;
+ new_pwrst++;
+ }
+done:
+ return new_pwrst;
+}
+
+/**
* omap_set_pwrdm_state - change a powerdomain's current power state
* @pwrdm: struct powerdomain * to change the power state of
* @pwrst: power state to change to
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index a754c82..11bd4dd 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -220,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain
*pwrdm);
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
+ bool is_logic_state, u8 req_state);
+
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_pwrst(struct powerdomain *pwrdm);
--
1.7.9.5
--
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[PATCH 2/6] ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstracted
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 47 +
1 file changed, 38 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a7f6ea2..d4d745e 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id)
u32 omap4_prm_vcvp_read(u8 offset)
{
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return 0;
+
return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
- OMAP4430_PRM_DEVICE_INST, offset);
+ inst, offset);
}
void omap4_prm_vcvp_write(u32 val, u8 offset)
{
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return;
+
omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
-OMAP4430_PRM_DEVICE_INST, offset);
+inst, offset);
}
u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
{
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return 0;
+
return omap4_prminst_rmw_inst_reg_bits(mask, bits,
OMAP4430_PRM_PARTITION,
- OMAP4430_PRM_DEVICE_INST,
+ inst,
offset);
}
@@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
void omap44xx_prm_reconfigure_io_chain(void)
{
int i = 0;
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return;
/* Trigger WUCLKIN enable */
omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
OMAP4430_WUCLK_CTRL_MASK,
- OMAP4430_PRM_DEVICE_INST,
+ inst,
OMAP4_PRM_IO_PMCTRL_OFFSET);
omap_test_timeout(
- (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+ (((omap4_prm_read_inst_reg(inst,
OMAP4_PRM_IO_PMCTRL_OFFSET)
OMAP4430_WUCLK_STATUS_MASK)
OMAP4430_WUCLK_STATUS_SHIFT) == 1),
@@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void)
/* Trigger WUCLKIN disable */
omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
- OMAP4430_PRM_DEVICE_INST,
+ inst,
OMAP4_PRM_IO_PMCTRL_OFFSET);
omap_test_timeout(
- (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+ (((omap4_prm_read_inst_reg(inst,
OMAP4_PRM_IO_PMCTRL_OFFSET)
OMAP4430_WUCLK_STATUS_MASK)
OMAP4430_WUCLK_STATUS_SHIFT) == 0),
@@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void)
*/
static void __init omap44xx_prm_enable_io_wakeup(void)
{
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return;
+
omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
OMAP4430_GLOBAL_WUEN_MASK,
- OMAP4430_PRM_DEVICE_INST,
+ inst,
OMAP4_PRM_IO_PMCTRL_OFFSET);
}
@@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void)
struct prm_reset_src_map *p;
u32 r = 0;
u32 v;
+ s32 inst = omap4_prmst_get_prm_dev_inst();
+
+ if (inst == PRM_INSTANCE_UNKNOWN)
+ return 0;
+
- v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+ v = omap4_prm_read_inst_reg(inst,
OMAP4_RM_RSTST);
p = omap44xx_prm_reset_src_map;
--
1.7.9.5
--
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[PATCH 4/6] ARM: OMAP4+: PRM: remove wkup event
wkup event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.
The same applies to AM437x as well.
Remove the wrong definition.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/prm44xx.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 5a70c91..b6bfa6f 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -33,7 +33,6 @@
/* Static data */
static const struct omap_prcm_irq omap4_prcm_irqs[] = {
- OMAP_PRCM_IRQ(wkup, 0, 0),
OMAP_PRCM_IRQ(io, 9, 1),
};
--
1.7.9.5
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[PATCH 0/6] ARM: OMAP3+: PRM: fix up prm_handling
The following series are various fixes and improvements for PRM for I/O Daisy chain support in OMAP4+ with device tree. This is part 2/6 series which eventually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7 Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/prm-fixes git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/prm-fixes An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Nishanth Menon (6): ARM: OMAP4+: prminst: provide function to find prm_dev instance offset ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstracted ARM: OMAP4+: PRM: register interrupt information from DT ARM: OMAP4+: PRM: remove wkup event ARM: OMAP4+: PRM: Enable wakeup capability for OMAP5, DRA7 ARM: OMAP3+: PRM: register interrupt information from DT arch/arm/mach-omap2/prm3xxx.c | 18 arch/arm/mach-omap2/prm44xx.c | 90 - arch/arm/mach-omap2/prminst44xx.c | 40 ++--- arch/arm/mach-omap2/prminst44xx.h |3 ++ 4 files changed, 125 insertions(+), 26 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] ARM: OMAP4+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d4d745e..5a70c91 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,6 +17,7 @@
#include linux/errno.h
#include linux/err.h
#include linux/io.h
+#include linux/of_irq.h
#include soc.h
@@ -699,11 +700,50 @@ int __init omap44xx_prm_init(void)
return prm_register(omap44xx_prm_ll_data);
}
+static struct of_device_id omap_prm_dt_match_table[] = {
+ { .compatible = ti,omap4-prm },
+ { .compatible = ti,omap5-prm },
+ { .compatible = ti,dra7-prm },
+ { }
+};
+
static int omap44xx_prm_late_init(void)
{
+ struct device_node *np;
+ int irq_num;
+
if (!(prm_features PRM_HAS_IO_WAKEUP))
return 0;
+ /* OMAP4+ is DT only now */
+ if (!of_have_populated_dt())
+ return 0;
+
+ np = of_find_matching_node(NULL, omap_prm_dt_match_table);
+
+ if (!np) {
+ /* Default loaded up with OMAP4 values */
+ if (!cpu_is_omap44xx())
+ return 0;
+ } else {
+ irq_num = of_irq_get(np, 0);
+ /*
+* Already have OMAP4 IRQ num. For all other platforms, we need
+* IRQ numbers from DT
+*/
+ if (irq_num 0 !cpu_is_omap44xx()) {
+ if (irq_num == -EPROBE_DEFER)
+ return irq_num;
+
+ /* Have nothing to do */
+ return 0;
+ }
+
+ /* Once OMAP4 DT is filled as well */
+ if (irq_num = 0)
+ omap4_prcm_irq_setup.irq = irq_num;
+ }
+
omap44xx_prm_enable_io_wakeup();
return omap_prcm_register_chain_handler(omap4_prcm_irq_setup);
--
1.7.9.5
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[PATCH 5/6] ARM: OMAP4+: PRM: Enable wakeup capability for OMAP5, DRA7
OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup
capability. So, enable the support.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index b6bfa6f..0958d07 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -693,7 +693,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
int __init omap44xx_prm_init(void)
{
- if (cpu_is_omap44xx())
+ if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
prm_features |= PRM_HAS_IO_WAKEUP;
return prm_register(omap44xx_prm_ll_data);
--
1.7.9.5
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[PATCH 6/6] ARM: OMAP3+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/prm3xxx.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 2458be6..e0088e0 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -17,6 +17,7 @@
#include linux/err.h
#include linux/io.h
#include linux/irq.h
+#include linux/of_irq.h
#include soc.h
#include common.h
@@ -649,6 +650,11 @@ int __init omap3xxx_prm_init(void)
return prm_register(omap3xxx_prm_ll_data);
}
+static struct of_device_id omap3_prm_dt_match_table[] = {
+ { .compatible = ti,omap3-prm },
+ { }
+};
+
static int omap3xxx_prm_late_init(void)
{
int ret;
@@ -656,6 +662,18 @@ static int omap3xxx_prm_late_init(void)
if (!(prm_features PRM_HAS_IO_WAKEUP))
return 0;
+ if (of_have_populated_dt()) {
+ struct device_node *np;
+ int irq_num;
+
+ np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
+ if (np) {
+ irq_num = of_irq_get(np, 0);
+ if (irq_num = 0)
+ omap3_prcm_irq_setup.irq = irq_num;
+ }
+ }
+
omap3xxx_prm_enable_io_wakeup();
ret = omap_prcm_register_chain_handler(omap3_prcm_irq_setup);
if (!ret)
--
1.7.9.5
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[PATCH 1/6] ARM: OMAP4+: prminst: provide function to find prm_dev instance offset
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Signed-off-by: Nishanth Menon n...@ti.com
---
Minor note: this patch has a 'CHECK: extern prototypes should be avoided in .h
files'
for prminst44xx.h but that is a continuation of existing style in the file.
arch/arm/mach-omap2/prminst44xx.c | 40 +++--
arch/arm/mach-omap2/prminst44xx.h |3 +++
2 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/prminst44xx.c
b/arch/arm/mach-omap2/prminst44xx.c
index 69f0dd0..225e025 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -31,6 +31,8 @@
static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
+
/**
* omap_prm_base_init - Populates the prm partitions
*
@@ -43,6 +45,24 @@ void omap_prm_base_init(void)
_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
}
+s32 omap4_prmst_get_prm_dev_inst(void)
+{
+ if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
+ return prm_dev_inst;
+
+ /* This cannot be done way early at boot.. as things are not setup */
+ if (cpu_is_omap44xx())
+ prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
+ else if (soc_is_omap54xx())
+ prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
+ else if (soc_is_dra7xx())
+ prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
+ else if (soc_is_am43xx())
+ prm_dev_inst = AM43XX_PRM_DEVICE_INST;
+
+ return prm_dev_inst;
+}
+
/* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
@@ -169,28 +189,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part,
s16 inst,
void omap4_prminst_global_warm_sw_reset(void)
{
u32 v;
- s16 dev_inst;
+ s32 inst = omap4_prmst_get_prm_dev_inst();
- if (cpu_is_omap44xx())
- dev_inst = OMAP4430_PRM_DEVICE_INST;
- else if (soc_is_omap54xx())
- dev_inst = OMAP54XX_PRM_DEVICE_INST;
- else if (soc_is_dra7xx())
- dev_inst = DRA7XX_PRM_DEVICE_INST;
- else if (soc_is_am43xx())
- dev_inst = AM43XX_PRM_DEVICE_INST;
- else
+ if (inst == PRM_INSTANCE_UNKNOWN)
return;
- v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
+ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
OMAP4_PRM_RSTCTRL_OFFSET);
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
-dev_inst,
-OMAP4_PRM_RSTCTRL_OFFSET);
+inst, OMAP4_PRM_RSTCTRL_OFFSET);
/* OCP barrier */
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
- dev_inst,
- OMAP4_PRM_RSTCTRL_OFFSET);
+ inst, OMAP4_PRM_RSTCTRL_OFFSET);
}
diff --git a/arch/arm/mach-omap2/prminst44xx.h
b/arch/arm/mach-omap2/prminst44xx.h
index a2ede2d..583aa37 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -12,6 +12,9 @@
#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+#define PRM_INSTANCE_UNKNOWN -1
+extern s32 omap4_prmst_get_prm_dev_inst(void);
+
/*
* In an ideal world, we would not export these low-level functions,
* but this will probably take some time to fix properly
--
1.7.9.5
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[PATCH 3/3] ARM: AM437x: use pdata quirks for pinctrl information
From: Keerthy j-keer...@ti.com
Provide pdata-quirks for Am437x processor family.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/pdata-quirks.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 827e106..5fea34e 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -359,6 +359,9 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
#ifdef CONFIG_SOC_DRA7XX
OF_DEV_AUXDATA(ti,dra7-padconf, 0x4a003400, 4a003400.pinmux,
pcs_pdata),
#endif
+#ifdef CONFIG_SOC_AM43XX
+ OF_DEV_AUXDATA(ti,am437-padconf, 0x44e10800, 44e10800.pinmux,
pcs_pdata),
+#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA(ti,omap4-iommu, 0x4a066000, 4a066000.mmu,
omap4_iommu_pdata),
--
1.7.9.5
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[PATCH 2/3] ARM: DRA7: use pdata quirks for pinctrl information
Provide pdata-quirks for DRA7 processor family.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/pdata-quirks.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index edacfed..827e106 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -356,6 +356,9 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA(ti,omap5-padconf, 0x4a002840, 4a002840.pinmux,
pcs_pdata),
OF_DEV_AUXDATA(ti,omap5-padconf, 0x4ae0c840, 4ae0c840.pinmux,
pcs_pdata),
#endif
+#ifdef CONFIG_SOC_DRA7XX
+ OF_DEV_AUXDATA(ti,dra7-padconf, 0x4a003400, 4a003400.pinmux,
pcs_pdata),
+#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA(ti,omap4-iommu, 0x4a066000, 4a066000.mmu,
omap4_iommu_pdata),
--
1.7.9.5
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[PATCH 1/3] ARM: OMAP5: use pdata quirks for pinctrl information
Provide pdata-quirks for OMAP5 processor family.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/pdata-quirks.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 90c88d4..edacfed 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -352,6 +352,10 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA(ti,omap4-padconf, 0x4a100040, 4a100040.pinmux,
pcs_pdata),
OF_DEV_AUXDATA(ti,omap4-padconf, 0x4a31e040, 4a31e040.pinmux,
pcs_pdata),
#endif
+#ifdef CONFIG_SOC_OMAP5
+ OF_DEV_AUXDATA(ti,omap5-padconf, 0x4a002840, 4a002840.pinmux,
pcs_pdata),
+ OF_DEV_AUXDATA(ti,omap5-padconf, 0x4ae0c840, 4ae0c840.pinmux,
pcs_pdata),
+#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA(ti,omap4-iommu, 0x4a066000, 4a066000.mmu,
omap4_iommu_pdata),
--
1.7.9.5
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[PATCH 0/3] ARM: OMAP5+: pdata quirks for pinctrl
The following series are various fixes and improvements for daisychain support in OMAP5+ using pinctrl framework similar to that done for OMAP3+ This is part 3/6 series which eventually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7 Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/prm-pdata-quirks git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/prm-pdata-quirks An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Minor note: thanks to existing style in pdata-quirks, new entries continue to possess 'over 80 character' checkpatch warnings Keerthy (1): ARM: AM437x: use pdata quirks for pinctrl information Nishanth Menon (2): ARM: OMAP5: use pdata quirks for pinctrl information ARM: DRA7: use pdata quirks for pinctrl information arch/arm/mach-omap2/pdata-quirks.c | 10 ++ 1 file changed, 10 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] pinctrl: single: Add DRA7 pinctrl compatibility
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../bindings/pinctrl/ti,omap-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-single.c |7 +++
2 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
index 156d964..d45386d 100644
--- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
@@ -5,5 +5,6 @@ Required properties:
ti,omap3-padconf - OMAP3 compatible pinctrl
ti,omap4-padconf - OMAP4 compatible pinctrl
ti,omap5-padconf - OMAP5 compatible pinctrl
+ ti,dra7-padconf - DRA7 compatible pinctrl
See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further
details.
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 95dd9cf..598d600 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1981,6 +1981,12 @@ static const struct pcs_soc_data
pinctrl_single_omap_wkup = {
.irq_status_mask = (1 15), /* OMAP_WAKEUP_EVENT */
};
+static const struct pcs_soc_data pinctrl_single_dra7 = {
+ .flags = PCS_QUIRK_SHARED_IRQ,
+ .irq_enable_mask = (1 24), /* WAKEUPENABLE */
+ .irq_status_mask = (1 25), /* WAKEUPEVENT */
+};
+
static const struct pcs_soc_data pinctrl_single = {
};
@@ -1992,6 +1998,7 @@ static struct of_device_id pcs_of_match[] = {
{ .compatible = ti,omap3-padconf, .data = pinctrl_single_omap_wkup },
{ .compatible = ti,omap4-padconf, .data = pinctrl_single_omap_wkup },
{ .compatible = ti,omap5-padconf, .data = pinctrl_single_omap_wkup },
+ { .compatible = ti,dra7-padconf, .data = pinctrl_single_dra7 },
{ .compatible = pinctrl-single, .data = pinctrl_single },
{ .compatible = pinconf-single, .data = pinconf_single },
{ },
--
1.7.9.5
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[PATCH 03/10] ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
From: Santosh Shilimkar santosh.shilim...@ti.com
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[n...@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap-secure.h|1 +
arch/arm/mach-omap2/omap-wakeupgen.c | 17 +
arch/arm/mach-omap2/omap-wakeupgen.h |1 +
3 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-secure.h
b/arch/arm/mach-omap2/omap-secure.h
index 3e97c6c..dec2b05 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -45,6 +45,7 @@
#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX0x109
+#define OMAP5_MON_AMBA_IF_INDEX0x108
/* Secure PPA(Primary Protected Application) APIs */
#define OMAP4_PPA_L2_POR_INDEX 0x23
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c
b/arch/arm/mach-omap2/omap-wakeupgen.c
index 37843a7..e844e16 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -406,6 +406,7 @@ int __init omap_wakeupgen_init(void)
{
int i;
unsigned int boot_cpu = smp_processor_id();
+ u32 val;
/* Not supported on OMAP4 ES1.0 silicon */
if (omap_rev() == OMAP4430_REV_ES1_0) {
@@ -451,6 +452,22 @@ int __init omap_wakeupgen_init(void)
for (i = 0; i max_irqs; i++)
irq_target_cpu[i] = boot_cpu;
+ /*
+* Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
+* 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
+* 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
+* independently.
+* This needs to be set one time thanks to always ON domain.
+*
+* We do not support ES1 behavior anymore. OMAP5 is assumed to be
+* ES2.0, and the same is applicable for DRA7.
+*/
+ if (soc_is_omap54xx() || soc_is_dra7xx()) {
+ val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
+ val |= BIT(5);
+ omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
+ }
+
irq_hotplug_init();
irq_pm_init();
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h
b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f..b3c8ecc 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
@@ -27,6 +27,7 @@
#define OMAP_WKG_ENB_E_1 0x420
#define OMAP_AUX_CORE_BOOT_0 0x800
#define OMAP_AUX_CORE_BOOT_1 0x804
+#define OMAP_AMBA_IF_MODE 0x80c
#define OMAP_PTMSYNCREQ_MASK 0xc00
#define OMAP_PTMSYNCREQ_EN 0xc04
#define OMAP_TIMESTAMPCYCLELO 0xc08
--
1.7.9.5
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[PATCH 09/10] ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
From: Santosh Shilimkar santosh.shilim...@ti.com
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[n...@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon n...@ti.com
---
/home/nmenon/tmp/upstream/v3.17/cpuidle-suspend-support/0009-ARM-OMAP5-Add-hook-in-SoC-initcalls-to-enable-pm-ini.patch
arch/arm/mach-omap2/common.h |2 +-
arch/arm/mach-omap2/io.c |3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dc571f1..5bb1592 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -60,7 +60,7 @@ static inline int omap3_pm_init(void)
}
#endif
-#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_PM) (defined(CONFIG_ARCH_OMAP4) ||
defined(CONFIG_SOC_OMAP5))
int omap4_pm_init(void);
int omap4_pm_init_early(void);
#else
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5d0667c..2890c2d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -667,6 +667,7 @@ void __init omap5_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap4_pm_init_early();
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
@@ -682,6 +683,8 @@ void __init omap5_init_early(void)
void __init omap5_init_late(void)
{
omap_common_late_init();
+ omap4_pm_init();
+ omap2_clk_enable_autoidle_all();
}
#endif
--
1.7.9.5
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[PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend
From: Rajendra Nayak rna...@ti.com
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
Signed-off-by: Rajendra Nayak rna...@ti.com
[n...@ti.com: update to do save_state only on DRA7]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |4
arch/arm/mach-omap2/omap-wakeupgen.c |2 +-
arch/arm/mach-omap2/pm44xx.c |9 +++--
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 207fce2..0d640eb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -242,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int
power_state)
save_state = 1;
break;
case PWRDM_POWER_RET:
+ if (soc_is_omap54xx() || soc_is_dra7xx()) {
+ save_state = 0;
+ break;
+ }
default:
/*
* CPUx CSWR is invalid hardware state. Also CPUx OSWR
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c
b/arch/arm/mach-omap2/omap-wakeupgen.c
index e844e16..87c1c0d 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -381,7 +381,7 @@ static struct notifier_block irq_notifier_block = {
static void __init irq_pm_init(void)
{
/* FIXME: Remove this when MPU OSWR support is added */
- if (!soc_is_omap54xx())
+ if (!soc_is_omap54xx() !soc_is_dra7xx())
cpu_pm_register_notifier(irq_notifier_block);
}
#else
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index b6f243d..c063833 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -36,6 +36,8 @@ struct power_state {
struct list_head node;
};
+static u32 cpu_suspend_state = PWRDM_POWER_OFF;
+
static LIST_HEAD(pwrst_list);
#ifdef CONFIG_SUSPEND
@@ -66,7 +68,7 @@ static int omap4_pm_suspend(void)
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+ omap4_enter_lowpower(cpu_id, cpu_suspend_state);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, pwrst_list, node) {
@@ -112,8 +114,11 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *unused)
* through hotplug path and CPU0 explicitly programmed
* further down in the code path
*/
- if (!strncmp(pwrdm-name, cpu, 3))
+ if (!strncmp(pwrdm-name, cpu, 3)) {
+ if (soc_is_omap54xx() || soc_is_dra7xx())
+ cpu_suspend_state = PWRDM_POWER_RET;
return 0;
+ }
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)
--
1.7.9.5
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[PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support
From: Santosh Shilimkar santosh.shilim...@ti.com
Add OMAP5/DRA74/72 CPUIDLE support.
This patch adds MPUSS low power states in cpuidle.
C1 - CPU0 WFI + CPU1 WFI + MPU ON
C2 - CPU0 RET + CPU1 RET + MPU CSWR
Tested on DRA74/72-EVM for C1 and C2 states.
NOTE: DRA7 does not do voltage scaling as part of retention transition
and has Mercury which speeds up transition paths - Latency numbers are
based on measurements done by toggling GPIOs.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[ j-keer...@ti.com rework on 3.14]
Signed-off-by: Keerthy j-keer...@ti.com
[n...@ti.com: updates based on profiling, OMAP5 squashed]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c | 82 -
arch/arm/mach-omap2/pm44xx.c |2 +-
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach-omap2/cpuidle44xx.c
index 2498ab0..8ad4f44 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -22,6 +22,7 @@
#include common.h
#include pm.h
#include prm.h
+#include soc.h
#include clockdomain.h
#define MAX_CPUS 2
@@ -31,6 +32,7 @@ struct idle_statedata {
u32 cpu_state;
u32 mpu_logic_state;
u32 mpu_state;
+ u32 mpu_state_vote;
};
static struct idle_statedata omap4_idle_data[] = {
@@ -51,12 +53,26 @@ static struct idle_statedata omap4_idle_data[] = {
},
};
+static struct idle_statedata dra7_idle_data[] = {
+ {
+ .cpu_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_POWER_ON,
+ .mpu_logic_state = PWRDM_POWER_ON,
+ },
+ {
+ .cpu_state = PWRDM_POWER_RET,
+ .mpu_state = PWRDM_POWER_RET,
+ .mpu_logic_state = PWRDM_POWER_RET,
+ },
+};
+
static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
static struct clockdomain *cpu_clkdm[MAX_CPUS];
static atomic_t abort_barrier;
static bool cpu_done[MAX_CPUS];
static struct idle_statedata *state_ptr = omap4_idle_data[0];
+static DEFINE_RAW_SPINLOCK(mpu_lock);
/* Private functions */
@@ -78,6 +94,32 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev,
return index;
}
+static int omap_enter_idle_smp(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct idle_statedata *cx = state_ptr + index;
+ unsigned long flag;
+
+ raw_spin_lock_irqsave(mpu_lock, flag);
+ cx-mpu_state_vote++;
+ if (cx-mpu_state_vote == num_online_cpus()) {
+ pwrdm_set_logic_retst(mpu_pd, cx-mpu_logic_state);
+ omap_set_pwrdm_state(mpu_pd, cx-mpu_state);
+ }
+ raw_spin_unlock_irqrestore(mpu_lock, flag);
+
+ omap4_enter_lowpower(dev-cpu, cx-cpu_state);
+
+ raw_spin_lock_irqsave(mpu_lock, flag);
+ if (cx-mpu_state_vote == num_online_cpus())
+ omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
+ cx-mpu_state_vote--;
+ raw_spin_unlock_irqrestore(mpu_lock, flag);
+
+ return index;
+}
+
static int omap_enter_idle_coupled(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -224,6 +266,34 @@ static struct cpuidle_driver omap4_idle_driver = {
.safe_state_index = 0,
};
+static struct cpuidle_driver dra7_idle_driver = {
+ .name = dra7_idle,
+ .owner = THIS_MODULE,
+ .states = {
+ {
+ /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+ .exit_latency = 2 + 2,
+ .target_residency = 5,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .enter = omap_enter_idle_simple,
+ .name = C1,
+ .desc = CPUx WFI, MPUSS ON
+ },
+ {
+ /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
+ .exit_latency = 48 + 60,
+ .target_residency = 100,
+ .flags = CPUIDLE_FLAG_TIME_VALID
+ | CPUIDLE_FLAG_TIMER_STOP,
+ .enter = omap_enter_idle_smp,
+ .name = C2,
+ .desc = CPUx CSWR, MPUSS CSWR,
+ },
+ },
+ .state_count = ARRAY_SIZE(dra7_idle_data),
+ .safe_state_index = 0,
+};
+
/* Public functions */
/**
@@ -234,6 +304,16 @@ static struct cpuidle_driver omap4_idle_driver = {
*/
int __init omap4_idle_init(void)
{
+ struct cpuidle_driver *idle_driver;
+
+ if (soc_is_dra7xx() || soc_is_omap54xx()) {
+ state_ptr = dra7_idle_data[0];
+ idle_driver = dra7_idle_driver;
+ } else {
+ state_ptr = omap4_idle_data[0];
+
[PATCH 06/10] ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
From: Santosh Shilimkar santosh.shilim...@ti.com
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[n...@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 53d8de5..207fce2 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -69,7 +69,6 @@ struct omap4_cpu_pm_info {
void __iomem *scu_sar_addr;
void __iomem *wkup_sar_addr;
void __iomem *l2x0_sar_addr;
- void (*secondary_startup)(void);
};
/**
@@ -77,6 +76,7 @@ struct omap4_cpu_pm_info {
* @finish_suspend:CPU suspend finisher function pointer
* @resume:CPU resume function pointer
* @scu_prepare: CPU Snoop Control program function pointer
+ * @hotplug_restart: CPU restart function pointer
*
* Structure holds functions pointer for CPU low power operations like
* suspend, resume and scu programming.
@@ -85,6 +85,7 @@ struct cpu_pm_ops {
int (*finish_suspend)(unsigned long cpu_state);
void (*resume)(void);
void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
+ void (*hotplug_restart)(void);
};
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
@@ -108,6 +109,7 @@ struct cpu_pm_ops omap_pm_ops = {
.finish_suspend = default_finish_suspend,
.resume = dummy_cpu_resume,
.scu_prepare= dummy_scu_prepare,
+ .hotplug_restart= dummy_cpu_resume,
};
/*
@@ -312,7 +314,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int
power_state)
pwrdm_clear_all_prev_pwrst(pm_info-pwrdm);
pwrdm_set_next_pwrst(pm_info-pwrdm, power_state);
- set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info-secondary_startup));
+ set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
omap_pm_ops.scu_prepare(cpu, power_state);
/*
@@ -385,10 +387,6 @@ int __init omap4_mpuss_init(void)
CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info-l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
}
- if (cpu_is_omap446x())
- pm_info-secondary_startup = omap4460_secondary_startup;
- else
- pm_info-secondary_startup = omap4_secondary_startup;
pm_info-pwrdm = pwrdm_lookup(cpu1_pwrdm);
if (!pm_info-pwrdm) {
@@ -422,12 +420,16 @@ int __init omap4_mpuss_init(void)
omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+ omap_pm_ops.hotplug_restart = omap4_secondary_startup;
cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
enable_mercury_retention_mode();
}
+ if (cpu_is_omap446x())
+ omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
+
return 0;
}
--
1.7.9.5
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[RFC PATCH 3/4] tty: omap-serial: use threaded interrupt handler
At 3.6Mbaud, with slightly over 2Mbit/s data coming in, we see 1600 uart
rx buffer overflows within 30 seconds. Threading the interrupt handling reduces
this to about 170 overflows in 10 minutes.
In practice this therefore reduces the need for hardware flow control,
meaning the sending side doesn't have to buffer as much either.
Signed-off-by: Frans Klaver frans.kla...@xsens.com
---
drivers/tty/serial/omap-serial.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 14a0167..1671443a 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -575,6 +575,20 @@ static void serial_omap_rdi(struct uart_omap_port *up,
unsigned int lsr)
}
/**
+ * serial_omap_fast_irq() - schedule interrupt handling
+ */
+static irqreturn_t serial_omap_fast_irq(int irq, void *dev_id)
+{
+ struct uart_omap_port *up = dev_id;
+ unsigned int iir = serial_in(up, UART_IIR);
+
+ if (iir UART_IIR_NO_INT)
+ return IRQ_NONE;
+
+ return IRQ_WAKE_THREAD;
+}
+
+/**
* serial_omap_irq() - This handles the interrupt from one port
* @irq: uart port irq number
* @dev_id: uart port info
@@ -584,7 +598,6 @@ static irqreturn_t serial_omap_irq(int irq, void *dev_id)
struct uart_omap_port *up = dev_id;
unsigned int iir, lsr;
unsigned int type;
- irqreturn_t ret = IRQ_NONE;
int max_count = 256;
spin_lock(up-port.lock);
@@ -595,7 +608,6 @@ static irqreturn_t serial_omap_irq(int irq, void *dev_id)
if (iir UART_IIR_NO_INT)
break;
- ret = IRQ_HANDLED;
lsr = serial_in(up, UART_LSR);
/* extract IRQ type from IIR register */
@@ -634,7 +646,7 @@ static irqreturn_t serial_omap_irq(int irq, void *dev_id)
pm_runtime_put_autosuspend(up-dev);
up-port_activity = jiffies;
- return ret;
+ return IRQ_HANDLED;
}
static unsigned int serial_omap_tx_empty(struct uart_port *port)
@@ -731,15 +743,19 @@ static int serial_omap_startup(struct uart_port *port)
/*
* Allocate the IRQ
*/
- retval = request_irq(up-port.irq, serial_omap_irq, up-port.irqflags,
- up-name, up);
+ retval = request_threaded_irq(up-port.irq, serial_omap_fast_irq,
+ serial_omap_irq,
+ IRQF_ONESHOT |
up-port.irqflags,
+ up-name, up);
if (retval)
return retval;
/* Optional wake-up IRQ */
if (up-wakeirq) {
- retval = request_irq(up-wakeirq, serial_omap_irq,
-up-port.irqflags, up-name, up);
+ retval = request_threaded_irq(up-wakeirq, serial_omap_fast_irq,
+ serial_omap_irq,
+ IRQF_ONESHOT |
up-port.irqflags,
+ up-name, up);
if (retval) {
free_irq(up-port.irq, up);
return retval;
--
1.9.3
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[PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle
The following series are various fixes and improvements for supporting suspend-to-ram. This depends on the following for basic functionality: series 1/6 where powerdomain fixes were involved. This will at least allow wake up from an internal source such as from a wakeup timer: For example with https://github.com/nmenon/linux-2.6-playground/commit/92e5e7407aa707ad6be8ae3b5bf21cfc741daab6 pinctrl series allows for external wakeup event sources like pushbutton etc. NOTE: OMAP5 and DRA7 definitions of power states and suspend targets are almost identical (except for core power domain target state as part of suspend). NOTE: This also needs missing hwmod and dts entries for various peripherals that will eventually arrive over a period of time. This is part 5/6 series which actually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7 Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/powerdomain-fixes git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/powerdomain-fixes An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Example test log: DRA7 based BeagleBoard X15: http://slexy.org/view/s2jgsH8bos (wakeup from external using pinctrl wakeup). OMAP5UEVM: http://slexy.org/view/s20MiQJQIq (external pinctrl not hooked) Rajendra Nayak (3): ARM: OMAP5 / DRA7: PM: Avoid all SAR saves ARM: OMAP5 / DRA7: Enable CPU RET on suspend ARM: DRA7: Add hook in SoC initcalls to enable pm initialization Santosh Shilimkar (7): ARM: OMAP5 / DRA7: PM: Update CPU context register offset ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization arch/arm/mach-omap2/common.h |2 +- arch/arm/mach-omap2/cpuidle44xx.c | 82 ++- arch/arm/mach-omap2/io.c |6 ++ arch/arm/mach-omap2/omap-mpuss-lowpower.c | 102 - arch/arm/mach-omap2/omap-secure.h |1 + arch/arm/mach-omap2/omap-wakeupgen.c | 19 +- arch/arm/mach-omap2/omap-wakeupgen.h |1 + arch/arm/mach-omap2/pm44xx.c | 47 +++-- 8 files changed, 220 insertions(+), 40 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/6] ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable
Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022..a329177 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -303,6 +303,8 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
+ interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
+ dra7_pmx_core 0x3e0;
};
uart2 {
--
1.7.9.5
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[PATCH 01/10] ARM: OMAP5 / DRA7: PM: Update CPU context register offset
From: Santosh Shilimkar santosh.shilim...@ti.com
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[rna...@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak rna...@ti.com
[n...@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 4001325..63a1dd7 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -56,6 +56,7 @@
#include omap4-sar-layout.h
#include pm.h
#include prcm_mpu44xx.h
+#include prcm_mpu54xx.h
#include prminst44xx.h
#include prcm44xx.h
#include prm44xx.h
@@ -89,6 +90,7 @@ struct cpu_pm_ops {
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static void __iomem *sar_base;
+static u32 cpu_context_offset;
static int default_finish_suspend(unsigned long cpu_state)
{
@@ -161,14 +163,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned
int cpu_id)
if (cpu_id) {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
- OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+ cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
- OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+ cpu_context_offset);
} else {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
- OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+ cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
- OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+ cpu_context_offset);
}
}
@@ -392,6 +394,9 @@ int __init omap4_mpuss_init(void)
omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+ cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
+ cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
}
return 0;
--
1.7.9.5
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[PATCH 0/6] ARM: dts: OMAP5+: Fixes for pinctrl support
The following series add the missing dts changes needed for pinctrl to finally work on OMAP5/DRA7. This is part 6/6 series which eventually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7. Depends on previous series for pinctrl and PRM fixes for functionality, but is capable of continuing to provide older functionality with older zImage NOTE: Various hwmod and dts fixes for various other IP blocks are still pending for complete suspend functionality. Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/dts-fixes git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/dts-fixes An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Nishanth Menon (6): ARM: dts: OMAP3+: Add PRM interrupt ARM: dts: OMAP5: switch to compatible pinctrl ARM: dts: DRA7: switch to compatible pinctrl ARM: dts: AM437x: switch to compatible pinctrl ARM: dts: OMAP5/DRA7: switch over to interrupts-extended property for UART ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable arch/arm/boot/dts/am4372.dtsi |4 +++- arch/arm/boot/dts/dra7-evm.dts |2 ++ arch/arm/boot/dts/dra7.dtsi| 25 ++--- arch/arm/boot/dts/omap3.dtsi |1 + arch/arm/boot/dts/omap4.dtsi |1 + arch/arm/boot/dts/omap5.dtsi | 21 + 6 files changed, 34 insertions(+), 20 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/10] ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
From: Santosh Shilimkar santosh.shilim...@ti.com
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only Fast-mode is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[n...@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon n...@ti.com
---
This has a minor checkpatch warning for aligning with '(', but that
when fixed results in over 80 char warning. So choose '(' check instead :D.
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 63a1dd7..fad6e8c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -321,6 +321,21 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int
power_state)
/*
+ * Enable Mercury Fast HG retention mode by default.
+ */
+static void enable_mercury_retention_mode(void)
+{
+ u32 reg;
+
+ reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
+ OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
+ /* Enable HG_EN, HG_RAMPUP = fast mode */
+ reg |= BIT(24) | BIT(25);
+ omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
+ OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
+}
+
+/*
* Initialise OMAP4 MPUSS
*/
int __init omap4_mpuss_init(void)
@@ -397,6 +412,7 @@ int __init omap4_mpuss_init(void)
cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
+ enable_mercury_retention_mode();
}
return 0;
--
1.7.9.5
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[PATCH 10/10] ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
From: Rajendra Nayak rna...@ti.com
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak rna...@ti.com
[n...@ti.com: minor modifications]
Signed-off-by: Nishanth Menon n...@ti.com
---
Note: Minor checkpatch warning exists for 80 char limit that was ignored.
arch/arm/mach-omap2/common.h |2 +-
arch/arm/mach-omap2/io.c |3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 5bb1592..b6d2989 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -60,7 +60,7 @@ static inline int omap3_pm_init(void)
}
#endif
-#if defined(CONFIG_PM) (defined(CONFIG_ARCH_OMAP4) ||
defined(CONFIG_SOC_OMAP5))
+#if defined(CONFIG_PM) (defined(CONFIG_ARCH_OMAP4) ||
defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
int omap4_pm_init(void);
int omap4_pm_init_early(void);
#else
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2890c2d..831805e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -698,6 +698,7 @@ void __init dra7xx_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap4_pm_init_early();
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
@@ -712,6 +713,8 @@ void __init dra7xx_init_early(void)
void __init dra7xx_init_late(void)
{
omap_common_late_init();
+ omap4_pm_init();
+ omap2_clk_enable_autoidle_all();
}
#endif
--
1.7.9.5
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[PATCH 02/10] ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
From: Santosh Shilimkar santosh.shilim...@ti.com
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
[rna...@ti.com: DRA7]
Signed-off-by: Rajendra Nayak rna...@ti.com
[n...@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/pm44xx.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 0dda6cf..b6f243d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -203,6 +203,32 @@ static inline int omap4_init_static_deps(void)
}
/**
+ * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
+ * DRA7
+ *
+ * The dynamic dependency between MPUSS - EMIF is broken and has
+ * not worked as expected. The hardware recommendation is to
+ * enable static dependencies for these to avoid system
+ * lock ups or random crashes.
+ */
+static inline int omap5_dra7_init_static_deps(void)
+{
+ struct clockdomain *mpuss_clkdm, *emif_clkdm;
+ int ret;
+
+ mpuss_clkdm = clkdm_lookup(mpu_clkdm);
+ emif_clkdm = clkdm_lookup(emif_clkdm);
+ if (!mpuss_clkdm || !emif_clkdm)
+ return -EINVAL;
+
+ ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+ if (ret)
+ pr_err(Failed to add MPUSS - EMIF wakeup dependency\n);
+
+ return ret;
+}
+
+/**
* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
*
* Initializes basic stuff for power management functionality.
@@ -239,10 +265,14 @@ int __init omap4_pm_init(void)
goto err2;
}
- if (cpu_is_omap44xx()) {
+ if (cpu_is_omap44xx())
ret = omap4_init_static_deps();
- if (ret)
- goto err2;
+ else if (soc_is_omap54xx() || soc_is_dra7xx())
+ ret = omap5_dra7_init_static_deps();
+
+ if (ret) {
+ pr_err(Failed to initialise static dependencies.\n);
+ goto err2;
}
ret = omap4_mpuss_init();
--
1.7.9.5
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[PATCH 05/10] ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
From: Rajendra Nayak rna...@ti.com
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak rna...@ti.com
[n...@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 55 ++---
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index fad6e8c..53d8de5 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -118,7 +118,8 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id,
u32 addr)
{
struct omap4_cpu_pm_info *pm_info = per_cpu(omap4_pm_info, cpu_id);
- writel_relaxed(addr, pm_info-wkup_sar_addr);
+ if (pm_info-wkup_sar_addr)
+ writel_relaxed(addr, pm_info-wkup_sar_addr);
}
/*
@@ -143,7 +144,8 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned
int cpu_state)
break;
}
- writel_relaxed(scu_pwr_st, pm_info-scu_sar_addr);
+ if (pm_info-scu_sar_addr)
+ writel_relaxed(scu_pwr_st, pm_info-scu_sar_addr);
}
/* Helper functions for MPUSS OSWR */
@@ -181,7 +183,8 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id,
unsigned int save_state)
{
struct omap4_cpu_pm_info *pm_info = per_cpu(omap4_pm_info, cpu_id);
- writel_relaxed(save_state, pm_info-l2x0_sar_addr);
+ if (pm_info-l2x0_sar_addr)
+ writel_relaxed(save_state, pm_info-l2x0_sar_addr);
}
/*
@@ -191,10 +194,14 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id,
unsigned int save_state)
#ifdef CONFIG_CACHE_L2X0
static void __init save_l2x0_context(void)
{
- writel_relaxed(l2x0_saved_regs.aux_ctrl,
-sar_base + L2X0_AUXCTRL_OFFSET);
- writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+ void __iomem *l2x0_base = omap4_get_l2cache_base();
+
+ if (l2x0_base sar_base) {
+ writel_relaxed(l2x0_saved_regs.aux_ctrl,
+ sar_base + L2X0_AUXCTRL_OFFSET);
+ writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+ sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+ }
}
#else
static void __init save_l2x0_context(void)
@@ -347,13 +354,17 @@ int __init omap4_mpuss_init(void)
return -ENODEV;
}
- sar_base = omap4_get_sar_ram_base();
+ if (cpu_is_omap44xx())
+ sar_base = omap4_get_sar_ram_base();
/* Initilaise per CPU PM information */
pm_info = per_cpu(omap4_pm_info, 0x0);
- pm_info-scu_sar_addr = sar_base + SCU_OFFSET0;
- pm_info-wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
- pm_info-l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ if (sar_base) {
+ pm_info-scu_sar_addr = sar_base + SCU_OFFSET0;
+ pm_info-wkup_sar_addr = sar_base +
+ CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info-l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ }
pm_info-pwrdm = pwrdm_lookup(cpu0_pwrdm);
if (!pm_info-pwrdm) {
pr_err(Lookup failed for CPU0 pwrdm\n);
@@ -368,9 +379,12 @@ int __init omap4_mpuss_init(void)
pwrdm_set_next_pwrst(pm_info-pwrdm, PWRDM_POWER_ON);
pm_info = per_cpu(omap4_pm_info, 0x1);
- pm_info-scu_sar_addr = sar_base + SCU_OFFSET1;
- pm_info-wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
- pm_info-l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ if (sar_base) {
+ pm_info-scu_sar_addr = sar_base + SCU_OFFSET1;
+ pm_info-wkup_sar_addr = sar_base +
+ CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info-l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ }
if (cpu_is_omap446x())
pm_info-secondary_startup = omap4460_secondary_startup;
else
@@ -397,13 +411,12 @@ int __init omap4_mpuss_init(void)
pwrdm_clear_all_prev_pwrst(mpuss_pd);
mpuss_clear_prev_logic_pwrst();
- /* Save device type on scratchpad for low level code to use */
- if (omap_type() != OMAP2_DEVICE_TYPE_GP)
- writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
- else
- writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
-
- save_l2x0_context();
+ if (sar_base) {
+ /* Save device type on scratchpad for low level code to use */
+ writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
+ sar_base + OMAP_TYPE_OFFSET);
+ save_l2x0_context();
+ }
if (cpu_is_omap44xx()) {
[PATCH 4/6] ARM: dts: AM437x: switch to compatible pinctrl
Now that ti,am437-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark the pinctrl as interrupt controller so that it can
be used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/am4372.dtsi |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 9b3d2ba..b384830 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -58,10 +58,12 @@
};
am43xx_pinmux: pinmux@44e10800 {
- compatible = pinctrl-single;
+ compatible = ti,am437-padconf, pinctrl-single;
reg = 0x44e10800 0x31c;
#address-cells = 1;
#size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
pinctrl-single,register-width = 32;
pinctrl-single,function-mask = 0x;
};
--
1.7.9.5
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[PATCH 3/6] ARM: dts: DRA7: switch to compatible pinctrl
Now that ti,dra7-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be used
with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 7a3e011..4e4ce96 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -218,10 +218,12 @@
};
dra7_pmx_core: pinmux@4a003400 {
- compatible = pinctrl-single;
+ compatible = ti,dra7-padconf, pinctrl-single;
reg = 0x4a003400 0x0464;
#address-cells = 1;
#size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
pinctrl-single,register-width = 32;
pinctrl-single,function-mask = 0x3fff;
};
--
1.7.9.5
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[PATCH 3/3] pinctrl: single: AM437x: Add pinctrl compatibility
From: Keerthy j-keer...@ti.com
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Keerthy j-keer...@ti.com
[n...@ti.com: minor updates]
Signed-off-by: Nishanth Menon n...@ti.com
---
.../bindings/pinctrl/ti,omap-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-single.c |7 +++
2 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
index d45386d..af225fe 100644
--- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
@@ -6,5 +6,6 @@ Required properties:
ti,omap4-padconf - OMAP4 compatible pinctrl
ti,omap5-padconf - OMAP5 compatible pinctrl
ti,dra7-padconf - DRA7 compatible pinctrl
+ ti,am437-padconf - AM437x compatible pinctrl
See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further
details.
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 598d600..784de13 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1987,6 +1987,12 @@ static const struct pcs_soc_data pinctrl_single_dra7 = {
.irq_status_mask = (1 25), /* WAKEUPEVENT */
};
+static const struct pcs_soc_data pinctrl_single_am437x = {
+ .flags = PCS_QUIRK_SHARED_IRQ,
+ .irq_enable_mask = (1 29), /* OMAP_WAKEUP_EN */
+ .irq_status_mask = (1 30), /* OMAP_WAKEUP_EVENT */
+};
+
static const struct pcs_soc_data pinctrl_single = {
};
@@ -1999,6 +2005,7 @@ static struct of_device_id pcs_of_match[] = {
{ .compatible = ti,omap4-padconf, .data = pinctrl_single_omap_wkup },
{ .compatible = ti,omap5-padconf, .data = pinctrl_single_omap_wkup },
{ .compatible = ti,dra7-padconf, .data = pinctrl_single_dra7 },
+ { .compatible = ti,am437-padconf, .data = pinctrl_single_am437x },
{ .compatible = pinctrl-single, .data = pinctrl_single },
{ .compatible = pinconf-single, .data = pinconf_single },
{ },
--
1.7.9.5
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[PATCH 5/6] ARM: dts: OMAP5/DRA7: switch over to interrupts-extended property for UART
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786a1 (pinctrl: single: Add support for wake-up interrupts)
that recently got merged. In addition to that we also needed
commit 79d9701559a9 (of/irq: create interrupts-extended property)
that's now also merged.
Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 20 ++--
arch/arm/boot/dts/omap5.dtsi | 12 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 4e4ce96..45cb91f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -331,7 +331,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -340,7 +340,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart2;
clock-frequency = 4800;
status = disabled;
@@ -349,7 +349,7 @@
uart3: serial@4802 {
compatible = ti,omap4-uart;
reg = 0x4802 0x100;
- interrupts = GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 69
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart3;
clock-frequency = 4800;
status = disabled;
@@ -358,7 +358,7 @@
uart4: serial@4806e000 {
compatible = ti,omap4-uart;
reg = 0x4806e000 0x100;
- interrupts = GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 65
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart4;
clock-frequency = 4800;
status = disabled;
@@ -367,7 +367,7 @@
uart5: serial@48066000 {
compatible = ti,omap4-uart;
reg = 0x48066000 0x100;
- interrupts = GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 100
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart5;
clock-frequency = 4800;
status = disabled;
@@ -376,7 +376,7 @@
uart6: serial@48068000 {
compatible = ti,omap4-uart;
reg = 0x48068000 0x100;
- interrupts = GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 101
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart6;
clock-frequency = 4800;
status = disabled;
@@ -385,7 +385,7 @@
uart7: serial@4842 {
compatible = ti,omap4-uart;
reg = 0x4842 0x100;
- interrupts = GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 218
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart7;
clock-frequency = 4800;
status = disabled;
@@ -394,7 +394,7 @@
uart8: serial@48422000 {
compatible = ti,omap4-uart;
reg = 0x48422000 0x100;
- interrupts = GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 219
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart8;
clock-frequency = 4800;
status = disabled;
@@ -403,7 +403,7 @@
uart9: serial@48424000 {
compatible = ti,omap4-uart;
reg = 0x48424000 0x100;
- interrupts = GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = gic GIC_SPI 220
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart9;
clock-frequency = 4800;
status = disabled;
@@
[PATCH 1/6] ARM: dts: OMAP3+: Add PRM interrupt
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |1 +
arch/arm/boot/dts/omap3.dtsi |1 +
arch/arm/boot/dts/omap4.dtsi |1 +
arch/arm/boot/dts/omap5.dtsi |1 +
4 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 97f603c..7a3e011 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -89,6 +89,7 @@
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
reg = 0x4ae06000 0x3000;
+ interrupts = GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH;
prm_clocks: clocks {
#address-cells = 1;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 575a49b..3136ed1 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -97,6 +97,7 @@
prm: prm@48306000 {
compatible = ti,omap3-prm;
reg = 0x48306000 0x4000;
+ interrupts = 11;
prm_clocks: clocks {
#address-cells = 1;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 69408b5..7375d44 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -129,6 +129,7 @@
prm: prm@4a306000 {
compatible = ti,omap4-prm;
reg = 0x4a306000 0x3000;
+ interrupts = GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
prm_clocks: clocks {
#address-cells = 1;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc8df17..df0a09b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -131,6 +131,7 @@
prm: prm@4ae06000 {
compatible = ti,omap5-prm;
reg = 0x4ae06000 0x3000;
+ interrupts = GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
prm_clocks: clocks {
#address-cells = 1;
--
1.7.9.5
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[PATCH 0/3] pinctrl: Add DRA7/AM437x pinctrl compatibility
The following series are various fixes and improvements for pinctrl for AM437x and DRA7. It also tries to add documentation for existing pinctrl bindings for Texas Instruments' OMAP SoCs. Functionality depends on the dts update (in series 6), PRM fixes and the pdata quirk changes This is part 4/6 series which eventually enables framework for suspend-to-ram and cpuidle for OMAP5 and DRA7 Each of series is based on v3.17-rc1 and this specific series is available: weblink: https://github.com/nmenon/linux-2.6-playground/commits/push/v3.17/pinctrl-compat git repo: https://github.com/nmenon/linux-2.6-playground.git push/v3.17/pinctrl-compat An complete integrated branch is available here: https://github.com/nmenon/linux-2.6-playground/commits/testing/v3.17/cpu-idle-suspend-dra7-omap5-framework Keerthy (1): pinctrl: single: AM437x: Add pinctrl compatibility Nishanth Menon (2): pinctrl: bindings: Add OMAP pinctrl binding pinctrl: single: Add DRA7 pinctrl compatibility .../bindings/pinctrl/ti,omap-pinctrl.txt | 11 +++ drivers/pinctrl/pinctrl-single.c | 14 ++ 2 files changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] pinctrl: bindings: Add OMAP pinctrl binding
Add basic skeleton of OMAP pinctrl bindings. This is compatible with pinctrl,single bindings and is meant purely as a reference point. Signed-off-by: Nishanth Menon n...@ti.com --- .../bindings/pinctrl/ti,omap-pinctrl.txt |9 + 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt new file mode 100644 index 000..156d964 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt @@ -0,0 +1,9 @@ +OMAP Pinctrl definitions + +Required properties: +- compatible : Should be one of: + ti,omap3-padconf - OMAP3 compatible pinctrl + ti,omap4-padconf - OMAP4 compatible pinctrl + ti,omap5-padconf - OMAP5 compatible pinctrl + +See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/6] ARM: dts: OMAP5: switch to compatible pinctrl
Now that ti,omap5-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be
used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index df0a09b..04acda6 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -188,18 +188,22 @@
};
omap5_pmx_core: pinmux@4a002840 {
- compatible = ti,omap4-padconf, pinctrl-single;
+ compatible = ti,omap5-padconf, pinctrl-single;
reg = 0x4a002840 0x01b6;
#address-cells = 1;
#size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
pinctrl-single,register-width = 16;
pinctrl-single,function-mask = 0x7fff;
};
omap5_pmx_wkup: pinmux@4ae0c840 {
- compatible = ti,omap4-padconf, pinctrl-single;
+ compatible = ti,omap5-padconf, pinctrl-single;
reg = 0x4ae0c840 0x0038;
#address-cells = 1;
#size-cells = 0;
+ #interrupt-cells = 1;
+ interrupt-controller;
pinctrl-single,register-width = 16;
pinctrl-single,function-mask = 0x7fff;
};
--
1.7.9.5
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Re: [PATCH] usb: phy: twl4030-usb: Fix lost interrupts after ID pin goes down
Hi,
* Grazvydas Ignotas nota...@gmail.com [140822 06:21]:
Hi,
On Thu, Aug 21, 2014 at 7:48 PM, Tony Lindgren t...@atomide.com wrote:
Commit 249751f22380 (usb: phy: twl4030-usb: poll for ID disconnect)
added twl4030_id_workaround_work() to deal with lost interrupts
after ID pin goes down. However, this currently only works for the
insertion. The PHY interrupts are not working after disconnecting
an USB-A device from the board, and the deeper idle states for
omap are blocked as the USB controller stays busy.
The issue can be solved by calling delayed work from twl4030_usb_irq()
when ID pin is down and the PHY is not asleep like we already do
in twl4030_id_workaround_work().
The way it is supposed to work is that after plugging in the cable
twl4030_phy_power_on() sees ID_GROUND and kicks off id_workaround_work
every second. When cable is unplugged, twl4030_id_workaround_work()
sees changes in STS_HW_CONDITIONS register and triggers events.
Doesn't that work for you, why do you need to trigger it from
twl4030_usb_irq() too?
Not any longer because we are currently call schedule_delayed_work()
only from twl4030_phy_power_on(). That function got renamed, it used
to be twl4030_phy_resume() before the generic phy framework
changes.
So looking at the v3.12 code, you're right, it seems to behave as
you describe. That however changed with the generic phy framework
changes for v3.13, and looks like the correct breaking commit is
f1ddc24c9e33 (usb: phy: twl4030-usb: remove *set_suspend* and
*phy_init* ops) instead.
So it won't currently work after unplugging and replugging as all
connect and disconnect interrupts go unnoticed after ID_GROUND.
So we need to poll whenever ID_GROUND and PHY is not asleep.
But as both twl4030_usb_irq() and twl4030_id_workaround_work()
already do pretty much the same thing, let's call twl4030_usb_irq()
from twl4030_id_workaround_work() instead of adding some more
duplicate code.
The difference is the sysfs_notify() call, so now every time
id_workaround_work triggers (around once per second while the cable is
plugged) userspace will now get useless uevent. Haven't actually
checked if it really happens though, so I might be wrong.
Good point. That can be avoided by doing calling it only if we have
an irq and not from delayed work. Updated patch below, I've updated
the description for the proper regression causing commit and
added a check when to call the sysfs_notify. Kept Felipe's ack,
hope that works.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Thu, 21 Aug 2014 08:59:43 -0700
Subject: [PATCH] usb: phy: twl4030-usb: Fix lost interrupts after ID pin goes
down
Commit 249751f22380 (usb: phy: twl4030-usb: poll for ID disconnect)
added twl4030_id_workaround_work() to deal with lost interrupts
after ID pin goes down. Looks like commit f1ddc24c9e33 (usb: phy:
twl4030-usb: remove *set_suspend* and *phy_init* ops) changed
things around for the generic phy framework, and delayed work no
longer got called except initially during boot.
The PHY connect and disconnect interrupts for twl4030-usb are not
working after disconnecting a USB-A cable from the board, and the
deeper idle states for omap are blocked as the USB controller
stays busy.
The issue can be solved by calling delayed work from twl4030_usb_irq()
when ID pin is down and the PHY is not asleep like we already do
in twl4030_id_workaround_work().
But as both twl4030_usb_irq() and twl4030_id_workaround_work()
already do pretty much the same thing, let's call twl4030_usb_irq()
from twl4030_id_workaround_work() instead of adding some more
duplicate code. We also must call sysfs_notify() only when we have
an interrupt and not from the delayed work as notified by
Grazvydas Ignotas nota...@gmail.com.
Fixes: f1ddc24c9e33 (usb: phy: twl4030-usb: remove *set_suspend* and
*phy_init* ops)
Cc: sta...@vger.kernel.org # v3.13+
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -560,7 +560,15 @@ static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
*/
omap_musb_mailbox(status);
}
- sysfs_notify(twl-dev-kobj, NULL, vbus);
+
+ /* don't schedule during sleep - irq works right then */
+ if (status == OMAP_MUSB_ID_GROUND !twl-asleep) {
+ cancel_delayed_work(twl-id_workaround_work);
+ schedule_delayed_work(twl-id_workaround_work, HZ);
+ }
+
+ if (irq)
+ sysfs_notify(twl-dev-kobj, NULL, vbus);
return IRQ_HANDLED;
}
@@ -569,29 +577,8 @@ static void twl4030_id_workaround_work(struct work_struct
*work)
{
struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
id_workaround_work.work);
- enum omap_musb_vbus_id_status status;
- bool status_changed = false;
-
- status =
Re: [PATCH] usb: phy: twl4030-usb: Fix regressions to runtime PM on omaps
* Kishon Vijay Abraham I kis...@ti.com [140821 21:52]:
Kishon, this regression fix would be nice to get into the v3.17-rc
series if no objections. If you don't have other fixes, I can also
queue via arm-soc with proper acks.
I can queue this one up once put_autosuspend() is used.
Great, thanks, here's the updated version.
Regards,
Tony
8 --
From: Tony Lindgren t...@atomide.com
Date: Wed, 20 Aug 2014 12:07:00 -0700
Subject: [PATCH] usb: phy: twl4030-usb: Fix regressions to runtime PM on omaps
Commit 30a70b026b4cd (usb: musb: fix obex in g_nokia.ko causing kernel
panic) attempted to fix runtime PM handling for PHYs that are on the
I2C bus. Commit 3063a12be2b0 (usb: musb: fix PHY power on/off) then
changed things around to enable of PHYs that rely on runtime PM.
These changes however broke idling of the PHY and causes at least
100 mW extra power consumption on omaps, which is a lot with
the idle power consumption being below 10 mW range on many devices.
As calling phy_power_on/off from runtime PM calls in the USB
causes complicated issues with I2C connected PHYs, let's just let
the PHY do it's own runtime PM as needed. This leaves out the
dependency between PHYs and USB controller drivers for runtime
PM.
Let's fix the regression for twl4030-usb by adding minimal runtime
PM support. This allows idling the PHY on disconnect.
Note that we are changing to use standard runtime PM handling
for twl4030_phy_init() as that function just checks the state
and does not initialize the PHY. The PHY won't get initialized
until in twl4030_phy_power_on().
Fixes: 30a70b026b4cd (usb: musb: fix obex in g_nokia.ko causing kernel panic)
Fixes: 3063a12be2b0 (usb: musb: fix PHY power on/off)
Cc: sta...@vger.kernel.org # v3.15+
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -34,6 +34,7 @@
#include linux/delay.h
#include linux/usb/otg.h
#include linux/phy/phy.h
+#include linux/pm_runtime.h
#include linux/usb/musb-omap.h
#include linux/usb/ulpi.h
#include linux/i2c/twl.h
@@ -422,37 +423,55 @@ static void twl4030_phy_power(struct twl4030_usb *twl,
int on)
}
}
-static int twl4030_phy_power_off(struct phy *phy)
+static int twl4030_usb_runtime_suspend(struct device *dev)
{
- struct twl4030_usb *twl = phy_get_drvdata(phy);
+ struct twl4030_usb *twl = dev_get_drvdata(dev);
+ dev_dbg(twl-dev, %s\n, __func__);
if (twl-asleep)
return 0;
twl4030_phy_power(twl, 0);
twl-asleep = 1;
- dev_dbg(twl-dev, %s\n, __func__);
+
return 0;
}
-static void __twl4030_phy_power_on(struct twl4030_usb *twl)
+static int twl4030_usb_runtime_resume(struct device *dev)
{
+ struct twl4030_usb *twl = dev_get_drvdata(dev);
+
+ dev_dbg(twl-dev, %s\n, __func__);
+ if (!twl-asleep)
+ return 0;
+
twl4030_phy_power(twl, 1);
- twl4030_i2c_access(twl, 1);
- twl4030_usb_set_mode(twl, twl-usb_mode);
- if (twl-usb_mode == T2_USB_MODE_ULPI)
- twl4030_i2c_access(twl, 0);
+ twl-asleep = 0;
+
+ return 0;
+}
+
+static int twl4030_phy_power_off(struct phy *phy)
+{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
+ dev_dbg(twl-dev, %s\n, __func__);
+ pm_runtime_mark_last_busy(twl-dev);
+ pm_runtime_put_autosuspend(twl-dev);
+
+ return 0;
}
static int twl4030_phy_power_on(struct phy *phy)
{
struct twl4030_usb *twl = phy_get_drvdata(phy);
- if (!twl-asleep)
- return 0;
- __twl4030_phy_power_on(twl);
- twl-asleep = 0;
dev_dbg(twl-dev, %s\n, __func__);
+ pm_runtime_get_sync(twl-dev);
+ twl4030_i2c_access(twl, 1);
+ twl4030_usb_set_mode(twl, twl-usb_mode);
+ if (twl-usb_mode == T2_USB_MODE_ULPI)
+ twl4030_i2c_access(twl, 0);
/*
* XXX When VBUS gets driven after musb goes to A mode,
@@ -558,6 +577,16 @@ static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
* USB_LINK_VBUS state. musb_hdrc won't care until it
* starts to handle softconnect right.
*/
+ if ((status == OMAP_MUSB_VBUS_VALID) ||
+ (status == OMAP_MUSB_ID_GROUND)) {
+ if (twl-asleep)
+ pm_runtime_get_sync(twl-dev);
+ } else {
+ if (!twl-asleep) {
+ pm_runtime_mark_last_busy(twl-dev);
+ pm_runtime_put_autosuspend(twl-dev);
+ }
+ }
omap_musb_mailbox(status);
}
sysfs_notify(twl-dev-kobj, NULL, vbus);
@@ -599,22 +628,17 @@ static int twl4030_phy_init(struct phy *phy)
struct twl4030_usb *twl = phy_get_drvdata(phy);
enum omap_musb_vbus_id_status
Re: [PATCH] ARM: OMAP2+: fix gpmc_cs_remap: re-allocating chip-select address space based on DT
* Pekon Gupta pe...@ti.com [140723 11:20]:
Each GPMC chip-select needs to be configured for (base-address,CS-size) so
that
GPMC understands the address-space allocated to device connected externally.
These chip-select configurations (base-address, CS-size) follow some basic
mapping rules like:
- The CS size is programmable from 256 MBytes to 16 MBytes (must be a power
of 2)
and is defined by the mask field. Attached memory smaller than the
programmed
CS region size is accessed through the entire CS region (aliasing).
- The programmed 'base-address' must be aligned to the 'CS-size' boundary and
be a power of 2.
- Valid CS-size values are {256MB(max), 128MB, 64MB, 32MB and 16MB (min)}
Any intermediate values creates holes in the chip-select memory-map.
This patch adds above checks in gpmc_cs_remap() so that any invalid value
passed by DT reg property can be filtered before actually allocating the
address space.
Signed-off-by: Pekon Gupta pe...@ti.com
Looks like size typos Roger mentioned are fixed in this one, so
applying into omap-for-v3.17/fixes thanks.
Tony
---
arch/arm/mach-omap2/gpmc.c | 42 +-
1 file changed, 29 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc1338..4a4cc04 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -521,26 +521,42 @@ static int gpmc_cs_delete_mem(int cs)
* base. Returns 0 on success and appropriate negative error code
* on failure.
*/
-static int gpmc_cs_remap(int cs, u32 base)
+static int gpmc_cs_remap(int cs, u32 base, u32 size)
{
int ret;
- u32 old_base, size;
if (cs gpmc_cs_num) {
pr_err(%s: requested chip-select is disabled\n, __func__);
return -ENODEV;
}
- /*
- * Make sure we ignore any device offsets from the GPMC partition
- * allocated for the chip select and that the new base confirms
- * to the GPMC 16MB minimum granularity.
- */
- base = ~(SZ_16M - 1);
-
- gpmc_cs_get_memconf(cs, old_base, size);
- if (base == old_base)
- return 0;
+ /* allocate enough address-space under GPMC chip-select to device */
+ if (size SZ_256M) {
+ pr_err(%s: memory device 256MB not supported\n, __func__);
+ return -ENODEV;
+ } else if (size SZ_128M) {
+ WARN((size != SZ_256M), cs=%d: allocating 256MB\n, cs);
+ size = SZ_256M;
+ } else if (size SZ_64M) {
+ WARN((size != SZ_128M), cs=%d: allocating 128MB\n, cs);
+ size = SZ_128M;
+ } else if (size SZ_32M) {
+ WARN((size != SZ_64M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_64M;
+ } else if (size SZ_16M) {
+ WARN((size != SZ_32M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_32M;
+ } else {
+ WARN((size != SZ_16M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_16M;
+ }
+
+ /* base address should be aligned with address-space size */
+ if (base (size - 1)) {
+ pr_err(base-addr=%x should be aligned to size=%x, base, size);
+ return -EINVAL;
+ }
+
gpmc_cs_disable_mem(cs);
ret = gpmc_cs_delete_mem(cs);
if (ret 0)
@@ -1551,7 +1567,7 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
* CS to this location. Once DT migration is complete should
* just make gpmc_cs_request() map a specific address.
*/
- ret = gpmc_cs_remap(cs, res.start);
+ ret = gpmc_cs_remap(cs, res.start, resource_size(res));
if (ret 0) {
dev_err(pdev-dev, cannot remap GPMC CS %d to %pa\n,
cs, res.start);
--
1.8.5.1.163.gd7aced9
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Re: [PATCH] ARM: dts: DRA7: fix interrupt-cells for GPIO
* Nishanth Menon n...@ti.com [140818 11:49]:
On 07/30/2014 02:20 PM, Nishanth Menon wrote:
GPIO modules are also interrupt sources. However, they require both the
GPIO number and IRQ type to function properly.
By declaring that GPIO uses interrupt-cells=1, we essentially do not
allow users of the nodes to use the interrupt property appropritely.
With this change, the following now works:
interrupt-parent = gpio6;
interrupts = 5 IRQ_TYPE_LEVEL_LOW;
Fixes: 6e58b8f1daaf ('ARM: dts: DRA7: Add the dts files for dra7 SoC and
dra7-evm board')
Signed-off-by: Nishanth Menon n...@ti.com
---
Based on v3.16-rc7
arch/arm/boot/dts/dra7.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Tony,
Gentle ping. we still have this issue on 3.17-rc1. any suggestions on
if we can pick this up during RC?
Yes thanks applying into omap-for-v3.17/fixes.
Tony
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Re: [PATCH 01/19] ARM: OMAP: fix %d confusingly prefixed with 0x in format string
* Hans Wennborg h...@hanshq.net [140803 17:21]: Signed-off-by: Hans Wennborg h...@hanshq.net --- arch/arm/mach-omap2/id.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index d42022f..53841de 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void) default: /* Unknown default to latest silicon rev as default*/ - pr_warn(%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n, + pr_warn(%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n, __func__, idcode, hawkeye, rev); omap_revision = DRA752_REV_ES1_1; } Thanks applying into omap-for-v3.17/fixes. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP2+: omap_device: remove warning that clk alias already exists
* Markus Pargmann m...@pengutronix.de [140804 05:56]:
When an alias for a clock already exists the warning is printed. For
every module with a main_clk defined, a clk alias for fck is added.
There are some components that have the same main_clk defined, so this
is a really normal situation.
For example the am33xx edma device has 4 components using the same main
clock. So there are three warnings in the boot log for this already
existing clock alias:
platform 4900.edma: alias fck already exists
platform 4900.edma: alias fck already exists
platform 4900.edma: alias fck already exists
As this is only interesting for developers, this patch changes the
message to a debug message.
Signed-off-by: Markus Pargmann m...@pengutronix.de
---
arch/arm/mach-omap2/omap_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_device.c
b/arch/arm/mach-omap2/omap_device.c
index 01ef59def44b..d22c30d3ccfa 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char
*clk_alias,
r = clk_get_sys(dev_name(od-pdev-dev), clk_alias);
if (!IS_ERR(r)) {
- dev_warn(od-pdev-dev,
+ dev_dbg(od-pdev-dev,
alias %s already exists\n, clk_alias);
clk_put(r);
return;
Thanks applying into omap-for-v3.17/fixes.
Tony
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Re: [PATCH 1/3] mtd: nand: omap: Revert to using software ECC by default
* Grazvydas Ignotas nota...@gmail.com [140806 15:57]: On Wed, Aug 6, 2014 at 11:02 AM, Roger Quadros rog...@ti.com wrote: Hi Gražvydas, On 08/05/2014 07:15 PM, Grazvydas Ignotas wrote: On Tue, Aug 5, 2014 at 1:11 PM, Roger Quadros rog...@ti.com wrote: For v3.12 and prior, 1-bit Hamming code ECC via software was the default choice. Commit c66d039197e4 in v3.13 changed the behaviour to use 1-bit Hamming code via Hardware using a different ECC layout i.e. (ROM code layout) than what is used by software ECC. This ECC layout change causes NAND filesystems created in v3.12 and prior to be unusable in v3.13 and later. So revert back to using software ECC by default if an ECC scheme is not explicitely specified. This defect can be observed on the following boards during legacy boot -omap3beagle -omap3touchbook -overo -am3517crane -devkit8000 -ldp -3430sdp omap3pandora is also using sw ecc, with ubifs. Some time ago I tried booting mainline (I think it was 3.14) with rootfs on NAND, and while it did boot and reached a shell, there were lots of ubifs errors, fs got corrupted and I lost all my data. I used to be able to boot mainline this way fine sometime ~3.8 release. It's interesting that 3.14 was able to read the data, even with wrong ecc setup. This is due to another bug introduced in 3.7 by commit 65b97cf6b8deca3ad7a3e00e8316bb89617190fb. Because of that bug (i.e. inverted CS_MASK in omap_calculate_ecc), omap_calculate_ecc() always fails with -EINVAL and calculated ECC bytes are always 0. I'll be sending a patch to fix that as well. But that will only affect the cases where OMAP_ECC_HAM1_CODE_HW is used which happened for pandora from 3.13 onwards. Do you think it's safe again to boot ubifs created on 3.2 after applying this series? Yes. If you boot pandora using legacy boot (non DT method), it passes 0 for .ecc_opt in pandora_nand_data. This used to mean OMAP_ECC_HAMMING_CODE_DEFAULT which is software ecc. i.e. NAND_ECC_SOFT with default ECC layout. Until the above mentioned commits changed the meaning. We now call that option OMAP_ECC_HAM1_CODE_SW. Please let me know if it works for you. Thanks. Yes it does, thank you. Tested-by: Grazvydas Ignotas nota...@gmail.com OK thanks applying the whole series into omap-for-v3.17/fixes. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Remove twl6030 clk32g regulator
* Mark Brown broo...@kernel.org [140812 10:52]:
From: Mark Brown broo...@linaro.org
The kernel has never supported clk32g as a regulator since it is a clock
and not a regulator. Fortunately nothing actually references this node so
we can just remove it.
Signed-off-by: Mark Brown broo...@linaro.org
If not too late:
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/twl6030.dtsi | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 2e3bd3172b23..55eb35f068fb 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -83,10 +83,6 @@
regulator-always-on;
};
- clk32kg: regulator-clk32kg {
- compatible = ti,twl6030-clk32kg;
- };
-
twl_usb_comparator: usb-comparator {
compatible = ti,twl6030-usb;
interrupts = 4, 10;
--
2.0.1
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Re: [PATCH] ARM: dts: Remove twl6030 clk32g regulator
On Fri, Aug 22, 2014 at 04:13:00PM -0700, Tony Lindgren wrote: * Mark Brown broo...@kernel.org [140812 10:52]: The kernel has never supported clk32g as a regulator since it is a clock and not a regulator. Fortunately nothing actually references this node so we can just remove it. If not too late: Acked-by: Tony Lindgren t...@atomide.com Definitely not too late - indeed I'd have expected you to apply this. signature.asc Description: Digital signature
Re: [PATCH] ARM: dts: Remove twl6030 clk32g regulator
* Mark Brown broo...@kernel.org [140822 17:07]: On Fri, Aug 22, 2014 at 04:13:00PM -0700, Tony Lindgren wrote: * Mark Brown broo...@kernel.org [140812 10:52]: The kernel has never supported clk32g as a regulator since it is a clock and not a regulator. Fortunately nothing actually references this node so we can just remove it. If not too late: Acked-by: Tony Lindgren t...@atomide.com Definitely not too late - indeed I'd have expected you to apply this. Sure, let me know if you prefer me to pick it up. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Remove twl6030 clk32g regulator
On Fri, Aug 22, 2014 at 05:20:24PM -0700, Tony Lindgren wrote: * Mark Brown broo...@kernel.org [140822 17:07]: Acked-by: Tony Lindgren t...@atomide.com Definitely not too late - indeed I'd have expected you to apply this. Sure, let me know if you prefer me to pick it up. Yes, please. signature.asc Description: Digital signature
Re: [PATCH] gpio: omap: Fix interrupt names
Nishanth Menon n...@ti.com writes: When viewing the /proc/interrupts, there is no information about which GPIO bank a specific gpio interrupt is hooked on to. This is more than a bit irritating as such information can esily be provided back to the user and at times, can be crucial for debug. So, instead of displaying something like: 31: 0 0 GPIO 0 palmas 32: 0 0 GPIO 27 mmc0 Display the following with appropriate device name: 31: 0 0 4ae1.gpio 0 palmas 32: 0 0 4805d000.gpio 27 mmc0 This requires that we create irq_chip instance specific for each GPIO bank which is trivial to achieve. Signed-off-by: Nishanth Menon n...@ti.com Acked-by: Kevin Hilman khil...@linaro.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
