On Wed, Jan 14, 2015 at 11:04:19AM -0800, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [150113 17:28]:
On Tue, Jan 13, 2015 at 03:13:56PM -0800, Tony Lindgren wrote:
+
+#define TI81XX_PRM_DEVICE_RSTCTRL0x00a0
+#define TI81XX_GLOBAL_RST_COLD BIT(1)
+
+/**
* David Miller da...@davemloft.net [150113 13:08]:
From: Tony Lindgren t...@atomide.com
Date: Tue, 13 Jan 2015 11:54:16 -0800
* Tom Lendacky thomas.lenda...@amd.com [150113 11:51]:
On 01/13/2015 01:29 PM, Tony Lindgren wrote:
We only use clk_get() to get the frequency, the rest is done
Add the generic property hwlock-base-id to the hwspinlock DT nodes
on all applicable OMAP SoCS (OMAP4, OMAP5, DRA7, AM33xx and AM43xx).
This common property is required by the hwspinlock core to be able
to translate client locks properly. All the current OMAP SoCs only
have a single instance of
* Tony Lindgren t...@atomide.com [150113 15:29]:
Add minimal hwmod support that works at least on dm8168. This
is based on the code in the earlier TI CDP tree, and an earlier
patch by Aida Mynzhasova aida.mynzhas...@skitlab.ru.
I've set up things to work pretty much the same way as for
This patch adds the generic common bindings used to represent
a hwlock device and use/request locks in a device-tree build.
All the platform-specific hwlock driver implementations need the
number of locks and associated base id for registering the locks
present within the device with the driver
* Russell King - ARM Linux li...@arm.linux.org.uk [150114 09:54]:
On Wed, Dec 17, 2014 at 09:52:52AM +, Russell King - ARM Linux wrote:
The combined kernel boot follows a similar pattern, but yets a bit
further before oopsing, with ASoC DAPM code printing random bits of
kernel memory.
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
DT bindings information for OMAP hwspinlock module.
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Suman Anna s-a...@ti.com
---
v7: Added information about hwlock-base-id and
This patch adds two new OF helper functions for platform
implementations and one new API to use/request locks from a
hwspinlock device instantiated through a device-tree blob.
1. The of_hwspin_lock_get_num_locks() is a common OF helper
function to read the 'hwlock-num-locks' property.
2. The
Hi Ohad,
This is an updated version of the hwspinlock dt support series,
rebased onto v3.19-rc3 and mainly addresses the continued discussion
on the need to maintain a list of registered spinlock banks [1].
I have removed this patch as per your wish, and as a result the
burden of the spinlock
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
base support for parsing the DT nodes, and removes the code
dealing with the traditional platform device instantiation.
Signed-off-by: Suman Anna s-a...@ti.com
[t...@atomide.com:
* Felipe Balbi ba...@ti.com [150113 17:28]:
On Tue, Jan 13, 2015 at 03:13:56PM -0800, Tony Lindgren wrote:
+
+#define TI81XX_PRM_DEVICE_RSTCTRL 0x00a0
+#define TI81XX_GLOBAL_RST_COLD BIT(1)
+
+/**
+ * ti81xx_restart - trigger a software restart of the SoC
+ * @mode: the
Quoting Tony Lindgren (2015-01-13 14:51:26)
Hi all,
Here's a minimal support for the FAPLL (Flying Adder PLL) on dm816x
which is a omap variant.
Tony,
Patches look fine to me. I'll give it a few days for Paul or Tero to
comment if they have any concerns.
Also, flying adder pll is a pretty
* Sergei Shtylyov sergei.shtyl...@cogentembedded.com [150114 05:54]:
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
Heh thanks will updated to:
This allows booting ti81xx boards when a .dts file
* Marc Zyngier marc.zyng...@arm.com [150112 10:30]:
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW
On Wed, Jan 14, 2015 at 11:09:26AM -0800, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [150114 09:54]:
On Wed, Dec 17, 2014 at 09:52:52AM +, Russell King - ARM Linux wrote:
The combined kernel boot follows a similar pattern, but yets a bit
further before
We've had omap4 booting in DT only mode for quite some time
now, let's remove the legacy PMIC code that's no longer
needed.
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -39,7 +39,7 @@ static struct i2c_board_info
On Sat, Jan 10, 2015 at 03:15:39PM +0100, Belisko Marek wrote:
Ping for input maintainer. DT changes was acked. Thanks.
On Tue, Sep 30, 2014 at 10:17 PM, Marek Belisko ma...@goldelico.com wrote:
This patch adds new parameters that allow to address typical hardware
design differences: touch
Hi all,
Looks like the legacy IRQ numbers are now all wrong at least for omap4
since commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain.).
Instead of this:
# cat /proc/interrupts
CPU0 CPU1
29: 1124981 GIC 29 twd
39: 0
* Tony Lindgren t...@atomide.com [150114 11:16]:
* Russell King - ARM Linux li...@arm.linux.org.uk [150114 09:54]:
On Wed, Dec 17, 2014 at 09:52:52AM +, Russell King - ARM Linux wrote:
The combined kernel boot follows a similar pattern, but yets a bit
further before oopsing, with ASoC
On Wed, Jan 14, 2015 at 02:39:55PM +0530, Amit Virdi wrote:
Alright, I just applied your patches to testing/fixes. I'll start
testing today and should be able to send a pull request to Greg by the
end of the week, hopefully.
Thanks! Just a small clarification - git failed to send patches
Hi,
In 3.19-rc4 on dra7-evm or dra72-evm
modprobe g_zero
[ 34.680683] zero gadget: Gadget Zero, version: Cinco de Mayo 2008
[ 34.687074] zero gadget: zero ready
[ 34.694133] dwc3 4889.usb: failed to enable ep0out
[ 34.701600] zero 4889.usb: failed to start zero: -110
ERROR: could
Hi,
Am 15.01.2015 um 01:59 schrieb Dmitry Torokhov dmitry.torok...@gmail.com:
On Sat, Jan 10, 2015 at 03:15:39PM +0100, Belisko Marek wrote:
Ping for input maintainer. DT changes was acked. Thanks.
On Tue, Sep 30, 2014 at 10:17 PM, Marek Belisko ma...@goldelico.com wrote:
This patch adds
On Wednesday 14 January 2015 10:28 PM, Felipe Balbi wrote:
CPSW never uses RX_THRESHOLD or MISC interrupts. In
fact, they are always kept masked in their appropriate
IRQ Enable register.
Instead of allocating an IRQ that never fires, it's best
to remove that code altogether and let future
on Exynos5250, using kgene/for-next and
linux-next/next-20150114, but S2R failed on Exynos5250 based SMDK board.
Following is the log I got on SMDK5250 board, (note I have added some
debugging log to know what is happening)
I can see is S3C-RTC's enable_irq_wake is failing with error -6.
I also observed
On Wed, Jan 14, 2015 at 04:46:03PM +0100, Alexandre Belloni wrote:
Hi,
This patch set hasn't moved since while. We actually need patch 4 to
properly configure prefetch on sama5d4. What would be needed to come to
an agreement ?
What do you mean hasn't moved since a while - there has been
Hi,
This patch set hasn't moved since while. We actually need patch 4 to
properly configure prefetch on sama5d4. What would be needed to come to
an agreement ?
On 24/09/2014 at 13:05:34 +0200, Marek Szyprowski wrote :
This is an updated patchset, which intends to add support for L2 cache
on
On Wed, Dec 17, 2014 at 09:52:52AM +, Russell King - ARM Linux wrote:
The combined kernel boot follows a similar pattern, but yets a bit
further before oopsing, with ASoC DAPM code printing random bits of
kernel memory.
Note that the combined kernel (which is OMAP4 + Versatile Express)
has
Hi,
On 14/01/2015 at 16:21:50 +, Russell King - ARM Linux wrote :
On Wed, Jan 14, 2015 at 04:46:03PM +0100, Alexandre Belloni wrote:
Hi,
This patch set hasn't moved since while. We actually need patch 4 to
properly configure prefetch on sama5d4. What would be needed to come to
an
Now we can introduce dedicated IRQ handlers
for each of the IRQ events. This helps with
cleaning up a little bit of the clutter in
cpsw_interrupt() while also making sure that
TX IRQs will try to handle TX buffers while
RX IRQs will try to handle RX buffers.
Signed-off-by: Felipe Balbi
CPSW never uses RX_THRESHOLD or MISC interrupts. In
fact, they are always kept masked in their appropriate
IRQ Enable register.
Instead of allocating an IRQ that never fires, it's best
to remove that code altogether and let future patches
implement it if anybody needs those.
Signed-off-by:
Hi,
On Wed, Jan 14, 2015 at 03:08:43PM +0800, Sneeker Yeh wrote:
Hi Felipe:
thanks for suggestion,
2015-01-13 1:20 GMT+08:00 Felipe Balbi ba...@ti.com:
Hi,
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
enable the quirk only for you. Isn't there a better way of
* Felipe Balbi ba...@ti.com [150112 08:50]:
Hi,
On Thu, Jan 08, 2015 at 10:25:12AM -0600, Felipe Balbi wrote:
On Tue, Jan 06, 2015 at 11:37:34AM -0600, Felipe Balbi wrote:
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
Hi,
On Wed, Jan 14, 2015 at 05:44:08PM +0200, Roger Quadros wrote:
In 3.19-rc4 on dra7-evm or dra72-evm
modprobe g_zero
[ 34.680683] zero gadget: Gadget Zero, version: Cinco de Mayo 2008
[ 34.687074] zero gadget: zero ready
[ 34.694133] dwc3 4889.usb: failed to enable ep0out
[
* Felipe Balbi ba...@ti.com [150113 17:25]:
On Tue, Jan 13, 2015 at 03:13:52PM -0800, Tony Lindgren wrote:
We need to check if we got the clock before trying to do anything
with it. Otherwise we will get something like this:
Unable to handle kernel paging request at virtual address
This patch is in preparation for a nicer IRQ
handling scheme where we use different IRQ
handlers for each IRQ line (as it should be).
Later, we will also drop IRQs offset 0 and 3
because they are always disabled in this driver.
Signed-off-by: Felipe Balbi ba...@ti.com
---
* Felipe Balbi ba...@ti.com [150113 17:23]:
On Tue, Jan 13, 2015 at 03:13:51PM -0800, Tony Lindgren wrote:
The support for 81xx was never working in mainline, and it
will be only supported in device tree mode. Let's remove all
the remaining 81xx related platform code.
you should probably
Alright, I just applied your patches to testing/fixes. I'll start
testing today and should be able to send a pull request to Greg by the
end of the week, hopefully.
Thanks! Just a small clarification - git failed to send patches to
stable kernel list again (unfortunately I used the older
On 01/14/2015 08:57 AM, Jean-Francois Moine wrote:
On Tue, 13 Jan 2015 19:12:25 +0200
Jyri Sarha jsa...@ti.com wrote:
These patches are needed for Beaglebone-back HDMI audio. There is no
direct dependency between these patches and the other (dts and ASoC)
changes needed for the HDMI audio so
On Mon, Jan 5, 2015 at 7:26 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Thursday 18 December 2014 07:41 PM, Nishanth Menon wrote:
On 12/18/2014 12:18 AM, Kishon Vijay Abraham I wrote:
On Tuesday 16 December 2014 02:20 AM, Nishanth Menon wrote:
On 12/12/2014 02:06 AM, Kishon Vijay
On Thursday 27 November 2014 04:11 PM, Peter Ujfalusi wrote:
Hi,
The linux/platform_data/edma.h file was used for API definition as well, which
is not correct since the header should only contain platform data related
structures, defines, etc.
I would like to queue this series through
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
file is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
WBR, Sergei
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To unsubscribe from this
On 14/01/15 01:46, Paul Walmsley wrote:
On Wed, 7 Jan 2015, Roger Quadros wrote:
From: Paul Walmsley p...@pwsan.com
Date: Mon, 5 Jan 2015 15:49:57 -0700
Subject: [PATCH] Only skip ioremap() if IP block does not have OCP header
registers. Experimental.
---
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