Hi!
The USB Battery Charging spec (BC1.2) suggests a dedicated
charging port can deliver from 0.5 to 5.0A at between 4.75 and 5.25
volts.
To choose the correct current voltage setting requires a trial
and error approach: try to draw current and see if the voltage drops
too
Hi Pavel,
Am 04.04.2015 um 10:16 schrieb Pavel Machek pa...@ucw.cz:
Hi!
Please propose your own code doing that so that we can test if it is
better.
So, how does this look?
It looks to me like you have cca 0.1 Ohm resistance in your system,
This is completely unknown.
and are
Hi Pavel,
On Sat, Apr 04, 2015 at 09:43:37AM +0200, Pavel Machek wrote:
Documentation for adp1653 binding.
s/binding/bindings/
Signed-off-by: Pavel Machek pa...@ucw.cz
---
Please apply.
Sorry, wrong version of patch was sent last time.
Documentation for adp1653 binding.
Signed-off-by: Pavel Machek pa...@ucw.cz
---
Please apply.
Sorry, wrong version of patch was sent last time.
Pavel
diff --git a/Documentation/devicetree/bindings/media/i2c/adp1653.txt
Hi!
Please propose your own code doing that so that we can test if it is
better.
So, how does this look?
It looks to me like you have cca 0.1 Ohm resistance in your system,
This is completely unknown.
and are using cca 75mA while discharging, and charge by cca 1.4A.
Where
Russell King rmk+ker...@arm.linux.org.uk writes:
clk_add_alias() is provided by clkdev, and is not part of the clk API.
Howver, it is prototyped in two locations: linux/clkdev.h and
linux/clk.h. This is a mess. Get rid of the redundant and unnecessary
version in linux/clk.h.
On Sat, Apr 04, 2015 at 02:43:22PM +0200, Robert Jarzmik wrote:
Russell King rmk+ker...@arm.linux.org.uk writes:
clk_add_alias() is provided by clkdev, and is not part of the clk API.
Howver, it is prototyped in two locations: linux/clkdev.h and
linux/clk.h. This is a mess. Get rid of
Hi all,
To my surprise, the am335x clock tree (am33xx-clocks.dtsi) currently
lists the functional clock of the AES accelerator and other crypto
modules to be the (max 26 MHz) main osc. This struck me as rather
unlikely, since the AES module is clocked much higher on other
devices, and such a slow
On 4 April 2015 at 00:52, Tony Lindgren t...@atomide.com wrote:
Right, it affects n900 for sure. My point is that it also seems to
affect 37xx versions not listed to suffer from this issue.
They shouldn't... erratum 430973 only affected Cortex-A8 r1, and the
dm37xx should have an r3p2 right?
A
Hi!
enable-gpios: Specifier of the GPIO connected to EN pin
I can make the changes if you're ok with that, otherwise please send v7. Then
I'll apply that to my tree.
I'm ok with that.
Thanks,
Pavel
--
(english)
On Sat, Apr 04, 2015 at 07:11:16PM +0200, Pavel Machek wrote:
Hi!
enable-gpios: Specifier of the GPIO connected to EN pin
I can make the changes if you're ok with that, otherwise please send v7.
Then
I'll apply that to my tree.
I'm ok with that.
Thanks. The patch is applied
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