The AEAD speed tests doesn't do a wait_for_completition,
if the return value is EINPROGRESS or EBUSY.
Fixing it here.
Also add a test case for gcm(aes).
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
crypto/tcrypt.c | 65 ++---
1 file
AES_CTRL_REG is used to configure AES mode. Before configuring
any mode we need to make sure all other modes are reset or else
driver will misbehave. So mask all modes before configuring
any AES mode.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 13 +
On 07/07/2015 05:37 PM, Roger Quadros wrote:
On 07/07/15 17:35, Roger Quadros wrote:
On 07/07/15 17:33, Marc Kleine-Budde wrote:
On 07/07/2015 04:27 PM, Roger Quadros wrote:
From: J.D. Schroeder jay.schroe...@garmin.com
The previous change 3973c526ae9c (net: can: c_can: Disable pins when
CAN
Algo self tests are failing for CTR mode with omap-aes driver,
giving the following error:
[ 150.053644] omap_aes_crypt: request size is not exact amount of AES
blocks
[ 150.061262] alg: skcipher: encryption failed on test 5 for ctr-aes-omap:
ret=22
This is because the input length is
Hi Tony, Sebastian,
On 07/01/2015 02:29 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150701 00:34]:
This should be OK for most cases as the GPIO interrupt devices are
typically on some external bus like I2C or GPMC. The hurting case
would be bitbanging GPIO devices, like the
On Monday 06 July 2015 06:53:18 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150706 06:27]:
On Tuesday 28 October 2014 23:26:41 Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [141028 15:22]:
On Tue 2014-10-28 23:04:50, Pavel Machek wrote:
Networking now works
* Tero Kristo t-kri...@ti.com [150707 00:25]:
On 07/06/2015 06:25 PM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [150706 08:14]:
On DRA7 there is one pinctrl domain (dra7_pmx_core) and
PRCM wake-up IRQ is not shared, so remove quirk.
Cc: Nishanth Menon n...@ti.com
On 07/06/2015 06:25 PM, Tony Lindgren wrote:
* Grygorii Strashko grygorii.stras...@ti.com [150706 08:14]:
On DRA7 there is one pinctrl domain (dra7_pmx_core) and
PRCM wake-up IRQ is not shared, so remove quirk.
Cc: Nishanth Menon n...@ti.com
Cc: Tony Lindgren t...@atomide.com
Fixes:
* Rafael J. Wysocki r...@rjwysocki.net [150706 15:49]:
On Monday, July 06, 2015 01:01:18 PM Felipe Balbi wrote:
on a first call to dev_pm_attach_wake_irq(), if it
fails, it will leave dev-power.wakeirq set to a
dangling pointer. Instead, let's clear it to make
sure a subsequent call to
On Tue, Jul 07, 2015 at 12:40:53AM -0700, Tony Lindgren wrote:
* Rafael J. Wysocki r...@rjwysocki.net [150706 15:49]:
On Monday, July 06, 2015 01:01:18 PM Felipe Balbi wrote:
on a first call to dev_pm_attach_wake_irq(), if it
fails, it will leave dev-power.wakeirq set to a
dangling
Clock rates are stored in an unsigned long field, but -determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.
Change -determine_rate() prototype to
On Tuesday 07 July 2015 17:02:30 Sebastian Reichel wrote:
Hi,
On Mon, Jul 06, 2015 at 09:44:22PM +0200, Pali Rohár wrote:
now I found out that rx51-battery.ko driver register sysnode
/sys/class/power_supply/rx51-battery/ when booting with legacy board
code. But when booting DT kernel
This series does some basic cleanup and adds support for
AES GCM mode for omap aes driver.
Changes since v1:
- Switched GCM to new AEAD interface
Lokesh Vutla (7):
crypto: omap-aes: Fix CTR mode
crypto: omap-aes: Increase priority of hw accelerator
crypto: omap-aes: Fix configuring of AES
Increasing the priority of omap-aes hw algos, in order to take
precedence over sw algos.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
Add aead_request_cast() api to get pointer to aead_request
from cryto_async_request.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
include/crypto/internal/aead.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/crypto/internal/aead.h b/include/crypto/internal/aead.h
index
OMAP AES hw supports AES-GCM mode.
Adding support for GCM mode in omap-aes driver.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/Kconfig| 1 +
drivers/crypto/Makefile | 3 +-
drivers/crypto/omap-aes-gcm.c | 376 ++
Use BIT()/GENMASK() macros for all register definitions instead of
hand-writing bit masks.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
On 08.07.2015 05:02, Joel Porquet wrote:
The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h', making it
globally accessible.
See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d
(irqchip: Move IRQCHIP_DECLARE macro to include/linux/irqchip.h).
This patch adds inclusions of
On Mon, 2015-07-06 at 17:46 +0300, Roger Quadros wrote:
-static int find_cable_index_by_name(struct extcon_dev *edev, const char
*name)
+static int find_cable_id_by_name(struct extcon_dev *edev, const char *name)
{
- unsigned int id = EXTCON_NONE;
+ unsigned int id =
On 06/22/2015 09:22 AM, Keerthy wrote:
The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded.
This makes it difficult to reuse the code for single core SoCs like AM437x.
Single core vs. having two sets of IRQENABLE / IRQSTATUS registers do
not have any relation to each
On 07/06/2015 09:11 AM, Vignesh R wrote:
On Wednesday 03 June 2015 05:21 PM, Vignesh R wrote:
Hi,
This patch series adds support for PWMSS on DRA7. The IP is same as that
present in AM33XX and AM43XX.
The first patch changes clock domain in which PWMSS is present
(l4per2_7xx_clkdm) to
* John Stultz john.stu...@linaro.org [150706 10:53]:
On Mon, Jul 6, 2015 at 8:46 AM, Thomas Gleixner t...@linutronix.de wrote:
On Mon, 6 Jul 2015, Tony Lindgren wrote:
* Thomas Gleixner t...@linutronix.de [150706 07:20]:
On Mon, 6 Jul 2015, Tony Lindgren wrote:
The timekeeping accuracy
* Pali Rohár pali.ro...@gmail.com [150707 00:48]:
On Monday 06 July 2015 06:53:18 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150706 06:27]:
On Tuesday 28 October 2014 23:26:41 Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [141028 15:22]:
On Tue 2014-10-28 23:04:50,
On Tuesday 07 July 2015 12:32:13 Russell King - ARM Linux wrote:
On Mon, Jul 06, 2015 at 10:26:13PM +0200, Pali Rohár wrote:
Legacy bootloaders can pass additional information for kernel or legacy
userspace applications. When booting DT kernel then ATAGs structure is not
more visible after
On Tuesday 07 July 2015 05:21 PM, Tero Kristo wrote:
On 06/22/2015 09:22 AM, Keerthy wrote:
The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are
hardcoded.
This makes it difficult to reuse the code for single core SoCs like
AM437x.
Single core vs. having two sets of IRQENABLE /
On 06/22/2015 09:22 AM, Keerthy wrote:
Add the PRM IRQ register offsets.
This patch doesn't apply cleanly to 4.2-rc1.
-Tero
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/prcm43xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/prcm43xx.h
On Mon, Jul 06, 2015 at 10:26:13PM +0200, Pali Rohár wrote:
Legacy bootloaders can pass additional information for kernel or legacy
userspace applications. When booting DT kernel then ATAGs structure is not
more visible after running kernel uncompress code. This patch stores full
ATAGs
On Mon 2015-07-06 21:44:22, Pali Rohár wrote:
Hello,
now I found out that rx51-battery.ko driver register sysnode
/sys/class/power_supply/rx51-battery/ when booting with legacy board
code. But when booting DT kernel it register sysnode with different name
On Tue, Jul 7, 2015 at 10:11 AM, Felipe Balbi ba...@ti.com wrote:
On Tue, Jul 07, 2015 at 12:40:53AM -0700, Tony Lindgren wrote:
* Rafael J. Wysocki r...@rjwysocki.net [150706 15:49]:
On Monday, July 06, 2015 01:01:18 PM Felipe Balbi wrote:
on a first call to dev_pm_attach_wake_irq(), if it
* John Stultz john.stu...@linaro.org [150706 10:55]:
On Mon, Jul 6, 2015 at 10:34 AM, Thomas Gleixner t...@linutronix.de wrote:
On Mon, 6 Jul 2015, John Stultz wrote:
On Mon, Jul 6, 2015 at 12:12 AM, Tony Lindgren t...@atomide.com wrote:
Some persistent clocksources can be on a slow
The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h', making it
globally accessible.
See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d
(irqchip: Move IRQCHIP_DECLARE macro to include/linux/irqchip.h).
This patch adds inclusions of 'include/linux/irqchip.h' and replaces uses of
macro
On 07/07, Boris Brezillon wrote:
Clock rates are stored in an unsigned long field, but -determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.
On Tue, 2015-07-07 at 16:06 +0300, Roger Quadros wrote:
Users of find_cable_index_by_name() will cause a kernel hang
as the while loop counter is never incremented and end condition
is never reached.
extcon_get_cable_state() and extcon_set_cable_state() are broken
because they use cable
Users of find_cable_index_by_name() will cause a kernel hang
as the while loop counter is never incremented and end condition
is never reached.
extcon_get_cable_state() and extcon_set_cable_state() are broken
because they use cable index instead of cable id. This causes
the first cable state
Hi,
On 07/07/15 15:40, Ivan T. Ivanov wrote:
On Mon, 2015-07-06 at 17:46 +0300, Roger Quadros wrote:
-static int find_cable_index_by_name(struct extcon_dev *edev, const char *name)
+static int find_cable_id_by_name(struct extcon_dev *edev, const char *name)
{
- unsigned int id =
On Tue, Jul 07, 2015 at 09:01:47PM +0530, Lokesh Vutla wrote:
Add aead_request_cast() api to get pointer to aead_request
from cryto_async_request.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
include/crypto/internal/aead.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Tue, Jul 07, 2015 at 09:01:48PM +0530, Lokesh Vutla wrote:
+static int omap_aes_gcm_copy_buffers(struct omap_aes_dev *dd,
+ struct aead_request *req)
+{
+ void *buf_in;
+ int pages, alen, clen, cryptlen, nsg;
+ struct crypto_aead *aead =
Enable IO wakeup feature.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/prm_common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 7add799..1730fc4 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++
The patch series adds IO wake up support for AM437x series
making use of the existing OMAP4 support. Adds the AM437x
specifics.
The series is boot tested on OMAP4 panda, DAR7 evm and AM437x evms.
Changes in v2:
Removed inefficient way of using arrays for irq ack and masks.
Keerthy (6):
ARM:
Add the PRM IRQ register offsets.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/prcm43xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7eebc27..d716d2e 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
Add PRCM IRQ entry.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c80a3e2..637133b 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++
The register offsets for some of the PRM Registers are different
hence populating the differing fields.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c
The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded.
This makes it difficult to reuse the code for SoCs like AM437x that have
a single instance of IRQENABLE_MPU and IRQSTATUS_MPU registers.
Hence handling the case using offset of 4 to accommodate single set of IRQ*
registers
PRM_IO_PMCTRL_OFFSET need not be same for all SOCs hence
remove hardcoding and use the value provided by the omap_prcm_irq_setup
structure.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/prcm-common.h | 1 +
arch/arm/mach-omap2/prm44xx.c | 11 ++-
2 files changed, 7
Driver core sets default pinmux on on probe and CAN driver
sets sleep pinmux during register. This causes a small window
where the CAN pins are in default state with the DCAN module
being disabled.
Change the default state to be like sleep so this glitch is
avoided. Add a new active state that is
Hi,
If default pins are active for CAN then there is a slight
window during boot when CAN pins are in active mode and can
affect DRA7 CAN stability. This is because device core
automatically selects default before probe.
These patches change default pins to inactive and adds
a new active pin
Hi,
On Mon, Jul 06, 2015 at 09:44:22PM +0200, Pali Rohár wrote:
now I found out that rx51-battery.ko driver register sysnode
/sys/class/power_supply/rx51-battery/ when booting with legacy board
code. But when booting DT kernel it register sysnode with different name
From: J.D. Schroeder jay.schroe...@garmin.com
The previous change 3973c526ae9c (net: can: c_can: Disable pins when CAN
interface
is down) causes a slight glitch on the pinctrl settings when used. Since
commit ab78029 (drivers/pinctrl: grab default handles from device core),
the device core will
On 07/07/2015 04:27 PM, Roger Quadros wrote:
From: J.D. Schroeder jay.schroe...@garmin.com
The previous change 3973c526ae9c (net: can: c_can: Disable pins when CAN
interface
is down) causes a slight glitch on the pinctrl settings when used. Since
commit ab78029 (drivers/pinctrl: grab
On 07/07/15 17:33, Marc Kleine-Budde wrote:
On 07/07/2015 04:27 PM, Roger Quadros wrote:
From: J.D. Schroeder jay.schroe...@garmin.com
The previous change 3973c526ae9c (net: can: c_can: Disable pins when CAN
interface
is down) causes a slight glitch on the pinctrl settings when used. Since
On 07/07/15 17:35, Roger Quadros wrote:
On 07/07/15 17:33, Marc Kleine-Budde wrote:
On 07/07/2015 04:27 PM, Roger Quadros wrote:
From: J.D. Schroeder jay.schroe...@garmin.com
The previous change 3973c526ae9c (net: can: c_can: Disable pins when
CAN interface
is down) causes a slight glitch on
On 07/07/2015 04:37 PM, Roger Quadros wrote:
diff --git a/drivers/net/can/c_can/c_can.c
b/drivers/net/can/c_can/c_can.c
index 041525d..66e98e7 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -605,7 +605,18 @@ static int c_can_start(struct net_device *dev)
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