On Wed, 14 Oct 2015, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 01:58 AM, Roger Quadros wrote:
> > On 13/10/15 16:44, Franklin S Cooper Jr wrote:
> >> ELM address information is provided by device tree. No longer need
> >> to include this information within hwmod.
> >>
> >> Signed-off-by:
Add AM438x compatible property to identify the SoCs on epos evms.
Signed-off-by: Keerthy
---
Changes in v2:
* Rebased to latest 4.3-rc5
Documentation/devicetree/bindings/arm/omap/omap.txt | 5 -
arch/arm/boot/dts/am43x-epos-evm.dts| 2 +-
2 files changed, 5 insertions(+)
Currently everytime soc_is calls are made, firstly device tree nodes
are parsed and then string comparisons are made to determine the
soc version. Optimizing it to be done one time and store the result.
Use the stored value in all the subsequent checks for soc_is calls.
Signed-off-by: Keerthy
---
The series implements optimizing soc_is calls for DRA7 and AM43XX
family of SoCs. Originally the soc_is calls for DRA7 involved parsing
device tree nodes and some repetitive string comparisons. Optimizing
to store the result and use the result in the subsequent calls.
The series is boot tested on
Currently everytime soc_is calls are made, firstly device tree nodes
are parsed and then string comparisons are made to determine the
soc version. Optimizing it to be done one time and store the result.
Use the stored value in all the subsequent checks for soc_is calls.
Signed-off-by: Keerthy
---
Hello Tony,
Am 15.10.2015 um 00:20 schrieb Tony Lindgren:
* Tony Lindgren [151014 10:56]:
* Heiko Schocher [151012 22:58]:
Of this, secure content (including PPA) uses initial
portion of the SRAM. This chunk is not (and shouldn't
be) accessible from the public code.
The minimum size of this
Hello Tony,
Am 14.10.2015 um 19:49 schrieb Tony Lindgren:
* Heiko Schocher [151012 22:58]:
Of this, secure content (including PPA) uses initial
portion of the SRAM. This chunk is not (and shouldn't
be) accessible from the public code.
The minimum size of this chunk (0x350) is used in this
pat
On Wed, Oct 14, 2015 at 06:02:18PM +0300, Peter Ujfalusi wrote:
> On 10/14/2015 05:41 PM, Vinod Koul wrote:
> > On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
> >> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
> >> *edma_prep_dma_memcpy(
> >>struct dma_chan *ch
* Tony Lindgren [151014 15:27]:
> * Tony Lindgren [151014 10:56]:
> > * Heiko Schocher [151012 22:58]:
> > > Of this, secure content (including PPA) uses initial
> > > portion of the SRAM. This chunk is not (and shouldn't
> > > be) accessible from the public code.
> > >
> > > The minimum size o
* Tony Lindgren [151014 10:56]:
> * Heiko Schocher [151012 22:58]:
> > Of this, secure content (including PPA) uses initial
> > portion of the SRAM. This chunk is not (and shouldn't
> > be) accessible from the public code.
> >
> > The minimum size of this chunk (0x350) is used in this
> > patch.
On 10/14/2015 04:48 PM, Lucas Stach wrote:
> Install a non-faulting handler just before unmasking imprecise aborts
> and switch back to the regular one after unmasking is done.
>
> This catches any pending imprecise abort that the firmware/bootloader
> may have left behind that would normally cras
On 10/14/2015 04:48 PM, Lucas Stach wrote:
> This is not needed anymore. Handling a potentially pending imprecise external
> abort left behind by the bootloader is now done in a slightly safer way inside
> the common ARM startup code.
>
> Signed-off-by: Lucas Stach
Acked-by: Hauke Mehrtens
I te
The following changes since commit 049e6dde7e57f0054fdc49102e7ef4830c698b46:
Linux 4.3-rc4 (2015-10-04 16:57:17 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
tags/omap-for-v4.4/dt-pt1
for you to fetch changes up to be14641250
The following changes since commit 049e6dde7e57f0054fdc49102e7ef4830c698b46:
Linux 4.3-rc4 (2015-10-04 16:57:17 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
tags/omap-for-v4.4/cleanup-pt1
for you to fetch changes up to d42f2
Lucas,
On Wed, 14 Oct 2015 16:48:32 +0200, Lucas Stach wrote:
> This is not needed anymore. Handling a potentially pending imprecise external
> abort left behind by the bootloader is now done in a slightly safer way inside
> the common ARM startup code.
>
> Signed-off-by: Lucas Stach
> ---
> ar
* Suman Anna [151014 13:32]:
> On 10/14/2015 03:12 PM, Arnd Bergmann wrote:
> > On Wednesday 14 October 2015 09:17:56 Tony Lindgren wrote:
> >> * Arnd Bergmann [151014 02:20]:
> >>> On Tuesday 13 October 2015 16:13:20 Tony Lindgren wrote:
> On boards with more than 2GB of RAM booting goes wr
On 10/14/2015 03:12 PM, Arnd Bergmann wrote:
> On Wednesday 14 October 2015 09:17:56 Tony Lindgren wrote:
>> * Arnd Bergmann [151014 02:20]:
>>> On Tuesday 13 October 2015 16:13:20 Tony Lindgren wrote:
On boards with more than 2GB of RAM booting goes wrong with things not
working
a
On Wednesday 14 October 2015 09:17:56 Tony Lindgren wrote:
> * Arnd Bergmann [151014 02:20]:
> > On Tuesday 13 October 2015 16:13:20 Tony Lindgren wrote:
> > > On boards with more than 2GB of RAM booting goes wrong with things not
> > > working
> > > and we're getting lots of l3 warnings:
> > >
On 10/14/2015 01:13 PM, Tony Lindgren wrote:
> * Franklin S Cooper Jr. [151014 09:27]:
>>
>> On 10/14/2015 11:18 AM, Tony Lindgren wrote:
>>> * Franklin S Cooper Jr. [151014 07:37]:
On 10/14/2015 09:11 AM, Roger Quadros wrote:
> On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>> On
The following changes since commit 25cb62b76430a91cc6195f902e61c2cb84ade622:
Linux 4.3-rc5 (2015-10-11 11:09:45 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
tags/omap-for-v4.3/fixes-rc5
for you to fetch changes up to d8e1f5e
* Tero Kristo [151014 04:52]:
> Remove the OMAP3 core DPLL re-program code, and the associated SRAM
> code that does the low-level programming of the DPLL divider, idling
> of the SDRAM etc.
>
> This code was never fully implemented in the kernel; things missing
> were driver side handling of cor
* Javier Martinez Canillas [151013 10:43]:
> Hello Laurent,
>
> Thanks a lot for the patch.
>
> On Tue, Oct 13, 2015 at 7:31 PM, Laurent Pinchart
> wrote:
> > Use the macro instead of absolute register offsets to make the code more
> > readable as the values now match register addresses from th
* Mark Jackson [151014 06:35]:
> Add USB hooks into NanoBone DTS file
Hmm looking at things, we really should not set status = "disabled"
for any of the internal devices. Setting "disabled" makes the kernel
completely ignore the device and we're better off from PM point of
view to probe and idle
* Franklin S Cooper Jr. [151014 09:27]:
>
>
> On 10/14/2015 11:18 AM, Tony Lindgren wrote:
> > * Franklin S Cooper Jr. [151014 07:37]:
> >>
> >> On 10/14/2015 09:11 AM, Roger Quadros wrote:
> >>> On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
> On 10/14/2015 06:52 AM, Roger Quadros wrote:
On 10/14/2015 12:19 PM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
On 10/14/2015 12:05 PM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Felipe,
On 10/14/2015 11:25 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
On 10/14/2015 10:56 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Hi,
On 10/
* Heiko Schocher [151012 22:58]:
> Of this, secure content (including PPA) uses initial
> portion of the SRAM. This chunk is not (and shouldn't
> be) accessible from the public code.
>
> The minimum size of this chunk (0x350) is used in this
> patch. Available size is rounded off to 63K.
>
> Bot
Hi,
Bin Liu writes:
> On 10/14/2015 12:05 PM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Bin Liu writes:
>>> Felipe,
>>>
>>> On 10/14/2015 11:25 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
> On 10/14/2015 10:56 AM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Bin Liu w
On 10/14/2015 12:05 PM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Felipe,
On 10/14/2015 11:25 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
On 10/14/2015 10:56 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Hi,
On 10/13/2015 01:22 PM, Felipe Balbi wrote:
Yegor Yefremov writes:
On Mo
Hi,
Bin Liu writes:
> Felipe,
>
> On 10/14/2015 11:25 AM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Bin Liu writes:
>>> On 10/14/2015 10:56 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
> Hi,
>
> On 10/13/2015 01:22 PM, Felipe Balbi wrote:
>> Yegor Yefremov writes:
Hi,
* Lucas Stach [151014 07:52]:
> This is not needed anymore. Handling a potentially pending imprecise external
> abort left behind by the bootloader is now done in a slightly safer way inside
> the common ARM startup code.
With commit bbeb92095159 ("ARM: 8422/1: enable imprecise aborts during
Felipe,
On 10/14/2015 11:25 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
On 10/14/2015 10:56 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Hi,
On 10/13/2015 01:22 PM, Felipe Balbi wrote:
Yegor Yefremov writes:
On Mon, Oct 12, 2015 at 11:34 AM, Yegor Yefremov
wrote:
We have a problem,
Hi,
Bin Liu writes:
> On 10/14/2015 10:56 AM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Bin Liu writes:
>>> Hi,
>>>
>>> On 10/13/2015 01:22 PM, Felipe Balbi wrote:
Yegor Yefremov writes:
> On Mon, Oct 12, 2015 at 11:34 AM, Yegor Yefremov
> wrote:
>> We have a problem, when using mo
On 10/14/2015 11:18 AM, Tony Lindgren wrote:
> * Franklin S Cooper Jr. [151014 07:37]:
>>
>> On 10/14/2015 09:11 AM, Roger Quadros wrote:
>>> On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
On 10/14/2015 06:52 AM, Roger Quadros wrote:
> Franklin,
>
> On 14/10/15 14:36, Roger Qua
On Wednesday, October 14, 2015 10:18:27 AM Marc Titinger wrote:
> On 14/10/2015 02:55, Rafael J. Wysocki wrote:
> > On Monday, September 28, 2015 03:20:44 PM Marc Titinger wrote:
> >> - change arg3 to a state name string: we got the current CPU rom the trace
> >> backend already. This also prepares
* Arnd Bergmann [151014 02:20]:
> On Tuesday 13 October 2015 16:13:20 Tony Lindgren wrote:
> > On boards with more than 2GB of RAM booting goes wrong with things not
> > working
> > and we're getting lots of l3 warnings:
> >
> > WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147
> > l3_int
* Franklin S Cooper Jr. [151014 07:37]:
>
>
> On 10/14/2015 09:11 AM, Roger Quadros wrote:
> > On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
> >>
> >> On 10/14/2015 06:52 AM, Roger Quadros wrote:
> >>> Franklin,
> >>>
> >>> On 14/10/15 14:36, Roger Quadros wrote:
> On 13/10/15 04:38, Fran
On 10/14/2015 10:56 AM, Felipe Balbi wrote:
Hi,
Bin Liu writes:
Hi,
On 10/13/2015 01:22 PM, Felipe Balbi wrote:
Yegor Yefremov writes:
On Mon, Oct 12, 2015 at 11:34 AM, Yegor Yefremov
wrote:
We have a problem, when using more than 12 FTDI ports. Kernels tried:
3.18.1, 4.2.3 and 4.3-rc5.
* Lokesh Vutla [151013 20:53]:
> Hi Tony,
>
> On Wednesday 14 October 2015 04:43 AM, Tony Lindgren wrote:
> > On boards with more than 2GB of RAM booting goes wrong with things not
> > working
> > and we're getting lots of l3 warnings:
> >
> > WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c
Hi,
Bin Liu writes:
> Hi,
>
> On 10/13/2015 01:22 PM, Felipe Balbi wrote:
>> Yegor Yefremov writes:
>>> On Mon, Oct 12, 2015 at 11:34 AM, Yegor Yefremov
>>> wrote:
We have a problem, when using more than 12 FTDI ports. Kernels tried:
3.18.1, 4.2.3 and 4.3-rc5. SoC am335x 600MHz
Hi,
On 10/13/2015 01:22 PM, Felipe Balbi wrote:
Yegor Yefremov writes:
On Mon, Oct 12, 2015 at 11:34 AM, Yegor Yefremov
wrote:
We have a problem, when using more than 12 FTDI ports. Kernels tried:
3.18.1, 4.2.3 and 4.3-rc5. SoC am335x 600MHz
Below the USB topology:
# lsusb -t
/: Bus 02.Po
On 10/14/2015 05:41 PM, Vinod Koul wrote:
> On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
>> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
>> *edma_prep_dma_memcpy(
>> struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
>> size_t len, unsigned long t
On 10/14/2015 05:48 PM, Vinod Koul wrote:
> On Wed, Oct 14, 2015 at 04:12:21PM +0300, Peter Ujfalusi wrote:
>> The DMA event crossbar on AM33xx/AM43xx is different from the one found in
>> DRA7x family.
>> Instead of a single event crossbar it has 64 identical mux attached to each
>> eDMA event lin
This is not needed anymore. Handling a potentially pending imprecise external
abort left behind by the bootloader is now done in a slightly safer way inside
the common ARM startup code.
Signed-off-by: Lucas Stach
---
arch/arm/mach-bcm/bcm_5301x.c | 35 ---
1 file
This is not needed anymore. Handling a potentially pending imprecise external
abort left behind by the bootloader is now done in a slightly safer way inside
the common ARM startup code.
Signed-off-by: Lucas Stach
---
arch/arm/mach-omap2/pdata-quirks.c | 29 -
1 file c
This is not needed anymore. Handling a potentially pending imprecise external
abort left behind by the bootloader is now done in a slightly safer way inside
the common ARM startup code.
Signed-off-by: Lucas Stach
---
arch/arm/mach-mvebu/board-v7.c | 35 ---
1 file
Install a non-faulting handler just before unmasking imprecise aborts
and switch back to the regular one after unmasking is done.
This catches any pending imprecise abort that the firmware/bootloader
may have left behind that would normally crash the kernel at that point.
As there are apparently a
This series implements the handling of a pending imprecise abort left behind
by the bootloader/firmware running before Linux in the common ARM startup code.
It turns pending imprecise aborts that may signal during the first unmasking
of such aborts on the boot CPU into a non-faulting event and war
On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
> *edma_prep_dma_memcpy(
> struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
> size_t len, unsigned long tx_flags)
> {
> - int ret;
> + int ret
On Wed, Oct 14, 2015 at 04:12:21PM +0300, Peter Ujfalusi wrote:
> The DMA event crossbar on AM33xx/AM43xx is different from the one found in
> DRA7x family.
> Instead of a single event crossbar it has 64 identical mux attached to each
> eDMA event line. When the 0 event mux is selected, the default
On 10/14/2015 09:17 AM, Roger Quadros wrote:
> On 14/10/15 16:34, Franklin S Cooper Jr. wrote:
>>
>> On 09/18/2015 09:53 AM, Roger Quadros wrote:
>>> Add compatible id, GPMC register resource and interrupt
>>> resource to NAND controller nodes.
>>>
>>> The GPMC driver now implements gpiochip and
On 10/14/2015 09:11 AM, Roger Quadros wrote:
> On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>>
>> On 10/14/2015 06:52 AM, Roger Quadros wrote:
>>> Franklin,
>>>
>>> On 14/10/15 14:36, Roger Quadros wrote:
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Switch from dma_request_channel
On Wed, Oct 14, 2015 at 02:42:42PM +0300, Peter Ujfalusi wrote:
> Hi,
>
> Cover letter:
>
> with this series the edma two driver setup will be changed to have only one
> driver to support eDMA3. The legacy edma interface will be removed and eDMA
> can
> only be used via dmaengine API from this p
On 14/10/15 16:34, Franklin S Cooper Jr. wrote:
>
>
> On 09/18/2015 09:53 AM, Roger Quadros wrote:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller and interrupt-
On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 06:52 AM, Roger Quadros wrote:
>> Franklin,
>>
>> On 14/10/15 14:36, Roger Quadros wrote:
>>> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
Switch from dma_request_channel to allow passing dma channel
information from
On 10/14/2015 06:44 AM, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> Add dma channel information to the gpmc. Although not enabled by
>> default this will allow prefetch-dma to be used.
>>
>> Signed-off-by: Franklin S Cooper Jr
>> ---
>> arch/arm/boot/dts/am33xx.dtsi
On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from low power
state via pinctrl and IO daisy chain using generic wakeirq framework.
With commit 3fffd1283927 ("i2c: allow specifying separate wakeup
interrupt in device tree") i2c core allows optional wakeirq to be
specified via device tree. Ad
Add USB hooks into NanoBone DTS file
Signed-off-by: Mark Jackson
---
arch/arm/boot/dts/am335x-nano.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-nano.dts
b/arch/arm/boot/dts/am335x-nano.dts
index 5ed4ca6..b86937a 100644
--- a/arch/arm/boot/d
On 10/14/2015 06:41 AM, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> The prefetch engine sends a dma request once a FIFO threshold has
>> been met. No other requests are received until the previous request
>> is handled.
>>
>> Starting an edma transfer (dma_async_issue
On 09/18/2015 09:53 AM, Roger Quadros wrote:
> Add compatible id, GPMC register resource and interrupt
> resource to NAND controller nodes.
>
> The GPMC driver now implements gpiochip and irqchip so
> enable gpio-controller and interrupt-controller properties.
>
> With this the interrupt parent o
On 10/14/2015 06:52 AM, Roger Quadros wrote:
> Franklin,
>
> On 14/10/15 14:36, Roger Quadros wrote:
>> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>>> Switch from dma_request_channel to allow passing dma channel
>>> information from DT rather than hardcoding a value.
>>>
>>> Signed-off-by: Fr
Hi,
This series depends on the eDMA driver merger series (v5) [1].
The first two patch is to improve the memcpy functionality by removing the
alignment constraint and speed optimization (memcpy speed is up from ~3MB/s to
~15MB/s).
The rest of the series consits of smaller cleanup patches and the
Despite the claim by the original commit adding the memcpy
support, eDMA does not have constraint on the alignment of src, dst
or length in increment mode.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drive
Instead of passing a pointer to struct edma_cc and the channel number,
pass only the pointer to the edma_chan structure for the given channel.
This struct contains all the information needed by the functions and the
use of this makes it obvious that most of the sanity checks can be removed
from the
If the transfer is shorted then 64K we can complete it with one ACNT burst
by configuring ACNT to the length of the copy, this require one paRAM slot.
Otherwise we use two paRAM slots for the copy:
slot1: will copy (length / 32767) number of 32767 byte long blocks
slot2: will be configured to copy
These inline functions are designed to modify parts of the PaRAM in eDMA.
Change the names accordingly.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
inde
Query the number of qDMA channels from CCCFG register.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index a02f84c7c3d7..d064fbc47351 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue()
We can merge the content of the later so we will have only one function
to be used for mapping channels to given eventq
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 56 +--
Instead of nesting functions just merge them since the resulting function
is still small and readable.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index
Move all code under one function to do the dma device and eDMA channel
related setup so they are not scattered around the driver.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 79 +-
1 file changed, 37 insertions(+), 42 deletions(-)
d
The channel/slot reservation is not supported when booted with DT so there
is not need to allocate memory.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 53188b9383a6..f511684f83a2 100644
The DMA event crossbar on AM33xx/AM43xx is different from the one found in
DRA7x family.
Instead of a single event crossbar it has 64 identical mux attached to each
eDMA event line. When the 0 event mux is selected, the default mapped event
is going to be routed to the corresponding eDMA event line
Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and
enable the DMA even crossbar with ti,am335x-edma-crossbar.
With the new bindings boards can customize and tweak the DMA channel
priority to match their needs. With the new binding the memcpy is safe
to be used since with th
Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and
enable the DMA even crossbar with ti,am335x-edma-crossbar.
With the new bindings boards can customize and tweak the DMA channel
priority to match their needs. With the new binding the memcpy is safe
to be used since with th
With the old binding and driver architecture we had many issues:
No way to assign eDMA channels to event queues, thus not able to tune the
system by moving specific DMA channels to low/high priority servicing. We
moved the cyclic channels to high priority within the code, but that was
just a workar
On 10/14/2015 01:58 AM, Roger Quadros wrote:
> On 13/10/15 16:44, Franklin S Cooper Jr wrote:
>> ELM address information is provided by device tree. No longer need
>> to include this information within hwmod.
>>
>> Signed-off-by: Franklin S Cooper Jr
> Acked-by: Roger Quadros
>
> Franklin,
>
>
On Fri, Oct 02, 2015 at 06:02:42PM -0500, Suman Anna wrote:
> Suman Anna (2):
> Documentation: dt: Update OMAP iommu bindings for DRA7 DSPs
> iommu/omap: Add support for configuring dsp iommus on DRA7xx
>
> .../devicetree/bindings/iommu/ti,omap-iommu.txt| 27 ++
> drivers/iommu/om
On 14/10/15 14:37, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Oct 14, 2015 at 02:27:27PM +0300, Roger Quadros wrote:
>> On 14/10/15 14:19, Sebastian Reichel wrote:
>>> On Wed, Oct 14, 2015 at 01:44:16PM +0300, Roger Quadros wrote:
Let's keep the SSI ports disabled in the omap3.dtsi to avoid
>
Franklin,
On 14/10/15 14:36, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> Switch from dma_request_channel to allow passing dma channel
>> information from DT rather than hardcoding a value.
>>
>> Signed-off-by: Franklin S Cooper Jr
>
> Acked-by: Roger Quadros
>
>> -
In case when the interrupt happened for the second eDMA the channel
number was incorrectly passed to the client driver.
Signed-off-by: Peter Ujfalusi
CC:
---
arch/arm/common/edma.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common
Since the driver stack no longer depends on lookup with id number in a
global array of pointers, the limitation for the number of eDMAs are no
longer needed. We can handle as many eDMAs in legacy and DT boot as we have
memory for them to allocate the needed structures.
Signed-off-by: Peter Ujfalus
Currently we have one device created to handle all (maximum 2) eDMAs in the
system.
With this change all eDMA instance will have it's own device/driver.
This change is needed for further cleanups in the eDMA driver stack since
the one device/driver to handle all eDMAs in the system was not flexible
If the of_dma_controller is registered in the non dmaengine driver we could
have race condition:
the of_dma_controller has been registered, but the dmaengine driver is not
yet probed. Drivers requesting DMA channels during this window will fail
since we do not yet have dmaengine drivers registered.
We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.
Signed-off-by: Peter Ujfalusi
---
arch/arm/common/edma.c | 376 -
include/linux/platform_data/edma.h | 33
2 files changed, 409
The code path in edma_execute() and edma_callback() can be simplified
and make it more optimal.
There is not need to call in to edma_execute() when the transfer
has been finished for example.
Also the handling of missed/first or next batch of paRAMs can
be done in a more optimal way.
Signed-off-by
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add additional details to the gpmc and nand documentation to clarify
> what is needed to enable nand dma prefetch.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 7
> ++-
>
The upcoming change to merge the arch/arm/common/edma.c into
drivers/dma/edma.c will need this change when booting daVinci devices in
no DT mode.
Signed-off-by: Peter Ujfalusi
Acked-by: Sekhar Nori
---
arch/arm/mach-davinci/devices-da8xx.c | 2 ++
arch/arm/mach-davinci/dm355.c | 1 +
ar
Convert the eDMA platform device creation to use
struct platform_device_info XX __initconst and
platform_device_register_full()
This will allow us to cleanly specify the dma_mask for the devices in an
upcoming patch.
Signed-off-by: Peter Ujfalusi
Acked-by: Sekhar Nori
---
arch/arm/mach-davi
Be consistent and do not mix the use of dev, &pdev->dev, etc in the
functions.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 61 +++---
1 file changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
When allocating a memory for number of items it is better (looks better)
to use devm_kcalloc.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index d5a76c67f83f..95c10373168d 1006
Instead of relying on indexes pointing to edma private date in the global
pointer array, pass the private data pointer via the public API.
Signed-off-by: Peter Ujfalusi
---
arch/arm/common/edma.c | 305 ++---
drivers/dma/edma.c | 79 ++
We have access to dev, so it is better to use the dev_dbg for debug prints.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index a9fe5c92451d..08f9bd0aa0b3
Remove the OMAP3 core DPLL re-program code, and the associated SRAM
code that does the low-level programming of the DPLL divider, idling
of the SDRAM etc.
This code was never fully implemented in the kernel; things missing
were driver side handling of core clock changes (they need to account
for t
Merge the iomem into the 'struct edma' and change the internal (static)
functions to use pointer to the edma_cc instead of the ctlr number.
Signed-off-by: Peter Ujfalusi
---
arch/arm/common/edma.c | 400 -
1 file changed, 197 insertions(+), 203 del
Remove or rewrite the comments for the internal functions.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 86 +++---
1 file changed, 11 insertions(+), 75 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index d33ae0b43925.
On 10/12/2015 08:01 PM, Tony Lindgren wrote:
* Tony Lindgren [150812 03:59]:
* Tony Lindgren [150812 00:29]:
* Tero Kristo [150716 01:10]:
Remove the OMAP3 core DPLL re-program code, and the associated SRAM
code that does the low-level programming of the DPLL divider, idling
of the SDRAM et
Warning message in case of linking between paRAM slots in different eDMA
controllers.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index f6653da0ee16..d33ae0b43925 100644
--- a/drivers/dma/edma
Move the code out from arch/arm/common and merge it inside of the dmaengine
driver.
This change is done with as minimal (if eny) functional change to the code
as possible to avoid introducing regression.
Signed-off-by: Peter Ujfalusi
Acked-by: Tony Lindgren
---
arch/arm/Kconfig
With the merger of the arch/arm/common/edma.c code into the dmaengine
driver, there is no longer need to have per channel callback/data storage
for interrupt events.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 450 -
1 file changed,
Instead of directly reading it from CCCFG register take the information out
once when we set up the configuration from the HW.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
No need to run through the bits in QEMR and CCERR events since they will
not trigger any action, so just clearing the errors there is fine.
In case of the missed event the loop can be optimized so we spend less time
to handle the event.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 82 +
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