Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode.
so why is this patch bothering
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Wed, May 16, 2012 at 10:21 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman
Jon Hunter jon-hun...@ti.com writes:
From: Jon Hunter jon-hun...@ti.com
The OMAP2+ timer code has a definition for the maximum number of timers that
OMAP2+ devices have. This defintion is not used anywhere in the code and
appears to be left over. Furthermore the definition is not accurate
(), the bank-workaround_enabled check is
moved after context restore. Otherwise, it would prevent
context restore when bank-enabled_non_wakeup_gpios is 0.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120517 15:29]:
I just noticed that this patch has caused some strange problems, notably
with the GPIO IRQ used by smsc911x NIC (Overo, Zoom3, 2430SDP, etc. etc.)
The patch itself is OK, but it has exposed a bug in other
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor
Tero Kristo t-kri...@ti.com writes:
On Tue, 2012-05-15 at 15:41 -0700, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
PM debug now contains a file that can be used to control OSWR support
enable / disable on OMAP4. Also removed the off_mode_enable file for
the same platform
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
L3INIT powerdomain has USB HOST and USB TLL modules which support
hardware save-and-restore (HW SAR) mechanism.
This patch updates the L3INIT power domain to mark them as capable
of doing H/w save and
Tero Kristo t-kri...@ti.com writes:
Added in preparation for device off mode. SAR ROM contains the mapping
from SAR RAM to IO registers, and this will eventually be parsed during
init time to do the reverse before device off.
Signed-off-by: Tero Kristo t-kri...@ti.com
This should be
+Jean for functional power states
Tero Kristo t-kri...@ti.com writes:
This patch adds device off support to OMAP4 device type.
Description is rather thin for a patch that is doing so much.
OFF mode is disabled by default,
why?
however, there are two ways to enable OFF mode:
a) In the
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post wakeup from OFF mode.
The rest of the DPLL's in OMAP4 platform (MPU/IVA/ABE/USB/PER)
are saved and restored here during an OFF transition.
[n...@ti.com:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Restore all CM1/2 module registers as they are lost in OFF mode.
Save and restore?
Also, as in the previous patch. Can this be done using cluster PM
notifier as well?(I realize that this series was probably done
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode.
so why is this patch bothering to save and restore it?
-ECONFUSED
The register layout
is fixed in SAR ROM. SAR is split into 4 banks with different
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS device only (not GP device), when
restoring the Secure RAM, the ROM Code
On 05/16/2012 04:05 PM, Kevin Hilman wrote:
Tero Kristot-kri...@ti.com writes:
From: Santosh Shilimkarsantosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS device only (not GP device), when
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
On HS devices on the way out of MPU OSWR and OFF ROM code wrongly
overwrites the CM L3INSTR registers. So to avoid this, save them and
restore on the way out from MPU OSWR/OFF.
This errata applies to all HS/EMU versions
Tero Kristo t-kri...@ti.com writes:
From: Carlos Leija cile...@ti.com
At wakeup from OFF/OSWR CPU1 will call secure HAL service through a local
secure dispatcher with MMU off,
Reviewers who are uninitaited in this level of detail need some more
help here (even those who are deeply familiar
Tero Kristo t-kri...@ti.com writes:
From: Axel Haslam axelhas...@gmail.com
ROM code restores part of the GIC context during wakeup from device
off mode from the SAR RAM. If the PPI and SPI interrupts are not
marked as non-secure on GP chips, this crashes the device during
wakeup, thus mark
+Benoit
Tero Kristo t-kri...@ti.com writes:
save_secure_all needs l3_main_3_ick and l4_secure_clkdm enabled,
otherwise the secure ROM code will crash.
Signed-off-by: Tero Kristo t-kri...@ti.com
I think I mentioned this already (I'm already lost in what I've said for
thisseries), but I don't
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1 Is Used On EMIF which impacts OMAP443x silicon
The issue occurs when EMIF_SDRAM_CONFIG is restored first before
Tero Kristo t-kri...@ti.com writes:
If AUX_CORE_BOOT0 does not indicate wakeup request for cpu1, put it back
to off.
Why is it waking up then? (I know the answer, but will forget. The
changelog serves as my long-term memory.)
This is needed during wakeup from device off to prevent cpu1
Tero Kristo t-kri...@ti.com writes:
Without this, CPU0 will crash in the ROM code during wakeup from
device off. This patch also clears the GIC save area, to prevent
ROM code from writing garbage to the GIC registers during wakeup.
The actual GIC restore is done by kernel.
This bug fix
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 15:48 -0700, Kevin Hilman wrote:
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 08:36 +0100, Joe Woodward wrote:
Any news on this?
This thread seems to have gone a little quiet...
Hi,
I've
Hi Amit, Eric,
Amit Kucheria amit.kuche...@linaro.org writes:
Eric,
This looks interesting, but I'll add the linux-omap list to CC so
someone can verify if there isn't already a patch to export this.
We used to have similar PM debug code in the kernel, but as the one who
maintained it, I
Tony Lindgren t...@atomide.com writes:
* Javier Martinez Canillas jav...@dowhile0.org [120427 02:33]:
On Wed, Apr 25, 2012 at 9:59 AM, Enric Balletbò i Serra
eballe...@gmail.com wrote:
Tony, as this is a fix ,may be included ?
Acked-by: Enric Balletbo i Serra eballe...@gmail.com
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Remove the FIXME's in the suspend sequence since
we now intend to support system level RET support.
minor: this should probably go at the end of the series, after retention
is supported. Otherwise, ending up with only
. Applies to your 'board' branch.
Kevin
From f4f2c35de0e67e3b8185059ffd78be67f7096d8a Mon Sep 17 00:00:00 2001
From: Kevin Hilman khil...@ti.com
Date: Tue, 15 May 2012 13:07:20 -0700
Subject: [PATCH] ARM: OMAP2+: nand: fix build error when
CONFIG_MTD_ONENAND_OMAP2=n
MIME-Version: 1.0
Content-Type
Cousson, Benoit b-cous...@ti.com writes:
On 4/24/2012 4:46 PM, Tero Kristo wrote:
On Mon, 2012-04-23 at 10:52 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:19 AM, Tero Kristo wrote:
From: Rajendra Nayakrna...@ti.com
On OMAP4 most modules/hwmods support module level context status. On
Tero Kristo t-kri...@ti.com writes:
On OMAP4, there is no support to read previous logic state
or previous memory state achieved when a power domain transitions
to RET. Instead there are module level context registers.
In order to support the powerdomain level logic/mem_off_counters
on
Tero Kristo t-kri...@ti.com writes:
PM debug now contains a file that can be used to control OSWR support
enable / disable on OMAP4. Also removed the off_mode_enable file for
the same platform as it is unsupported.
Signed-off-by: Tero Kristo t-kri...@ti.com
I'll gladly take a patch that
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC
Vaibhav Hiremath hvaib...@ti.com writes:
From: Kevin Hilman khil...@ti.com
There are certain fields inside 'struct dpll_data' which are
included under ARCH_OMAP3 and ARCH_OMAP4 option, which makes it
difficult to use it for new devices like, am33xx, ti81xx, etc...
So remove the ifdef
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 08:36 +0100, Joe Woodward wrote:
Any news on this?
This thread seems to have gone a little quiet...
Hi,
I've been doing testing to understand the problem, but so far I don't
have any idea why things go wrong. I haven't
+Sekhar,
Mark A. Greer mgr...@animalcreek.com writes:
From: Mark A. Greer mgr...@animalcreek.com
Paul, Kevin,
These patches convert the davinci emac support for the am35x SoC
to use hwmod and add enable_hlt()/disable_hlt() calls to the
pm_runtime hooks for that driver.
Great. I didn't
Hiremath, Vaibhav hvaib...@ti.com writes:
On Fri, May 11, 2012 at 03:09:39, Hilman, Kevin wrote:
Hiremath, Vaibhav hvaib...@ti.com writes:
On Wed, May 09, 2012 at 04:08:09, Hilman, Kevin wrote:
Vaibhav Hiremath hvaib...@ti.com writes:
The function __omap2_set_globals() can be common
Hi Grant,
Here's the final round of GPIO cleanups for v3.5. This branch is based
on my for_3.5/fixes/gpio branch you just pulled.
Kevin
The following changes since commit 6edd94db250038c8fdf176f23ca4017d2f312509:
gpio/omap: fix incorrect initialization of omap_gpio_mod_init (2012-05-10
Jon Hunter jon-hun...@ti.com writes:
[...]
I have posted my latest series here [1] based upon that from Will [2]
which attempts to fix the EMU CD based upon the inputs from this thread.
It is working on my omap4460 panda.
There are some differences between 4430 and 4460 here. Can you test
Grant,
DebBarma, Tarun Kanti tarun.ka...@ti.com writes:
Hi,
On Thu, May 10, 2012 at 3:06 AM, Janusz Krzysztofik
jkrzy...@tis.icnet.pl wrote:
On Mon, 7 May 2012 10:52:28 DebBarma, Tarun Kanti wrote:
On Sun, May 6, 2012 at 3:25 AM, Grazvydas Ignotas nota...@gmail.com wrote:
On Mon, Apr 30,
Hiremath, Vaibhav hvaib...@ti.com writes:
On Wed, May 09, 2012 at 04:08:09, Hilman, Kevin wrote:
Vaibhav Hiremath hvaib...@ti.com writes:
The function __omap2_set_globals() can be common across all
platforms/architectures, even in case of omap4, internally it
calls same set of functions
hvaib...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin Hilman khil...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
Ideally, we should use dynamic allocation to allocate memory
for registers/arrays,
Yes.
Thanks Kevin, I will put
Hi Govindraj,
Raja, Govindraj govindraj.r...@ti.com writes:
[...]
I tested this series from your tree on Beagle-XM retention, offmode,
suspend to mem and resume with and and without enabling offmode
from sysfs was checked and found retention count and off mode
count was getting incremented.
Woodruff, Richard r-woodru...@ti.com writes:
From: Hilman, Kevin
Sent: Tuesday, May 08, 2012 5:17 PM
A basic OMAP AVS driver has been in mainline for a long time, yet we
have not seen support submitted for all of these features.
1.5/3.5 is a feature.
And I'm still waiting for it to be
Tero Kristo t-kri...@ti.com writes:
Hi,
First version for this work. Applies on top of mainline + iochain set +
OMAP4 core retention set. Working tree available here:
tree: git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.4-omap4-dev-off
FYI... seems your get repo is
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Restore all CM1/2 module registers as they are lost in OFF mode.
Except they are still lost since nobody calls these new functions (in
this patch.) :)
For ease of review, it's preferred to add the *users* of new code in
Paul Walmsley p...@pwsan.com writes:
On Thu, 19 Apr 2012, Igor Grinberg wrote:
IMO this can be seen on any AM35xx based board with EMAC, or am I mistaken?
Just tested this on a 3517EVM and the same problem is there too.
Does adding nohlt on the cmdline make a difference?
The AM35x has
Jean Pihet jean.pi...@newoldbits.com writes:
[...]
Yes, indeed, we should not hack the flags to fix that kind of issue. The
flags describe what the HW is capable of, and the EMU CD can support
HW_AUTO
and SW_WAKEUP. AFAIK, the issue with that EMU CD is that the only valid
next
power state
Cousson, Benoit b-cous...@ti.com writes:
On 5/8/2012 4:00 PM, Kevin Hilman wrote:
Jean Pihetjean.pi...@newoldbits.com writes:
[...]
Yes, indeed, we should not hack the flags to fix that kind of issue. The
flags describe what the HW is capable of, and the EMU CD can support
HW_AUTO
maintain. I Cc'd the linux-omap list in case there are any
objections to me adding myself.
Kevin
From 307f4150416c34936d7f0011d7f1b2146c13f9a0 Mon Sep 17 00:00:00 2001
From: Kevin Hilman khil...@ti.com
Date: Tue, 8 May 2012 09:51:22 -0700
Subject: [PATCH] MAINTAINERS: add OMAP CPUfreq driver
The TWL driver has been converted to use SPARSE_IRQ and no longer
needs to be passed IRQ base/end. Since driver no longer uses these
fields, so remove them from the reamaining users.
Cc: Benoit Cousson b-cous...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Kevin Hilman khil
After converstion to SPARSE_IRQ, the driver doesn't use the
pdata-irq_base/irq_end fields anymore. The last users
have been cleanup up, and now these fields can be removed.
Cc: Benoit Cousson b-cous...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Kevin Hilman khil...@ti.com
The TWL driver has been converted to SPARSE_IRQ, and no longer needs
these fields. Remove them.
Samuel, with your ack, we can keep the twl.h change with the OMAP
change that removes all the users so they merge together and avoid
potential build problems if they merge separately.
Kevin
Kevin
cleanups
the code, to increase maximum number of interrupts support
to 128, with dynamic detection of no of registers required for
handling all interrupts.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin
Daniel Lezcano daniel.lezc...@linaro.org writes:
Define a CPU_IDLE section in the makefile, declare the functions in
the header files conforming to the kernel coding rules and remove the
'define's in the C files.
CONFIG_PM is enabled when CPU_IDLE is enabled because the cpuidle drivers
use
Daniel Lezcano daniel.lezc...@linaro.org writes:
On 05/04/2012 07:18 PM, Daniel Lezcano wrote:
Define a CPU_IDLE section in the makefile, declare the functions in
the header files conforming to the kernel coding rules and remove the
'define's in the C files.
CONFIG_PM is enabled when
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120507 10:37]:
Tony,
Kevin Hilman khil...@ti.com writes:
The detection of AM35xx SoCs is confusing and has redundancies. Clean
this up so that SoC detection is only based on SoC family: AM35xx.
Since these aren't
Jon Hunter jon-hun...@ti.com writes:
Hi Benoit,
On 05/08/2012 06:01 AM, Cousson, Benoit wrote:
[...]
P.S. Please note there is also already a different fix in mainline for
the EMU clkdm data from Paul which adds the force wakeup flag and
removes the DISABLE_AUTO flag[1] (but leaves the
Jon Hunter jon-hun...@ti.com writes:
On 05/08/2012 11:18 AM, Kevin Hilman wrote:
Cousson, Benoit b-cous...@ti.com writes:
On 5/8/2012 4:00 PM, Kevin Hilman wrote:
Jean Pihetjean.pi...@newoldbits.com writes:
[...]
Yes, indeed, we should not hack the flags to fix that kind of issue
Vaibhav Hiremath hvaib...@ti.com writes:
Initially, we decided to make am33xx family of device to fall
under omap3 class (cpu_is_omap34xx() = true), since it carries
Cortex-A8 core. But while adding complete baseport support
(like, clock, power and hwmod) support, it is observed that,
we are
Hi Russ,
Russ Dill russ.d...@ti.com writes:
This removes several boot warnings from board-omap3beagle.c:
- gpio_request: gpio--22 (DVI reset) status -22
- Unable to get DVI reset GPIO
Thanks for your patches and revies on the list! It's much appreciated.
Some requests for upstream-bound
Woodruff, Richard r-woodru...@ti.com writes:
The only thing the higher-level layers might potentially need to
do is to enable/disable AVS around transitions (e.g. when
changing OPP,AVS is disabled before changing OPP and
only re-enabled when the newnominal voltage has been
Vaibhav Hiremath hvaib...@ti.com writes:
The function __omap2_set_globals() can be common across all
platforms/architectures, even in case of omap4, internally it
calls same set of functions as in __omap2_set_globals() function
(except for sdrc).
OK so far.
This patch adds new config flag
SOC_HAS_OMAP3_DPLL_DCO_SEL: dco selection
SOC_HAS_OMAP3_DPLL_SDDIV: sigma-delta div factor
SOC_HAS_OMAP3_DPLL_FREQSEL: frequency selection
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin Hilman khil...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Paul is the one
it supports the FORCE_WAKEUP state.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Benoît Cousson b-cous...@ti.com
Cc: Kevin Hilman khil...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Ming Lei ming@canonical.com
Cc: Will Deacon will.dea...@arm.com
Jean Pihet jean.pi...@newoldbits.com writes:
On Tue, May 1, 2012 at 7:27 PM, Kevin Hilman khil...@ti.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
HI Kevin, Grazvydas,
On Tue, Apr 24, 2012 at 4:29 PM, Kevin Hilman khil...@ti.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes
Tony,
Kevin Hilman khil...@ti.com writes:
The detection of AM35xx SoCs is confusing and has redundancies. Clean
this up so that SoC detection is only based on SoC family: AM35xx.
Since these aren't PM related, can you queue these with other cleanups
for v3.5. This is now independent from
Tony Lindgren t...@atomide.com writes:
* Raja, Govindraj govindraj.r...@ti.com [120424 01:41]:
On Tue, Apr 24, 2012 at 5:15 AM, Kevin Hilman khil...@ti.com wrote:
Govindraj.R govindraj.r...@ti.com writes:
From: Govindraj.R govindraj.r...@ti.com
The following commit:
(7496ba3 ARM
Govindraj.R govindraj.r...@ti.com writes:
From: Govindraj.R govindraj.r...@ti.com
On 24xx/34xx/36xx Module level wakeup events are enabled/disabled using
PM_WKEN1_CORE/PM_WKEN_PER regs.
Add api to control the module level wakeup mechanism from info provided from
hwmod data.
Can you rework
Jon Hunter jon-hun...@ti.com writes:
Hi Kevin,
On 05/07/2012 12:15 PM, Kevin Hilman wrote:
Jon Hunter jon-hun...@ti.com writes:
Hi Will,
On 04/26/2012 01:07 PM, Will Deacon wrote:
On Wed, Apr 04, 2012 at 12:15:24PM +0100, Will Deacon wrote:
On Wed, Apr 04, 2012 at 12:29:49AM +0100
J, KEERTHY j-keer...@ti.com writes:
Hi AnilKumar,
Thanks for reviewing.
On Fri, May 4, 2012 at 2:00 PM, AnilKumar, Chimata anilku...@ti.com wrote:
On Thu, Apr 26, 2012 at 23:10:35, J, KEERTHY wrote:
From: Jean Pihet j-pi...@ti.com
Change the name field value to better reflect the
AnilKumar, Chimata anilku...@ti.com writes:
On Sat, Apr 28, 2012 at 02:31:17, Hilman, Kevin wrote:
Hi Mark,
Mark Brown broo...@opensource.wolfsonmicro.com writes:
On Fri, Apr 27, 2012 at 11:09:10AM +0530, J, KEERTHY wrote:
Devfreq and cpufreq are related to dynamic frequency/voltage
Rafael,
Keerthy j-keer...@ti.com writes:
From: J Keerthy j-keer...@ti.com
AVS(Adaptive Voltage Scaling) is a power management technique which
controls the operating voltage of a device in order to optimize (i.e. reduce)
its power consumption. The voltage is adapted depending on static
Kevin Hilman khil...@ti.com writes:
J, KEERTHY j-keer...@ti.com writes:
[...]
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 2edd1e2..d859277 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -183,7 +183,7
Tero Kristo t-kri...@ti.com writes:
From: Axel Haslam axelhas...@gmail.com
On OMAP4, there is no support to read previous logic state
or previous memory state achieved when a power domain transitions
to RET. Instead there are module level context registers.
In order to support the
+Sekhar
Bedia, Vaibhav vaibhav.be...@ti.com writes:
Hi Kevin,
On Fri, May 04, 2012 at 03:02:16, Hilman, Kevin wrote:
Ben Hutchings bhutchi...@solarflare.com writes:
On Thu, 2012-05-03 at 19:25 +, Bedia, Vaibhav wrote:
On Fri, May 04, 2012 at 00:16:32, Mark A. Greer wrote:
[...]
Hi Thomas,
Thomas Petazzoni thomas.petazz...@free-electrons.com writes:
I have an IGEPv2 revision 6 board, which uses the DM3730 OMAP3. With
3.2 omap2plus_defconfig, the system boots fine and have a working shell
on ttyO2. On either 3.3, 3.4-rc5 or arm-soc/for-next from Arnd, the
system
Hi Mark,
Mark A. Greer mgr...@animalcreek.com writes:
[...]
To work around this issue, add platform data callbacks which
are called at the beginning of the open routine and at the
end of the stop routine of the davinci_emac driver. The
callbacks allow the platform code to issue
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Fri, May 4, 2012 at 3:17 AM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need
Mark A. Greer mgr...@animalcreek.com writes:
On Fri, May 04, 2012 at 07:31:30AM -0700, Kevin Hilman wrote:
[...]
Come to think of it, the right solution here is probably to use runtime
PM. We could then to add some custom hooks for davinci_emac in the
device code to use enable_hlt
Daniel Lezcano daniel.lezc...@linaro.org writes:
At init time, check the powerdomains lookup is successful otherwise
exit the cpuidle driver init function with -ENODEV like what is done for the
omap3 cpuidle driver.
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Jean
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120504 09:31]:
Hi Thomas,
Thomas Petazzoni thomas.petazz...@free-electrons.com writes:
I have an IGEPv2 revision 6 board, which uses the DM3730 OMAP3. With
3.2 omap2plus_defconfig, the system boots fine and have
Bedia, Vaibhav vaibhav.be...@ti.com writes:
On Thu, May 03, 2012 at 05:17:18, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The davinci EMAC driver has been incorporated into the am35x
family of SoC's which is OMAP-based. The incorporation is
incomplete in that the EMAC
Hi Paul,
On 04/20/2012 01:59 PM, Paul Walmsley wrote:
[...]
This looks great, looks like it will finally fix this longstanding bug. I
think Santosh hit it too a long time ago, so I suspect he will be happy
too.
One comment: I think that omap2_wd_timer_reset() needs to be updated in
light of
Daniel Lezcano daniel.lezc...@linaro.org writes:
With the previous changes all the states are valid, except
the last state which can be handled by decreasing the number
of states.
I don't think this changelog is valid anymore as you're not doing
anything to decrease the number of states.
I
daniel.lezc...@linaro.org
Reviewed-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Tested-by: Kevin Hilman khil...@ti.com
[khil...@ti.com: update changelog, drop error check in fast path]
Signed-off-by: Kevin
Daniel Lezcano daniel.lezc...@linaro.org writes:
Define a CPU_IDLE section in the makefile, declare the functions in
the header files conforming to the kernel coding rules and remove the
'define's in the C files.
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Jean
Hi Daniel,
Daniel Lezcano daniel.lezc...@linaro.org writes:
This patchset makes some cleanup on these cpuidle drivers
and consolidate the code across both architecture.
I think I said it before, but it's worth repeating: Very nice cleanup!
Thanks for your persistence.
I've now been through
-off-by: Vaibhav Hiremath hvaib...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
I realize people may not necessarily like this, but I think that the
AM33xx EVM needs its own board file. This is because it really has
nothing to do with the AM3517EVM. Also, the AM3517EVM
Santosh Shilimkar santosh.shilim...@ti.com writes:
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need to patch
the file for any future OMAP2+ devices.
In long run, all these attributes should come from hwmod dev_attr based
that applies on top of
io_chain_devel_3.5 with an ack from Tero and Tested-by from Mohammed.
Kevin
From 22726db6fc514cc5110db43fdf05d5afda8e4a59 Mon Sep 17 00:00:00 2001
From: Kevin Hilman khil...@ti.com
Date: Tue, 1 May 2012 07:06:42 -0700
Subject: [PATCH] ARM: OMAP3: PM: leave PRCM interrupts disabled
check for return value from function
omap_init_clocksource_32k(), and fallback to omap_mpu_timer_init()
in case of failure/error from omap_init_clocksource_32k().
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin Hilman khil...@ti.com
Cc: Paul
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
With the change above,
Acked-by: Kevin Hilman khil...@ti.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More
Hiremath hvaib...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
Cc: Tarun Kanti DebBarma tarun.ka
currently
in Paul's tree[1].
Kevin
[1] git://git.pwsan.com/linux-2.6 io_chain_devel_3.5
From d94f04eea40686cd9db8e9dbd8dbf3c02edca07f Mon Sep 17 00:00:00 2001
From: Kevin Hilman khil...@ti.com
Date: Tue, 1 May 2012 07:06:42 -0700
Subject: [PATCH] ARM: OMAP3: PM: leave PRCM interrupts disabled
Mark A. Greer mgr...@animalcreek.com writes:
From: Mark A. Greer mgr...@animalcreek.com
The Chip Identification register on the am35x family of SoCs
has bits 12, 7:5, and 3:2 marked as reserved and are read as
zeroes. Unfortunately, on other omap SoCs, a 0 bit means a
feature is Full Use
Hiremath, Vaibhav hvaib...@ti.com writes:
On Fri, Apr 27, 2012 at 04:08:07, Paul Walmsley wrote:
On Thu, 26 Apr 2012, Paul Walmsley wrote:
Okay, thanks for testing. Please do update this patch to use
omap_hwmod_enable(), etc.; see for example omap_dm_timer_init_one().
And, just to be
Jean Pihet jean.pi...@newoldbits.com writes:
HI Kevin, Grazvydas,
On Tue, Apr 24, 2012 at 4:29 PM, Kevin Hilman khil...@ti.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
Hi Grazvydas, Kevin,
I did some gather some performance measurements and statistics using
custom tracepoints
Paul Walmsley p...@pwsan.com writes:
Hi Kevin,
On Fri, 27 Apr 2012, Kevin Hilman wrote:
_enable_module is specific to OMAP4-class SoCs, so rename it to
be consistend with the corresponding _omap4_disable_module.
Signed-off-by: Kevin Hilman khil...@ti.com
I tweaked the commit message
Jean Pihet jean.pi...@newoldbits.com writes:
Hi Kevin,
On Fri, Apr 27, 2012 at 1:29 AM, Kevin Hilman khil...@ti.com wrote:
This flag is no longer used since clock init all AM35x devices
is now the same.
Acked-by: Vaibhav Hiremath hvaib...@ti.com
Tested-by: Vaibhav Hiremath hvaib...@ti.com
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