Re: [PATCH v2] clocksource: arm_global_timer: fix suspend resume

[Marc Zyngier]

On 20/11/15 18:35, Grygorii Strashko wrote:
> Hi Santosh,
> 
> On 11/20/2015 07:23 PM, santosh shilimkar wrote:
>> + Thomas, Marc
>>
>> On 11/20/2015 5:57 AM, Grygorii Strashko wrote:
>>> Now the System stall is observed on TI AM437x based board
>>> (am437x-gp-evm) during resuming from System suspend when ARM Global
>>> timer is selected as clocksource device - SysRq are working, but
>>> nothing else. The reason of stall is that ARM Global timer loses its
>>> contexts.
>>>
>>> The reason of stall is that ARM Global timer loses its contexts during
>>> System suspend:
>>> GT_CONTROL.TIMER_ENABLE = 0 (unbanked)
>>> GT_COUNTERx = 0
>>>
>>> Hence, update ARM Global timer driver to reflect above behaviour
>>> - re-enable ARM Global timer on resume GT_CONTROL.TIMER_ENABLE = 1
>>> - ensure clocksource and clockevent devices have coresponding flags
>>>(CLOCK_SOURCE_SUSPEND_NONSTOP and CLOCK_EVT_FEAT_C3STOP) set
>>>depending on presence of "always-on" DT property.
>>>
>> Something which loses context in low power states can't be
>> called "always-on"
> 
> Sry, it's kinda new area for me and I could make mistakes.
> 
> While working on this patch I've:
>  - re-used implementation from ARM arch timer 
> commit 82a5619410d4c4df65c04272db198eca5a867c18
> Author: Lorenzo Pieralisi 
> Date:   Tue Apr 8 10:04:32 2014 +0100
> 
> clocksource: arch_arm_timer: Fix age-old arch timer C3STOP detection issue

[...]

This patch has a very specific purpose: instructing the core code that
this timer will never stop ticking, ever. It is really targeted at
virtual machines, whose timer is backed by the host timer, even when the
VM is not running.

Using it on actual hardware is may not be the best idea, specially in
the presence of PM.

Thanks,

M.
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Re: [PATCH v2 2/6] genirq: fix irqchip_set_wake_parent if IRQCHIP_SKIP_SET_WAKE

[Marc Zyngier]

On 14/08/15 11:18, Grygorii Strashko wrote:
 On 08/13/2015 03:58 PM, Grygorii Strashko wrote:
 On 08/13/2015 01:31 PM, Grygorii Strashko wrote:
 On 08/13/2015 01:01 PM, Marc Zyngier wrote:
 On 12/08/15 18:45, Grygorii Strashko wrote:
 The irqchip_set_wake_parent should not fail if IRQ chip
 specifies IRQCHIP_SKIP_SET_WAKE. Otherwise, IRQ wakeup
 configuration can't be propagated properly through IRQ
 domains hierarchy.

 In case of TI OMAP DRA7 the issue reproduced with following
 configuration:
 ARM GIC-OMAP wakeupgen-TI CBAR-GPIO-GPIO pcf857x-gpio_key

 gpio_key is wakeup source

 Failure is reproduced during suspend/resume to RAM:
 suspend:
- gpio_keys_suspend
  enable_irq_wake
+ pcf857x_irq_set_wake
  + omap_gpio_wake_enable
+ TI CBAR irq_chip_set_wake_parent
  + OMAP wakeupgen has no .irq_set_wake()

 Most importantly, wakeupgen has IRQCHIP_SKIP_SET_WAKE set.

  and -ENOSYS will be returned

 resume:
- gpio_keys_resume
  + disable_irq_wake
+ irq_set_irq_wake
  + WARN(1, Unbalanced IRQ %d wake disable\n, irq);

 Fixes: 08b55e2a9208 ('genirq: Add irqchip_set_wake_parent')
 Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
 ---
kernel/irq/chip.c | 4 
1 file changed, 4 insertions(+)

 diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
 index 6de638b..bdb1b9d 100644
 --- a/kernel/irq/chip.c
 +++ b/kernel/irq/chip.c
 @@ -1024,6 +1024,10 @@ int irq_chip_set_vcpu_affinity_parent(struct
 irq_data *data, void *vcpu_info)
int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
{
data = data-parent_data;
 +
 +if (irq_data_get_irq_chip(data)-flags  IRQCHIP_SKIP_SET_WAKE)
 +return 0;
 +
if (data-chip-irq_set_wake)
return data-chip-irq_set_wake(data, on);



 We have a more general issue with chip flags, and how they combine
 within a stack of irqchips.

 Indeed. Problem looks similar to IRQCHIP_MASK_ON_SUSPEND flag usage.


 What if you remove the irq_chip_set_wake_parent from the crossbar
 driver, and instead set IRQCHIP_SKIP_SET_WAKE?

 I've thought about this and it should work for me.
 One question - what if crossbar will be not the last one in
 IRQ domains hierarchy?


 I can confirm, if I revert this patch, add IRQCHIP_SKIP_SET_WAKE to
 the crossbar and remove irq_chip_set_wake_parent wakeups still works.
 What do you prefer me to do: add additional patch for the crossbar,
 drop/keep this patch?

 
 OK. There are two possibilities to fix set_wake functionality for TI OMAPs
 where below HW configurations are used:
   OMAP4/5: GIC - OMAP wakeupgen
   DRA7: GIC - OMAP wakeupgen - TI CBAR
 
 
 1) ensure that IRQCHIP_SKIP_SET_WAKE flag is set only for GIC and
 use irq_chip_set_wake_parent() in both wakeupgen and crossbar 
  [this patch is required]
 
 2) ensure that IRQCHIP_SKIP_SET_WAKE flag is set and drop 
 .irq_set_wake()/irq_chip_set_wake_parent() for all IRQ chips
 in IRQ domains hierarchy.
  [this patch can be dropped]
 
 I'm going to select approach 2 and re-send.

Yeah, I'd like to go for the minimal approach for now, and work out what
exactly are the propagation semantics (I had something at some point,
need to find what I did with those patches...).

Thanks,

M.
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Re: [PATCH v2 1/6] genirq: fix irq_chip_retrigger_hierarchy

[Marc Zyngier]

[adding Jiang to the cc list]

On 12/08/15 18:45, Grygorii Strashko wrote:
 Now irq_chip_retrigger_hierarchy() returns -ENOSYS if it
 was not able to find at least one .irq_retrigger() callback
 implemented in IRQ domain hierarchy. As result, IRQ
 re-triggering is not working now on ARM (TI OMAP) where
 ARM GIC is not implemented this callback.
 The .irq_retrigger() is optional (see check_irq_resend())
 and there are no reasons to fail if it was not found, hence
 lets return 0 in this case.
 
 In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
 ARM GIC - OMAP wakeupgen - TI CBAR
 
 Failure is reproduced during resume from suspend to RAM:
 - wakeup by IRQx
 - suspend_enter
   + arch_suspend_enable_irqs
 + handle_fasteoi_irq
   + irq_may_run
 + irq_pm_check_wakeup
   + irq_disable(IRQx)
   + dpm_resume_noirq()
 + resume_device_irqs
   + resume_irqs
 + resume_irq
   + __enable_irq == IRQx is not re-triggered
 
 Fixes: 85f08c17de26 ('genirq: Introduce helper functions...')
 Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
 ---
  kernel/irq/chip.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
 index 27f4332..6de638b 100644
 --- a/kernel/irq/chip.c
 +++ b/kernel/irq/chip.c
 @@ -997,7 +997,7 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
   if (data-chip  data-chip-irq_retrigger)
   return data-chip-irq_retrigger(data);
  
 - return -ENOSYS;
 + return 0;
  }
  
  /**
 

I think this makes sense. Not having an irq_retrigger or having an
irq_retrigger that returns zero are the same thing.

Actually, we don't even distinguish between a retrigger that
successfully poked the HW, and a retrigger that returned an error. Both
are considered to not to require a SW retrigger... maybe we should fix
that too. Jiang, Thomas?

Anyway, for this patch:

Reviewed-by: Marc Zyngier marc.zyng...@arm.com

M.
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Re: [PATCH v2 2/6] genirq: fix irqchip_set_wake_parent if IRQCHIP_SKIP_SET_WAKE

[Marc Zyngier]

On 12/08/15 18:45, Grygorii Strashko wrote:
 The irqchip_set_wake_parent should not fail if IRQ chip
 specifies IRQCHIP_SKIP_SET_WAKE. Otherwise, IRQ wakeup
 configuration can't be propagated properly through IRQ
 domains hierarchy.
 
 In case of TI OMAP DRA7 the issue reproduced with following
 configuration:
 ARM GIC-OMAP wakeupgen-TI CBAR-GPIO-GPIO pcf857x-gpio_key
 
 gpio_key is wakeup source
 
 Failure is reproduced during suspend/resume to RAM:
 suspend:
  - gpio_keys_suspend
enable_irq_wake
  + pcf857x_irq_set_wake
+ omap_gpio_wake_enable
  + TI CBAR irq_chip_set_wake_parent
+ OMAP wakeupgen has no .irq_set_wake()

Most importantly, wakeupgen has IRQCHIP_SKIP_SET_WAKE set.

and -ENOSYS will be returned
 
 resume:
  - gpio_keys_resume
+ disable_irq_wake
  + irq_set_irq_wake
+ WARN(1, Unbalanced IRQ %d wake disable\n, irq);
 
 Fixes: 08b55e2a9208 ('genirq: Add irqchip_set_wake_parent')
 Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
 ---
  kernel/irq/chip.c | 4 
  1 file changed, 4 insertions(+)
 
 diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
 index 6de638b..bdb1b9d 100644
 --- a/kernel/irq/chip.c
 +++ b/kernel/irq/chip.c
 @@ -1024,6 +1024,10 @@ int irq_chip_set_vcpu_affinity_parent(struct irq_data 
 *data, void *vcpu_info)
  int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  {
   data = data-parent_data;
 +
 + if (irq_data_get_irq_chip(data)-flags  IRQCHIP_SKIP_SET_WAKE)
 + return 0;
 +
   if (data-chip-irq_set_wake)
   return data-chip-irq_set_wake(data, on);
  
 

We have a more general issue with chip flags, and how they combine
within a stack of irqchips.

What if you remove the irq_chip_set_wake_parent from the crossbar
driver, and instead set IRQCHIP_SKIP_SET_WAKE?

Thanks,

M.
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Re: [PATCH] ARM: OMAP: irqdomain_hierarchy: fix arm gic irq type configuration

[Marc Zyngier]

On Tue, 11 Aug 2015 10:25:47 +0100
Grygorii Strashko grygorii.stras...@ti.com wrote:

Hi Grygorii,

 It's observed that ARM GIC IRQ triggering type is not configured
 properly when IRQ is routed through IRQ domains hierarchy and
 system started using DT. As result, system will start using default
 ARM GIC configuration, ignore DT IRQ type configuration,
 and value of desc-irq_data.state_use_accessors = 0.
 
 In case of TI OMAP the following IRQ hierarchy is defined:
 ARM GIC - OMAP wakeupgen - TI CBAR
 
 Failed call chain:
  irq_create_of_mapping
  irq_set_irq_type
  __irq_set_trigger
  if (!chip || !chip-irq_set_type) {
 return 0; - return here
  }
  CBAR has no .irq_set_type() defined and, so, IRQ triggering
  configuration will not be propagated to parent IRQ domain.
 
 Hence, fix it by introducing irq_chip_set_type_parent(), in the
 same manner as irq_chip_set_wake_parent(), and use it for IRQ 
 triggering type propagation to the parent IRQ domain in
 irq-crossbar and omap-wakeupgen.
 
 / # cat /proc/interrupts -- before
 230:  0  0  CBAR  30 Edge-  48051000.gpio
 263:  0  0  CBAR 116 Edge-  48053000.gpio
 296:246  0  CBAR  67 Edge-  OMAP UART0
 311:341  0  CBAR  51 Edge-  4807.i2c
 312:  3  0  CBAR  52 Edge-  48072000.i2c
 313:  0  0  CBAR  56 Edge-  4806.i2c
 314:255  0  CBAR  78 Edge-  mmc0
 315: 40  0  CBAR  81 Edge-  mmc1
 316: 13  0  CBAR  91 Edge-  mmc2
 320:  0  0  CBAR  49 Edge-  4a14.sata
 324:  0  0  CBAR   1 Edge-  48078000.elm
 325:  0  0  CBAR  15 Edge-  gpmc
 333:  0  0  CBAR 335 Edge-  48484000.ethernet
 334:  0  0  CBAR 336 Edge-  48484000.ethernet
 415:  0  0   pcf857x   2 Edge-  btnUser1
 416:  0  0   pcf857x   3 Edge-  btnUser2
 445:  0  0   pinctrl 992 Edge-0001  4806a000.seria
 
 / # cat /proc/interrupts -- after
 230:  0  0  CBAR  30 Level   -2004  48051000.gpio
 263:  0  0  CBAR 116 Level   -2004  48053000.gpio
 296:567  0  CBAR  67 Level   -2004  OMAP UART0
 311:363  0  CBAR  51 Level   -2004  4807.i2c
 312:  3  0  CBAR  52 Level   -2004  48072000.i2c
 313:  0  0  CBAR  56 Level   -2004  4806.i2c
 314:197  0  CBAR  78 Level   -2004  mmc0
 315: 40  0  CBAR  81 Level   -2004  mmc1
 316: 13  0  CBAR  91 Level   -2004  mmc2
 320:  0  0  CBAR  49 Level   -2004  4a14.sata
 324:  0  0  CBAR   1 Level   -2004  48078000.elm
 325:  0  0  CBAR  15 Level   -2004  gpmc
 333:  0  0  CBAR 335 Level   -2004  48484000.ethernet
 334:  0  0  CBAR 336 Level   -2004  48484000.ethernet
 415:  0  0   pcf857x   2 Edge-  btnUser1
 416:  4  2   pcf857x   3 Edge-  btnUser2
 445:  0  0   pinctrl 992 Edge-0001  4806a000.serial
 
 Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar to stacked 
 domains')
 Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
 ---
 Hi All,
 
 I can split patch if required and overall solution acceptable.

This looks good to me. Please repost it after splitting it in two
patches.

Thanks,

M.
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Re: [PATCH] ARM: OMAP: irqdomain_hierarchy: fix arm gic irq type configuration

[Marc Zyngier]

On Tue, 11 Aug 2015 13:16:13 +0100
Grygorii Strashko grygorii.stras...@ti.com wrote:

 On 08/11/2015 02:24 PM, Marc Zyngier wrote:
  On Tue, 11 Aug 2015 10:25:47 +0100
  Grygorii Strashko grygorii.stras...@ti.com wrote:
 
  Hi Grygorii,
 
  It's observed that ARM GIC IRQ triggering type is not configured
  properly when IRQ is routed through IRQ domains hierarchy and
  system started using DT. As result, system will start using default
  ARM GIC configuration, ignore DT IRQ type configuration,
  and value of desc-irq_data.state_use_accessors = 0.
 
  In case of TI OMAP the following IRQ hierarchy is defined:
  ARM GIC - OMAP wakeupgen - TI CBAR
 
  Failed call chain:
irq_create_of_mapping
irq_set_irq_type
__irq_set_trigger
if (!chip || !chip-irq_set_type) {
   return 0; - return here
}
CBAR has no .irq_set_type() defined and, so, IRQ triggering
configuration will not be propagated to parent IRQ domain.
 
  Hence, fix it by introducing irq_chip_set_type_parent(), in the
  same manner as irq_chip_set_wake_parent(), and use it for IRQ
  triggering type propagation to the parent IRQ domain in
  irq-crossbar and omap-wakeupgen.
 
  / # cat /proc/interrupts -- before
  230:  0  0  CBAR  30 Edge-  48051000.gpio
  263:  0  0  CBAR 116 Edge-  48053000.gpio
  296:246  0  CBAR  67 Edge-  OMAP UART0
  311:341  0  CBAR  51 Edge-  4807.i2c
  312:  3  0  CBAR  52 Edge-  48072000.i2c
  313:  0  0  CBAR  56 Edge-  4806.i2c
  314:255  0  CBAR  78 Edge-  mmc0
  315: 40  0  CBAR  81 Edge-  mmc1
  316: 13  0  CBAR  91 Edge-  mmc2
  320:  0  0  CBAR  49 Edge-  4a14.sata
  324:  0  0  CBAR   1 Edge-  48078000.elm
  325:  0  0  CBAR  15 Edge-  gpmc
  333:  0  0  CBAR 335 Edge-  
  48484000.ethernet
  334:  0  0  CBAR 336 Edge-  
  48484000.ethernet
  415:  0  0   pcf857x   2 Edge-  btnUser1
  416:  0  0   pcf857x   3 Edge-  btnUser2
  445:  0  0   pinctrl 992 Edge-0001  4806a000.seria
 
  / # cat /proc/interrupts -- after
  230:  0  0  CBAR  30 Level   -2004  48051000.gpio
  263:  0  0  CBAR 116 Level   -2004  48053000.gpio
  296:567  0  CBAR  67 Level   -2004  OMAP UART0
  311:363  0  CBAR  51 Level   -2004  4807.i2c
  312:  3  0  CBAR  52 Level   -2004  48072000.i2c
  313:  0  0  CBAR  56 Level   -2004  4806.i2c
  314:197  0  CBAR  78 Level   -2004  mmc0
  315: 40  0  CBAR  81 Level   -2004  mmc1
  316: 13  0  CBAR  91 Level   -2004  mmc2
  320:  0  0  CBAR  49 Level   -2004  4a14.sata
  324:  0  0  CBAR   1 Level   -2004  48078000.elm
  325:  0  0  CBAR  15 Level   -2004  gpmc
  333:  0  0  CBAR 335 Level   -2004  
  48484000.ethernet
  334:  0  0  CBAR 336 Level   -2004  
  48484000.ethernet
  415:  0  0   pcf857x   2 Edge-  btnUser1
  416:  4  2   pcf857x   3 Edge-  btnUser2
  445:  0  0   pinctrl 992 Edge-0001  4806a000.serial
 
  Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar to stacked 
  domains')
  Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
  ---
  Hi All,
 
  I can split patch if required and overall solution acceptable.
 
  This looks good to me. Please repost it after splitting it in two
  patches.
 
 just to clarify - Do you want to see two or three patches?
 
 2) or 3) arch/arm/mach-omap2/omap-wakeupgen.c |  1 +
 2) drivers/irqchip/irq-crossbar.c   |  1 +
 1) include/linux/irq.h  |  1 +
 1) kernel/irq/chip.c| 16 

Ah, I forgot wakeupgen lived in the omap-specific directory.

Please cut it in 3 then (generic implementation, crossbar and
wakeupgen).

Thanks,

M.


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Re: n900 in 4.1-rc0

[Marc Zyngier]

On 16/04/15 10:32, Pavel Machek wrote:
 Hi!
 
 Just tried booting 4.1-rc0 on n900 (commit
 34c9a0ffc75ad25b6a60f61e27c4a4b1189b8085) and it is broken.
 
 Any ideas?

To such a question, the only answer I have is Yes.

For a more useful reply, I'm afraid you'll have to ask a better question.

Thanks,

M.
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Re: [PATCH] mm/migrate: Mark unmap_and_move() noinline to avoid ICE in gcc 4.7.3

[Marc Zyngier]

On 01/04/15 10:37, Geert Uytterhoeven wrote:
   Hi Kevin,
 
 On Tue, 31 Mar 2015, Kevin Hilman wrote:
 Ard Biesheuvel ard.biesheu...@linaro.org writes:
 Nope, that branch is already part of linux-next, and linux-next still
 fails to compile for 20+ defconfigs[1]

 Could you elaborate on the issue please? What is the error you are
 getting, and can you confirm that is is caused by ld choking on the
 linker script? If not, this is another error than the one we have been
 trying to fix

 It's definitely not linker script related.

 Using arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3,
 here's the error when building for multi_v7_defconfig (full log
 available[2]):

 ../mm/migrate.c: In function 'migrate_pages':
 ../mm/migrate.c:1148:1: internal compiler error: in push_minipool_fix, at 
 config/arm/arm.c:13101
 Please submit a full bug report,
 with preprocessed source if appropriate.
 See file:///usr/share/doc/gcc-4.7/README.Bugs for instructions.
 Preprocessed source stored into /tmp/ccO1Nz1m.out file, please attach
 this to your bugreport.
 make[2]: *** [mm/migrate.o] Error 1
 make[2]: Target `__build' not remade because of errors.
 make[1]: *** [mm] Error 2

 build bisect points to commit 21f992084aeb[3], but that doesn't revert
 cleanly so I haven't got any further than that yet.
 
 I installed gcc-arm-linux-gnueabi (4:4.7.2-1 from Ubuntu 14.04 LTS) and could
 reproduce the ICE. I came up with the workaround below.
 Does this work for you?
 
 From 7ebe83316eaf1952e55a76754ce7a5832e461b8c Mon Sep 17 00:00:00 2001
 From: Geert Uytterhoeven geert+rene...@glider.be
 Date: Wed, 1 Apr 2015 11:22:51 +0200
 Subject: [PATCH] mm/migrate: Mark unmap_and_move() noinline to avoid ICE in
  gcc 4.7.3
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 
 With gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1) :
 
 mm/migrate.c: In function ‘migrate_pages’:
 mm/migrate.c:1148:1: internal compiler error: in push_minipool_fix, at 
 config/arm/arm.c:13500
 Please submit a full bug report,
 with preprocessed source if appropriate.
 See file:///usr/share/doc/gcc-4.7/README.Bugs for instructions.
 Preprocessed source stored into /tmp/ccPoM1tr.out file, please attach 
 this to your bugreport.
 make[1]: *** [mm/migrate.o] Error 1
 make: *** [mm/migrate.o] Error 2
 
 Mark unmap_and_move() (which is used in a single place only) noinline
 to work around this compiler bug.
 
 Reported-by: Kevin Hilman khil...@kernel.org
 Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
 ---
  mm/migrate.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)
 
 diff --git a/mm/migrate.c b/mm/migrate.c
 index 114602a68111d809..98f8574456c2010c 100644
 --- a/mm/migrate.c
 +++ b/mm/migrate.c
 @@ -904,9 +904,10 @@ out:
   * Obtain the lock on page, remove all ptes and migrate the page
   * to the newly allocated page in newpage.
   */
 -static int unmap_and_move(new_page_t get_new_page, free_page_t put_new_page,
 - unsigned long private, struct page *page, int force,
 - enum migrate_mode mode)
 +static noinline int unmap_and_move(new_page_t get_new_page,
 +free_page_t put_new_page,
 +unsigned long private, struct page *page,
 +int force, enum migrate_mode mode)
  {
   int rc = 0;
   int *result = NULL;
 

Ouch. That's really ugly. And on 32bit ARM, we end-up spilling half of
the parameters on the stack, which is not going to help performance
either (not that this would be useful on 32bit ARM anyway...).

Any chance you could make this dependent on some compiler detection
mechanism?

Thanks,

M.
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Re: [PATCH 01/25] arm: Use bool function return values of true/false not 1/0

[Marc Zyngier]

On Tue, 31 Mar 2015 16:58:28 +0100
Paolo Bonzini pbonz...@redhat.com wrote:

 On 31/03/2015 01:45, Joe Perches wrote:
  Use the normal return values for bool functions
  
  Signed-off-by: Joe Perches j...@perches.com
  ---
   arch/arm/include/asm/dma-mapping.h |  8 
   arch/arm/include/asm/kvm_emulate.h |  2 +-
   arch/arm/mach-omap2/powerdomain.c  | 14 +++---
   3 files changed, 12 insertions(+), 12 deletions(-)
  
  diff --git a/arch/arm/include/asm/dma-mapping.h 
  b/arch/arm/include/asm/dma-mapping.h
  index b52101d..166e1e1 100644
  --- a/arch/arm/include/asm/dma-mapping.h
  +++ b/arch/arm/include/asm/dma-mapping.h
  @@ -151,18 +151,18 @@ static inline bool dma_capable(struct device *dev, 
  dma_addr_t addr, size_t size)
  u64 limit, mask;
   
  if (!dev-dma_mask)
  -   return 0;
  +   return false;
   
  mask = *dev-dma_mask;
   
  limit = (mask + 1)  ~mask;
  if (limit  size  limit)
  -   return 0;
  +   return false;
   
  if ((addr | (addr + size - 1))  ~mask)
  -   return 0;
  +   return false;
   
  -   return 1;
  +   return true;
   }
   
   static inline void dma_mark_clean(void *addr, size_t size) { }
  diff --git a/arch/arm/include/asm/kvm_emulate.h 
  b/arch/arm/include/asm/kvm_emulate.h
  index a9c80a2..ad200a0 100644
  --- a/arch/arm/include/asm/kvm_emulate.h
  +++ b/arch/arm/include/asm/kvm_emulate.h
  @@ -51,7 +51,7 @@ static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, 
  unsigned long hcr)
   
   static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
   {
  -   return 1;
  +   return true;
   }
   
   static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
  diff --git a/arch/arm/mach-omap2/powerdomain.c 
  b/arch/arm/mach-omap2/powerdomain.c
  index 78af6d8..897f9fb 100644
  --- a/arch/arm/mach-omap2/powerdomain.c
  +++ b/arch/arm/mach-omap2/powerdomain.c
  @@ -950,7 +950,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
*/
   bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
   {
  -   return (pwrdm  pwrdm-flags  PWRDM_HAS_HDWR_SAR) ? 1 : 0;
  +   return pwrdm  (pwrdm-flags  PWRDM_HAS_HDWR_SAR);
   }
   
   int pwrdm_state_switch_nolock(struct powerdomain *pwrdm)
  @@ -1185,24 +1185,24 @@ bool pwrdm_can_ever_lose_context(struct powerdomain 
  *pwrdm)
  if (!pwrdm) {
  pr_debug(powerdomain: %s: invalid powerdomain pointer\n,
   __func__);
  -   return 1;
  +   return true;
  }
   
  if (pwrdm-pwrsts  PWRSTS_OFF)
  -   return 1;
  +   return true;
   
  if (pwrdm-pwrsts  PWRSTS_RET) {
  if (pwrdm-pwrsts_logic_ret  PWRSTS_OFF)
  -   return 1;
  +   return true;
   
  for (i = 0; i  pwrdm-banks; i++)
  if (pwrdm-pwrsts_mem_ret[i]  PWRSTS_OFF)
  -   return 1;
  +   return true;
  }
   
  for (i = 0; i  pwrdm-banks; i++)
  if (pwrdm-pwrsts_mem_on[i]  PWRSTS_OFF)
  -   return 1;
  +   return true;
   
  -   return 0;
  +   return false;
   }
  
 
 Marc/Christoffer, please pick this up yourself.

Given that it touches a range of completely unrelated files, for the
KVM part:

Acked-by: Marc Zyngier marc.zyng...@arm.com

M.
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Re: [PATCH v6 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

On 13/03/15 17:38, Tony Lindgren wrote:
 * Jason Cooper ja...@lakedaemon.net [150313 10:25]:
 Hey Tony,

 On Fri, Mar 13, 2015 at 08:40:39AM -0700, Tony Lindgren wrote:
 * Marc Zyngier marc.zyng...@arm.com [150311 08:44]:
 This series is extracted from [4], which is trying to remove all
 traces of gic_arch_extn from the tree. As some maintainers are more
 responsive than others (understatement of the year...), I've decided
 to split it per sub-arch, and get it moving, at least partially.

 This series addresses OMAP{4,5} by converting the WUGEN to stacked
 domains. The DRA7 crossbar gets the same treatment.
 ...

  Documentation/devicetree/bindings/arm/gic.txt  |   6 -
  .../devicetree/bindings/arm/omap/crossbar.txt  |  18 +-
  .../interrupt-controller/ti,omap4-wugen-mpu|  33 
  arch/arm/boot/dts/am4372.dtsi  |  11 +-
  arch/arm/boot/dts/am437x-gp-evm.dts|   1 -
  arch/arm/boot/dts/am437x-sk-evm.dts|   1 -
  arch/arm/boot/dts/am43x-epos-evm.dts   |   1 -
  arch/arm/boot/dts/am57xx-beagle-x15.dts|   3 +-
  arch/arm/boot/dts/dra7-evm.dts |   2 +-
  arch/arm/boot/dts/dra7.dtsi|  43 +++--
  arch/arm/boot/dts/dra72-evm.dts|   1 -
  arch/arm/boot/dts/dra72x.dtsi  |   3 +-
  arch/arm/boot/dts/dra74x.dtsi  |   5 +-
  arch/arm/boot/dts/omap4-duovero.dtsi   |   2 -
  arch/arm/boot/dts/omap4-panda-common.dtsi  |   8 +-
  arch/arm/boot/dts/omap4-sdp.dts|   8 +-
  arch/arm/boot/dts/omap4-var-som-om44.dtsi  |   2 -
  arch/arm/boot/dts/omap4.dtsi   |  18 +-
  arch/arm/boot/dts/omap5-cm-t54.dts |   1 -
  arch/arm/boot/dts/omap5-uevm.dts   |   2 -
  arch/arm/boot/dts/omap5.dtsi   |  26 ++-
  arch/arm/mach-omap2/omap-wakeupgen.c   | 128 ++---
  arch/arm/mach-omap2/omap-wakeupgen.h   |   1 -
  arch/arm/mach-omap2/omap4-common.c |  27 +--
  drivers/irqchip/irq-crossbar.c | 210 
 -
  drivers/irqchip/irq-gic.c  |  59 +-
  include/linux/irq.h|   1 +
  include/linux/irqchip/arm-gic.h|   6 -
  include/linux/irqchip/irq-crossbar.h   |  11 --
  kernel/irq/chip.c  |  16 ++
  30 files changed, 376 insertions(+), 278 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
  delete mode 100644 include/linux/irqchip/irq-crossbar.h

 For merging this, how about Marc sets up an immutable branch against
 v4.0-rc1 that both Jason and I can merge it in? Then Jason can
 send the pull request I can sort out the merge conflict issues.

 If you don't mind, I'll create the branch.  I tend to fixup some nitpicks 
 when
 I apply patches for irqchip.  If there are any nits you'd like me to fix 
 while
 I'm applying, just let me know.
 
 That works for me thanks as long as it works for Marc.

Definitely works for me. I just want to get rid of these patches! ;-)

Thanks,

M.
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[PATCH v6 6/7] DT: omap4/5: add binding for the wake-up generator

[Marc Zyngier]

Add a binding for the OMAP4/5 wake-up generator, which acts as
an interrupt controller feeding into the GIC.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+  ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+
+Example:
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
+   };
-- 
2.1.4

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[PATCH v6 2/7] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts |   3 +-
 arch/arm/boot/dts/dra7-evm.dts  |   2 +-
 arch/arm/boot/dts/dra7.dtsi |  35 +++---
 arch/arm/boot/dts/dra72-evm.dts |   1 -
 arch/arm/boot/dts/dra72x.dtsi   |   3 +-
 arch/arm/boot/dts/dra74x.dtsi   |   5 +-
 arch/arm/mach-omap2/omap4-common.c  |   4 -
 drivers/irqchip/irq-crossbar.c  | 210 +++-
 include/linux/irqchip/irq-crossbar.h|  11 --
 9 files changed, 149 insertions(+), 125 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts 
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af..170fbf9 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -454,7 +454,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
-   interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW;  /* IRQ_SYS_1N */
 
pinctrl-names = default;
@@ -477,7 +476,7 @@
 
 uart3 {
status = okay;
-   interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x248;
 
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 746cddb..789ee58 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -446,7 +446,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
-   interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x3e0;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fed..850f949 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
 #include skeleton.dtsi
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
#address-cells = 1;
#size-cells = 1;
 
compatible = ti,dra7xx;
-   interrupt-parent = gic;
+   interrupt-parent = crossbar_mpu;
 
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
 GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
-   arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
  0x48212000 0x1000,
  0x48214000 0x2000,
  0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
  0x4500 0x1000;
-   interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 4 
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
 
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
-   interrupts-extended = gic GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
-   interrupts-extended = gic GIC_SPI 68 
IRQ_TYPE_LEVEL_HIGH

[PATCH v6 5/7] DT: arm,gic: kill arm,routable-irqs

[Marc Zyngier]

Nobody will regret it.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/gic.txt | 6 --
 1 file changed, 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt 
b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b..1e0d212 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
 Example:
 
intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
-   arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
  0xfff10100 0x100;
};
-- 
2.1.4

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[PATCH v6 7/7] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.

On a platform with this patch applied, the system looks like
this:

root@bacon-fat:~# cat /proc/interrupts
CPU0   CPU1
 16:  0  0 WUGEN  37  gp_timer
 19: 233799 155916   GIC  27  arch_timer
 23:  0  0 WUGEN   9  l3-dbg-irq
 24:  1  0 WUGEN  10  l3-app-irq
 27:282  0 WUGEN  13  omap-dma-engine
 44:  0  0  4ae1.gpio  13  DMA
294:  0  0 WUGEN  20  gpmc
297:506  0 WUGEN  56  4807.i2c
298:  0  0 WUGEN  57  48072000.i2c
299:  0  0 WUGEN  61  4806.i2c
300:  0  0 WUGEN  62  4807a000.i2c
301:  8  0 WUGEN  60  4807c000.i2c
308:   2439  0 WUGEN  74  OMAP UART2
312:362  0 WUGEN  83  mmc2
313:502  0 WUGEN  86  mmc0
314: 13  0 WUGEN  94  mmc1
350:  0  0  PRCM  pinctrl, pinctrl
406:   35155709  0   GIC 109  ehci_hcd:usb1
407:  0  0 WUGEN   7  palmas
409:  0  0 WUGEN 119  twl6040
410:  0  0   twl6040   5  twl6040_irq_ready
411:  0  0   twl6040   0  twl6040_irq_th
IPI0:  0  1  CPU wakeup interrupts
IPI1:  0  0  Timer broadcast interrupts
IPI2:  95334 902334  Rescheduling interrupts
IPI3:  0  0  Function call interrupts
IPI4:479648  Single function call interrupts
IPI5:  0  0  CPU stop interrupts
IPI6:  0  0  IRQ work interrupts
IPI7:  0  0  completion interrupts
Err:  0

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am4372.dtsi |  11 ++-
 arch/arm/boot/dts/am437x-gp-evm.dts   |   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts   |   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts  |   1 -
 arch/arm/boot/dts/dra7.dtsi   |  12 ++-
 arch/arm/boot/dts/dra72x.dtsi |   2 +-
 arch/arm/boot/dts/dra74x.dtsi |   2 +-
 arch/arm/boot/dts/omap4-duovero.dtsi  |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts   |   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi |   2 -
 arch/arm/boot/dts/omap4.dtsi  |  18 -
 arch/arm/boot/dts/omap5-cm-t54.dts|   1 -
 arch/arm/boot/dts/omap5-uevm.dts  |   2 -
 arch/arm/boot/dts/omap5.dtsi  |  26 +++---
 arch/arm/mach-omap2/omap-wakeupgen.c  | 128 +++---
 arch/arm/mach-omap2/omap-wakeupgen.h  |   1 -
 arch/arm/mach-omap2/omap4-common.c|  23 +++---
 18 files changed, 171 insertions(+), 78 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc3..8a099bc 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 
 / {
compatible = ti,am4372, ti,am43;
-   interrupt-parent = gic;
+   interrupt-parent = wakeupgen;
 
 
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
  0x48240100 0x0100;
+   interrupt-parent = gic;
+   };
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
};
 
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts 
b/arch/arm/boot/dts/am437x-gp-evm.dts
index f84d971..26956cb 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -352,7 +352,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts 
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 832d243..8ae29c9 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -392,7 +392,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
-   interrupt-parent

[PATCH v6 4/7] irqchip: GIC: get rid of routable domain

[Marc Zyngier]

The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 59 -
 include/linux/irqchip/arm-gic.h |  6 -
 2 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4634cf7..e3ca6da 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -798,15 +798,12 @@ static int gic_irq_domain_map(struct irq_domain *d, 
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-   gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-   gic_routable_irq_domain_ops-unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -825,16 +822,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
 
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-   if (!intspec[0]) {
-   ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
-   if (IS_ERR_VALUE(ret))
-   return ret;
-   }
+   if (!intspec[0])
+   *out_hwirq += 16;
 
*out_type = intspec[2]  IRQ_TYPE_SENSE_MASK;
 
@@ -891,37 +880,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
-   return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-   struct device_node *controller,
-   const u32 *intspec, unsigned int intsize,
-   unsigned long *out_hwirq,
-   unsigned int *out_type)
-{
-   *out_hwirq += 16;
-   return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-   .map = gic_routable_irq_domain_map,
-   .unmap = gic_routable_irq_domain_unmap,
-   .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-   gic_default_routable_irq_domain_ops;
-
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
@@ -929,7 +887,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
-   int nr_routable_irqs;
 
BUG_ON(gic_nr = MAX_GIC_NR);
 
@@ -985,15 +942,9 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
gic-gic_irqs = gic_irqs;
 
if (node) { /* DT case */
-   const struct irq_domain_ops *ops = 
gic_irq_domain_hierarchy_ops;
-
-   if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
-   ops = gic_irq_domain_ops;
-   gic_irqs = nr_routable_irqs;
-   }
-
-   gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+   gic-domain = irq_domain_add_linear(node, gic_irqs,
+   
gic_irq_domain_hierarchy_ops,
+   gic);
} else {/* Non-DT case */
/*
 * For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-   (const struct irq_domain_ops *ops

[PATCH v6 3/7] DT: update ti,irq-crossbar binding

[Marc Zyngier]

Make it look like a real interrupt controller.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../devicetree/bindings/arm/omap/crossbar.txt  | 18 +-
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt 
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be ti,irq-crossbar
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt 
controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be 
routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-   crossbar_mpu: @4a02 {
+   crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
-   ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+   ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further 
details.
 
 An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as 
a
-quirky hardware mapping direct to GIC.
 
 Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
-   device_y@0x4a033000 {
-   /* Direct mapped GIC SPI 1 used */
-   interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
-   ...
-   };
-- 
2.1.4

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[PATCH v6 1/7] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.

Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 include/linux/irq.h |  1 +
 kernel/irq/chip.c   | 16 
 2 files changed, 17 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 /* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data:  Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this 
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+   data = data-parent_data;
+   if (data-chip-irq_set_wake)
+   return data-chip-irq_set_wake(data, on);
+
+   return -ENOSYS;
+}
 #endif
 
 /**
-- 
2.1.4

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[PATCH v6 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

This series is extracted from [4], which is trying to remove all
traces of gic_arch_extn from the tree. As some maintainers are more
responsive than others (understatement of the year...), I've decided
to split it per sub-arch, and get it moving, at least partially.

This series addresses OMAP{4,5} by converting the WUGEN to stacked
domains. The DRA7 crossbar gets the same treatment.

It is worth realizing that:

- I haven't been able to test this as much as I would have wanted to
  (it's only been tested on omap4 and omap5).

- This actively *breaks* existing setups. Once you boot a new kernel
  with an old DT, suspend/resume *will* be broken. Old kernels on a
  new DT won't even boot! You've been warned. This really outline the
  necessity of actually describing the HW in device trees...

Based on 4.0-rc1.

* From v5: [5]
- Allow interrupt affinity to be changed

* From v4: [4]
- Extracted from the full series
- Rebased on 4.0-rc1

* From v3 [3]:
- Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
- Fixed more iMX6 DTs (Stephan)
- Fixed Exynos4/5 DTs

* From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan

* From v1 [1]:
- Rebased on 3.19-rc3
- Fixed a number of additional platforms
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth

[5]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325178.html
[4]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html
[3]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
[2]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
[1]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html

Marc Zyngier (7):
  genirq: Add irqchip_set_wake_parent
  irqchip: crossbar: convert dra7 crossbar to stacked domains
  DT: update ti,irq-crossbar binding
  irqchip: GIC: get rid of routable domain
  DT: arm,gic: kill arm,routable-irqs
  DT: omap4/5: add binding for the wake-up generator
  ARM: omap: convert wakeupgen to stacked domains

 Documentation/devicetree/bindings/arm/gic.txt  |   6 -
 .../devicetree/bindings/arm/omap/crossbar.txt  |  18 +-
 .../interrupt-controller/ti,omap4-wugen-mpu|  33 
 arch/arm/boot/dts/am4372.dtsi  |  11 +-
 arch/arm/boot/dts/am437x-gp-evm.dts|   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts|   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts   |   1 -
 arch/arm/boot/dts/am57xx-beagle-x15.dts|   3 +-
 arch/arm/boot/dts/dra7-evm.dts |   2 +-
 arch/arm/boot/dts/dra7.dtsi|  43 +++--
 arch/arm/boot/dts/dra72-evm.dts|   1 -
 arch/arm/boot/dts/dra72x.dtsi  |   3 +-
 arch/arm/boot/dts/dra74x.dtsi  |   5 +-
 arch/arm/boot/dts/omap4-duovero.dtsi   |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi  |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts|   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi  |   2 -
 arch/arm/boot/dts/omap4.dtsi   |  18 +-
 arch/arm/boot/dts/omap5-cm-t54.dts |   1 -
 arch/arm/boot/dts/omap5-uevm.dts   |   2 -
 arch/arm/boot/dts/omap5.dtsi   |  26 ++-
 arch/arm/mach-omap2/omap-wakeupgen.c   | 128 ++---
 arch/arm/mach-omap2/omap-wakeupgen.h   |   1 -
 arch/arm/mach-omap2/omap4-common.c |  27 +--
 drivers/irqchip/irq-crossbar.c | 210 -
 drivers/irqchip/irq-gic.c  |  59 +-
 include/linux/irq.h|   1 +
 include/linux/irqchip/arm-gic.h|   6 -
 include/linux/irqchip/irq-crossbar.h   |  11 --
 kernel/irq/chip.c  |  16 ++
 30 files changed, 376 insertions(+), 278 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

-- 
2.1.4

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Re: [PATCH v5 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

On 23/02/15 23:02, Tony Lindgren wrote:
 * Marc Zyngier marc.zyng...@arm.com [150223 09:48]:
 This series is extracted from [4], which is trying to remove all
 traces of gic_arch_extn from the tree. As some maintainers are more
 responsive than others (understatement of the year...), I've decided
 to split it per sub-arch, and get it moving, at least partially.

 This series addresses OMAP{4,5} by converting the WUGEN to stacked
 domains. The DRA7 crossbar gets the same treatment.

 It is worth realizing that:

 - I haven't been able to test this as much as I would have wanted to
   (it's only been tested on omap4 and omap5).

 - This actively *breaks* existing setups. Once you boot a new kernel
   with an old DT, suspend/resume *will* be broken. Old kernels on a
   new DT won't even boot! You've been warned. This really outline the
   necessity of actually describing the HW in device trees...
 
 Could we parse still the old binding and produce warning for the
 case when a new kernel is booted with the old DT? That would make
 it easier for people to debug what's going on.

There's a number of strategies:
- Looking up the default, top-level interrupt controller:
  if that's the GIC, scream.
- Lookup the crossbar:
  if it exists, but is not an interrupt controller, scream as well.
- Lookup the WUGEN:
  if it doesn't exist, scream again.

The last one is pretty easy to implement:

diff --git a/arch/arm/mach-omap2/omap4-common.c 
b/arch/arm/mach-omap2/omap4-common.c
index fba1ba7..7bb116a 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -277,6 +277,12 @@ void __init omap_gic_of_init(void)
 {
struct device_node *np;
 
+   intc_node = of_find_matching_node(NULL, intc_match);
+   if (WARN_ON(!intc_node)) {
+   pr_err(No WUGEN found in DT, system will misbehave.\n);
+   pr_err(UPDATE YOUR DEVICE TREE!\n);
+   }
+
/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
if (!cpu_is_omap446x())
goto skip_errata_init;

This should cover both OMAP4, OMAP5 and DRA7.

What do you think?

M.
-- 
Jazz is not dead. It just smells funny...
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Re: [PATCH v5 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

On 24/02/15 03:45, Subramaniam Chanderashekarapuram wrote:
 
 Tested this on  DRA7 for smp_affinity. Needs these minor fixes attached.
 
 Note: I do not have a OMAP4/5 with me now. Hope to test that tomorrow.
 
 Log for DRA7 are here:
 http://pastebin.ubuntu.com/10382176/

Looks good to me. I've folded that into the existing series.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...
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Re: [PATCH v5 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

On 23/02/15 20:39, Nishanth Menon wrote:
 On 02/23/2015 02:32 PM, Nishanth Menon wrote:
 On 17:44-20150223, Marc Zyngier wrote:
 This series is extracted from [4], which is trying to remove all
 traces of gic_arch_extn from the tree. As some maintainers are more
 responsive than others (understatement of the year...), I've decided
 to split it per sub-arch, and get it moving, at least partially.

 This series addresses OMAP{4,5} by converting the WUGEN to stacked
 domains. The DRA7 crossbar gets the same treatment.

 It is worth realizing that:

 - I haven't been able to test this as much as I would have wanted to
   (it's only been tested on omap4 and omap5).

 - This actively *breaks* existing setups. Once you boot a new kernel
   with an old DT, suspend/resume *will* be broken. Old kernels on a
   new DT won't even boot! You've been warned. This really outline the
   necessity of actually describing the HW in device trees...

 Based on 4.0-rc1.

 * From v4: [4]
 - Extracted from the full series
 - Rebased on 4.0-rc1

 * From v3 [3]:
 - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
 - Fixed more iMX6 DTs (Stephan)
 - Fixed Exynos4/5 DTs

 * From v2 [2]:
 - Addressed numerous comments from Thierry
 - Merged bug fixes from Nishanth
 - Merged bug fix from Stefan

 * From v1 [1]:
 - Rebased on 3.19-rc3
 - Fixed a number of additional platforms
 - Added crossbar conversion to stacked domains
 - Merged bug fixes from Nishanth

 [4]: 
 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html
 [3]: 
 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
 [2]: 
 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
 [1]: 
 http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html

 Marc Zyngier (7):
   genirq: Add irqchip_set_wake_parent
   irqchip: crossbar: convert dra7 crossbar to stacked domains
   DT: update ti,irq-crossbar binding
   irqchip: GIC: get rid of routable domain
   DT: arm,gic: kill arm,routable-irqs
   DT: omap4/5: add binding for the wake-up generator
   ARM: omap: convert wakeupgen to stacked domains

  Documentation/devicetree/bindings/arm/gic.txt  |   6 -
  .../devicetree/bindings/arm/omap/crossbar.txt  |  18 +-
  .../interrupt-controller/ti,omap4-wugen-mpu|  33 
  arch/arm/boot/dts/am4372.dtsi  |  11 +-
  arch/arm/boot/dts/am437x-gp-evm.dts|   1 -
  arch/arm/boot/dts/am437x-sk-evm.dts|   1 -
  arch/arm/boot/dts/am43x-epos-evm.dts   |   1 -
  arch/arm/boot/dts/am57xx-beagle-x15.dts|   3 +-
  arch/arm/boot/dts/dra7-evm.dts |   2 +-
  arch/arm/boot/dts/dra7.dtsi|  43 +++--
  arch/arm/boot/dts/dra72-evm.dts|   1 -
  arch/arm/boot/dts/dra72x.dtsi  |   3 +-
  arch/arm/boot/dts/dra74x.dtsi  |   5 +-
  arch/arm/boot/dts/omap4-duovero.dtsi   |   2 -
  arch/arm/boot/dts/omap4-panda-common.dtsi  |   8 +-
  arch/arm/boot/dts/omap4-sdp.dts|   8 +-
  arch/arm/boot/dts/omap4-var-som-om44.dtsi  |   2 -
  arch/arm/boot/dts/omap4.dtsi   |  18 +-
  arch/arm/boot/dts/omap5-cm-t54.dts |   1 -
  arch/arm/boot/dts/omap5-uevm.dts   |   2 -
  arch/arm/boot/dts/omap5.dtsi   |  26 ++-
  arch/arm/mach-omap2/omap-wakeupgen.c   | 125 ++---
  arch/arm/mach-omap2/omap-wakeupgen.h   |   1 -
  arch/arm/mach-omap2/omap4-common.c |  21 +--
  drivers/irqchip/irq-crossbar.c | 207 
 -
  drivers/irqchip/irq-gic.c  |  59 +-
  include/linux/irq.h|   1 +
  include/linux/irqchip/arm-gic.h|   6 -
  include/linux/irqchip/irq-crossbar.h   |  11 --
  kernel/irq/chip.c  |  16 ++
  30 files changed, 364 insertions(+), 278 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
  delete mode 100644 include/linux/irqchip/irq-crossbar.h

 marc-test-irq (Applied the series to v4.0-rc1) - boot logs:
  1: am335x-evm: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469913
  2:  am335x-sk: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469914
  3: am3517-evm: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469915
  4:  am37x-evm: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469916
  5:  am437x-sk: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469917
  6:am43xx-epos: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469918
  7:   am43xx-gpevm: BOOT: PASS: 
 http://paste.ubuntu.org.cn/2469919
  8: BeagleBoard-XM: BOOT: PASS: 
 http

[PATCH v5 6/7] DT: omap4/5: add binding for the wake-up generator

[Marc Zyngier]

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+  ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+
+Example:
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
+   };
-- 
2.1.4

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[PATCH v5 3/7] DT: update ti,irq-crossbar binding

[Marc Zyngier]

Make it look like a real interrupt controller.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../devicetree/bindings/arm/omap/crossbar.txt  | 18 +-
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt 
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be ti,irq-crossbar
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt 
controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be 
routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-   crossbar_mpu: @4a02 {
+   crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
-   ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+   ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further 
details.
 
 An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as 
a
-quirky hardware mapping direct to GIC.
 
 Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
-   device_y@0x4a033000 {
-   /* Direct mapped GIC SPI 1 used */
-   interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
-   ...
-   };
-- 
2.1.4

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[PATCH v5 7/7] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.

On a platform with this patch applied, the system looks like
this:

root@bacon-fat:~# cat /proc/interrupts
CPU0   CPU1
 16:  0  0 WUGEN  37  gp_timer
 19: 233799 155916   GIC  27  arch_timer
 23:  0  0 WUGEN   9  l3-dbg-irq
 24:  1  0 WUGEN  10  l3-app-irq
 27:282  0 WUGEN  13  omap-dma-engine
 44:  0  0  4ae1.gpio  13  DMA
294:  0  0 WUGEN  20  gpmc
297:506  0 WUGEN  56  4807.i2c
298:  0  0 WUGEN  57  48072000.i2c
299:  0  0 WUGEN  61  4806.i2c
300:  0  0 WUGEN  62  4807a000.i2c
301:  8  0 WUGEN  60  4807c000.i2c
308:   2439  0 WUGEN  74  OMAP UART2
312:362  0 WUGEN  83  mmc2
313:502  0 WUGEN  86  mmc0
314: 13  0 WUGEN  94  mmc1
350:  0  0  PRCM  pinctrl, pinctrl
406:   35155709  0   GIC 109  ehci_hcd:usb1
407:  0  0 WUGEN   7  palmas
409:  0  0 WUGEN 119  twl6040
410:  0  0   twl6040   5  twl6040_irq_ready
411:  0  0   twl6040   0  twl6040_irq_th
IPI0:  0  1  CPU wakeup interrupts
IPI1:  0  0  Timer broadcast interrupts
IPI2:  95334 902334  Rescheduling interrupts
IPI3:  0  0  Function call interrupts
IPI4:479648  Single function call interrupts
IPI5:  0  0  CPU stop interrupts
IPI6:  0  0  IRQ work interrupts
IPI7:  0  0  completion interrupts
Err:  0

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am4372.dtsi |  11 ++-
 arch/arm/boot/dts/am437x-gp-evm.dts   |   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts   |   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts  |   1 -
 arch/arm/boot/dts/dra7.dtsi   |  12 ++-
 arch/arm/boot/dts/dra72x.dtsi |   2 +-
 arch/arm/boot/dts/dra74x.dtsi |   2 +-
 arch/arm/boot/dts/omap4-duovero.dtsi  |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts   |   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi |   2 -
 arch/arm/boot/dts/omap4.dtsi  |  18 -
 arch/arm/boot/dts/omap5-cm-t54.dts|   1 -
 arch/arm/boot/dts/omap5-uevm.dts  |   2 -
 arch/arm/boot/dts/omap5.dtsi  |  26 ---
 arch/arm/mach-omap2/omap-wakeupgen.c  | 125 +++---
 arch/arm/mach-omap2/omap-wakeupgen.h  |   1 -
 arch/arm/mach-omap2/omap4-common.c|  17 ++--
 18 files changed, 162 insertions(+), 78 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc3..8a099bc 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 
 / {
compatible = ti,am4372, ti,am43;
-   interrupt-parent = gic;
+   interrupt-parent = wakeupgen;
 
 
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
  0x48240100 0x0100;
+   interrupt-parent = gic;
+   };
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
};
 
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts 
b/arch/arm/boot/dts/am437x-gp-evm.dts
index f84d971..26956cb 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -352,7 +352,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts 
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 832d243..8ae29c9 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -392,7 +392,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
-   interrupt-parent = gic;
interrupts = GIC_SPI 7

[PATCH v5 0/7] irqchip: Move OMAP{4,5}/DRA7 to use stacked domains

[Marc Zyngier]

This series is extracted from [4], which is trying to remove all
traces of gic_arch_extn from the tree. As some maintainers are more
responsive than others (understatement of the year...), I've decided
to split it per sub-arch, and get it moving, at least partially.

This series addresses OMAP{4,5} by converting the WUGEN to stacked
domains. The DRA7 crossbar gets the same treatment.

It is worth realizing that:

- I haven't been able to test this as much as I would have wanted to
  (it's only been tested on omap4 and omap5).

- This actively *breaks* existing setups. Once you boot a new kernel
  with an old DT, suspend/resume *will* be broken. Old kernels on a
  new DT won't even boot! You've been warned. This really outline the
  necessity of actually describing the HW in device trees...

Based on 4.0-rc1.

* From v4: [4]
- Extracted from the full series
- Rebased on 4.0-rc1

* From v3 [3]:
- Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
- Fixed more iMX6 DTs (Stephan)
- Fixed Exynos4/5 DTs

* From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan

* From v1 [1]:
- Rebased on 3.19-rc3
- Fixed a number of additional platforms
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth

[4]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317531.html
[3]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
[2]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
[1]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html

Marc Zyngier (7):
  genirq: Add irqchip_set_wake_parent
  irqchip: crossbar: convert dra7 crossbar to stacked domains
  DT: update ti,irq-crossbar binding
  irqchip: GIC: get rid of routable domain
  DT: arm,gic: kill arm,routable-irqs
  DT: omap4/5: add binding for the wake-up generator
  ARM: omap: convert wakeupgen to stacked domains

 Documentation/devicetree/bindings/arm/gic.txt  |   6 -
 .../devicetree/bindings/arm/omap/crossbar.txt  |  18 +-
 .../interrupt-controller/ti,omap4-wugen-mpu|  33 
 arch/arm/boot/dts/am4372.dtsi  |  11 +-
 arch/arm/boot/dts/am437x-gp-evm.dts|   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts|   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts   |   1 -
 arch/arm/boot/dts/am57xx-beagle-x15.dts|   3 +-
 arch/arm/boot/dts/dra7-evm.dts |   2 +-
 arch/arm/boot/dts/dra7.dtsi|  43 +++--
 arch/arm/boot/dts/dra72-evm.dts|   1 -
 arch/arm/boot/dts/dra72x.dtsi  |   3 +-
 arch/arm/boot/dts/dra74x.dtsi  |   5 +-
 arch/arm/boot/dts/omap4-duovero.dtsi   |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi  |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts|   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi  |   2 -
 arch/arm/boot/dts/omap4.dtsi   |  18 +-
 arch/arm/boot/dts/omap5-cm-t54.dts |   1 -
 arch/arm/boot/dts/omap5-uevm.dts   |   2 -
 arch/arm/boot/dts/omap5.dtsi   |  26 ++-
 arch/arm/mach-omap2/omap-wakeupgen.c   | 125 ++---
 arch/arm/mach-omap2/omap-wakeupgen.h   |   1 -
 arch/arm/mach-omap2/omap4-common.c |  21 +--
 drivers/irqchip/irq-crossbar.c | 207 -
 drivers/irqchip/irq-gic.c  |  59 +-
 include/linux/irq.h|   1 +
 include/linux/irqchip/arm-gic.h|   6 -
 include/linux/irqchip/irq-crossbar.h   |  11 --
 kernel/irq/chip.c  |  16 ++
 30 files changed, 364 insertions(+), 278 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

-- 
2.1.4

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[PATCH v5 2/7] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts |   3 +-
 arch/arm/boot/dts/dra7-evm.dts  |   2 +-
 arch/arm/boot/dts/dra7.dtsi |  35 +++---
 arch/arm/boot/dts/dra72-evm.dts |   1 -
 arch/arm/boot/dts/dra72x.dtsi   |   3 +-
 arch/arm/boot/dts/dra74x.dtsi   |   5 +-
 arch/arm/mach-omap2/omap4-common.c  |   4 -
 drivers/irqchip/irq-crossbar.c  | 207 ++--
 include/linux/irqchip/irq-crossbar.h|  11 --
 9 files changed, 146 insertions(+), 125 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts 
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af..170fbf9 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -454,7 +454,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
-   interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW;  /* IRQ_SYS_1N */
 
pinctrl-names = default;
@@ -477,7 +476,7 @@
 
 uart3 {
status = okay;
-   interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x248;
 
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 746cddb..789ee58 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -446,7 +446,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
-   interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x3e0;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fed..850f949 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
 #include skeleton.dtsi
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
#address-cells = 1;
#size-cells = 1;
 
compatible = ti,dra7xx;
-   interrupt-parent = gic;
+   interrupt-parent = crossbar_mpu;
 
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
 GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
-   arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
  0x48212000 0x1000,
  0x48214000 0x2000,
  0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
  0x4500 0x1000;
-   interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 4 
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
 
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
-   interrupts-extended = gic GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
-   interrupts-extended = gic GIC_SPI 68 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH

[PATCH v5 5/7] DT: arm,gic: kill arm,routable-irqs

[Marc Zyngier]

Nobody will regret it.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/gic.txt | 6 --
 1 file changed, 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt 
b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b..1e0d212 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
 Example:
 
intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
-   arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
  0xfff10100 0x100;
};
-- 
2.1.4

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[PATCH v5 4/7] irqchip: GIC: get rid of routable domain

[Marc Zyngier]

The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 59 -
 include/linux/irqchip/arm-gic.h |  6 -
 2 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4634cf7..e3ca6da 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -798,15 +798,12 @@ static int gic_irq_domain_map(struct irq_domain *d, 
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-   gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-   gic_routable_irq_domain_ops-unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -825,16 +822,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
 
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-   if (!intspec[0]) {
-   ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
-   if (IS_ERR_VALUE(ret))
-   return ret;
-   }
+   if (!intspec[0])
+   *out_hwirq += 16;
 
*out_type = intspec[2]  IRQ_TYPE_SENSE_MASK;
 
@@ -891,37 +880,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
-   return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-   struct device_node *controller,
-   const u32 *intspec, unsigned int intsize,
-   unsigned long *out_hwirq,
-   unsigned int *out_type)
-{
-   *out_hwirq += 16;
-   return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-   .map = gic_routable_irq_domain_map,
-   .unmap = gic_routable_irq_domain_unmap,
-   .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-   gic_default_routable_irq_domain_ops;
-
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
@@ -929,7 +887,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
-   int nr_routable_irqs;
 
BUG_ON(gic_nr = MAX_GIC_NR);
 
@@ -985,15 +942,9 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
gic-gic_irqs = gic_irqs;
 
if (node) { /* DT case */
-   const struct irq_domain_ops *ops = 
gic_irq_domain_hierarchy_ops;
-
-   if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
-   ops = gic_irq_domain_ops;
-   gic_irqs = nr_routable_irqs;
-   }
-
-   gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+   gic-domain = irq_domain_add_linear(node, gic_irqs,
+   
gic_irq_domain_hierarchy_ops,
+   gic);
} else {/* Non-DT case */
/*
 * For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-   (const struct irq_domain_ops *ops)
-{
-   gic_routable_irq_domain_ops = ops

[PATCH v5 1/7] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 include/linux/irq.h |  1 +
 kernel/irq/chip.c   | 16 
 2 files changed, 17 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 /* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data:  Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this 
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+   data = data-parent_data;
+   if (data-chip-irq_set_wake)
+   return data-chip-irq_set_wake(data, on);
+
+   return -ENOSYS;
+}
 #endif
 
 /**
-- 
2.1.4

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Re: [PATCH v4 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

On 21/01/15 16:30, Tony Lindgren wrote:
 * Marc Zyngier marc.zyng...@arm.com [150119 01:48]:
 OMAP4/5 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the WUGEN HW block, kernels with this patch applied
 won't have any suspend-resume facility when booted with old DTs,
 and old kernels with updated DTs won't even boot.

 On a platform with this patch applied, the system looks like
 this:

 root@bacon-fat:~# cat /proc/interrupts
 CPU0   CPU1
  16:  0  0 WUGEN  37  gp_timer
  19: 233799 155916   GIC  27  arch_timer
  23:  0  0 WUGEN   9  l3-dbg-irq
  24:  1  0 WUGEN  10  l3-app-irq
  27:282  0 WUGEN  13  omap-dma-engine
  44:  0  0  4ae1.gpio  13  DMA
 
 You may want to update this part for the fix :)

Ah, yes. Thanks for noticing this.

 I gave this a quick boot test on am437x-gp-evm and the
 interrupts look OK with the fix also applied:
 
 # cat /proc/interrupts 
 CPU0   
  16:657 WUGEN  68  gp_timer
  18:  0 WUGEN   9  l3-dbg-irq
  19:  0 WUGEN  10  l3-app-irq
  20:  5 WUGEN  12  edma
  22:  0 WUGEN  14  edma_error
  23: 96 WUGEN  72  OMAP UART0
  33:  0  44e07000.gpio   6  mmc0
 158: 52 WUGEN  70  44e0b000.i2c
 159:  0 WUGEN  71  4802a000.i2c
 160: 35 WUGEN  64  mmc0
 161:  0 WUGEN  40  4a10.ethernet
 162:   7739 WUGEN  41  4a10.ethernet
 163:   7608 WUGEN  42  4a10.ethernet
 164:  0 WUGEN  43  4a10.ethernet
 170:  0 WUGEN 100  gpmc
 180:  0 WUGEN   7  tps65218
 IPI0:  0  CPU wakeup interrupts
 IPI1:  0  Timer broadcast interrupts
 IPI2:  0  Rescheduling interrupts
 IPI3:  0  Function call interrupts
 IPI4:  0  Single function call interrupts
 IPI5:  0  CPU stop interrupts
 IPI6:  0  IRQ work interrupts
 IPI7:  0  completion interrupts
 Err:  0

Interesting. No TWD timer on this one?

 Also verified that suspend and resume to a serial console event
 works on omap4430-sdp. So please feel free to add:
 
 Acked-by: Tony Lindgren t...@atomide.com

Thanks,

M.
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Re: [PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains

[Marc Zyngier]

Hi Pankaj,

On 2015-01-20 07:42, Pankaj Dubey wrote:

Hi Marc,

On Monday 19 January 2015 03:14 PM, Marc Zyngier wrote:

Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.

Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---


I tested this patch series on SMDK5250 board.

With the addition of #interrupt-cells = 3;in PMU device node S2R
is working on Exynos5250 based SMDK board.


Thanks for letting me know. Can I add your Tested-by tag on this?


  arch/arm/boot/dts/exynos4.dtsi|   4 ++
  arch/arm/boot/dts/exynos5250.dtsi |   4 ++
  arch/arm/boot/dts/exynos5420.dtsi |   4 ++
  arch/arm/mach-exynos/exynos.c |  14 ++---
  arch/arm/mach-exynos/suspend.c| 122 
++

  5 files changed, 129 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi 
b/arch/arm/boot/dts/exynos4.dtsi

index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};

dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+   interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi

index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};

sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi

index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};

@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};

sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c 
b/arch/arm/mach-exynos/exynos.c

index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
  }

+/*
+ * Apparently, these SoCs are not able to wake-up from suspend 
using

+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
  static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },


As I know Exynos3250, S2R support has been added in kgene/for-next
and should work as expected so we may need to do update
exynos_wkup_irq for exynos3250 and remove it from this list, so 
that

it's S2R should not break. I am adding concern engineer (+cc: Chanwoo
Choi) in the loop.


That would have to be an additional patch, unless we decide to delay 
this series.


Thanks,

M.
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[PATCH v4 00/21] irqchip: gic: killing gic_arch_extn and co, slowly

[Marc Zyngier]

The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea (let's use it to put some new custom hack in there...).

But now that stacked irq domains have been merged into 3.19, the time
has come for gic_arch_extn to meet the Big Bit Bucket.

This patch series takes several steps towards the elimination of
gic_arch_extn:

- moves Tegra's legacy interrupt controller support to
  drivers/irqchip, implementing a stacked domain on top of the
  standard GIC.

- OMAP, imx6 and exynos are also converted to stacked domains, but
  their implementation is left in place (the code is far too
  intricately mixed with other details of the platform for me to even
  try to move it). Some OMAP variants get a special treatment as we
  also kill the crossbar horror (more on that below).

- shmobile, ux500 and zynq are only slightly modified.

- The GIC itself is cleaned up, and some other bits and bobs are
  adjusted for a good measure.

About the TI crossbar:

- The allocation of interrupts in this domain is fairly similar to
  what we do for MSI (see the GICv2m driver), and stacked domains have
  proved to be a fitting solution.

- The current description in DT is currently entierely inaccurate, and
  as we're already breaking it for the WUGEN block, we might as well
  do it again for the crossbar.

- The way crossbar, WUGEN and GIC interract is quite complex (this is
  effectively a stack of three interrupt controllers with interesting
  exceptions and braindead routing), and stacked domains are the right
  abstraction for that.

- Other platforms (Freescale Vybrid) are starting to come up with the
  same type of things, and it'd be good to avoid them following the
  same broken model.

- It removes a few lines from the code base so it can't completely be
  a bad idea!

So this patch series does exactly that: make the crossbar a stacked
interrupt controller that only takes care of setting up the routing,
fix the DTs to represent the actual HW, and remove a bit of the
craziness from the GIC code.

It is worth realizing that:

- I haven't been able to test this as much as I would have wanted to
  (it's only been tested on tegra2, omap4 and omap5).

- I've created DT bindings when needed, updated existing ones, but I
  haven't created a binding for platforms that already used an
  undocumented one (imx6, I'm looking at you).

- I've relaxed quite a bit of the locking in the GIC code. I believe
  this is safe, but someone else should give it a long hard look.

- This actively *breaks* existing setups. Once you boot a new kernel
  with an old DT, suspend/resume *will* be broken. Old kernels on a
  new DT won't even boot! You've been warned. This really outline the
  necessity of actually describing the HW in device trees...

As for the patches, they are on top of 3.19-rc3 + the patch posted
here [4].

I've pushed the code to:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git 
irq/die-gic-arch-extn-die-die-die

I'm still targetting 3.20 for this, but obviously things are getting
quite tight. I'd very much like to hear from the maintainers about
their views concerning this series.

Thanks,

 M.

* From v4 [3]:
- Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4]
- Fixed more iMX6 DTs (Stephan)
- Fixed Exynos4/5 DTs

* From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan

* From v1 [1]:
- Rebased on 3.19-rc3
- Fixed a number of additional platforms
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth

[4]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317286.html
[3]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html
[2]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html
[1]: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html

Marc Zyngier (21):
  ARM: tegra: irq: nuke leftovers from non-DT support
  irqchip: tegra: add DT-based support for legacy interrupt controller
  ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
  ARM: tegra: update DTs to expose legacy interrupt controller
  DT: tegra: add binding for the legacy interrupt controller
  ARM: tegra: remove old LIC support
  genirq: Add irqchip_set_wake_parent
  irqchip: crossbar: convert dra7 crossbar to stacked domains
  DT: update ti,irq-crossbar binding
  irqchip: GIC: get rid of routable domain
  DT: arm,gic: kill arm,routable-irqs
  DT: omap4/5: add binding for the wake-up generator
  ARM: omap: convert wakeupgen to stacked domains
  ARM: imx6: convert GPC to stacked domains
  ARM: exynos4/5: convert pmu wakeup to stacked domains
  DT: exynos: update PMU binding
  irqchip: gic: add an entry point to set up irqchip flags
  ARM: shmobile: remove use

[PATCH v4 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts |   3 +-
 arch/arm/boot/dts/dra7-evm.dts  |   2 +-
 arch/arm/boot/dts/dra7.dtsi |  35 +++---
 arch/arm/boot/dts/dra72-evm.dts |   1 -
 arch/arm/boot/dts/dra72x.dtsi   |   3 +-
 arch/arm/boot/dts/dra74x.dtsi   |   5 +-
 arch/arm/mach-omap2/omap4-common.c  |   4 -
 drivers/irqchip/irq-crossbar.c  | 207 ++--
 include/linux/irqchip/irq-crossbar.h|  11 --
 9 files changed, 146 insertions(+), 125 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts 
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..c2241c2 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
-   interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW;  /* IRQ_SYS_1N */
 
pinctrl-names = default;
@@ -358,7 +357,7 @@
 
 uart3 {
status = okay;
-   interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x248;
 
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
-   interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x3e0;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..6f90673 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
 #include skeleton.dtsi
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
#address-cells = 1;
#size-cells = 1;
 
compatible = ti,dra7xx;
-   interrupt-parent = gic;
+   interrupt-parent = crossbar_mpu;
 
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
 GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
-   arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
  0x48212000 0x1000,
  0x48214000 0x2000,
  0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
  0x4500 0x1000;
-   interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 4 
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
 
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
-   interrupts-extended = gic GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
-   interrupts-extended = gic GIC_SPI 68 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH

[PATCH v4 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller

[Marc Zyngier]

Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.

The stacked IRQ domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/Makefile|   1 +
 drivers/irqchip/irq-tegra.c | 368 
 2 files changed, 369 insertions(+)
 create mode 100644 drivers/irqchip/irq-tegra.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
 obj-$(CONFIG_DW_APB_ICTL)  += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..e1ac65e
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,368 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR  0x14
+#define ICTLR_CPU_IEP_FIR_SET  0x18
+#define ICTLR_CPU_IEP_FIR_CLR  0x1c
+
+#define ICTLR_CPU_IER  0x20
+#define ICTLR_CPU_IER_SET  0x24
+#define ICTLR_CPU_IER_CLR  0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER  0x30
+#define ICTLR_COP_IER_SET  0x34
+#define ICTLR_COP_IER_CLR  0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS   5
+
+static unsigned int num_ictlrs;
+
+struct tegra_ictlr_soc {
+   unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+   .num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+   .num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+   { .compatible = nvidia,tegra30-ictlr, .data = tegra30_ictlr_soc },
+   { .compatible = nvidia,tegra20-ictlr, .data = tegra20_ictlr_soc },
+   { }
+};
+
+struct tegra_ictlr_info {
+   void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+   u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+   u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *lic;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long 
reg)
+{
+   void __iomem *base = d-chip_data;
+   u32 mask;
+
+   mask = BIT(d-hwirq % 32);
+   writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+   irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+   irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+   irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+   return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+   u32 irq = d-hwirq;
+   u32 index, mask;
+
+   index = (irq / 32);
+   mask = BIT(irq % 32);
+   if (enable)
+   lic-ictlr_wake_mask[index] |= mask;
+   else
+   lic-ictlr_wake_mask[index] = ~mask

[PATCH v4 07/21] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 include/linux/irq.h |  1 +
 kernel/irq/chip.c   | 16 
 2 files changed, 17 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 /* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data:  Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this 
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+   data = data-parent_data;
+   if (data-chip-irq_set_wake)
+   return data-chip-irq_set_wake(data, on);
+
+   return -ENOSYS;
+}
 #endif
 
 /**
-- 
2.1.4

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[PATCH v4 01/21] ARM: tegra: irq: nuke leftovers from non-DT support

[Marc Zyngier]

The GIC is now always initialized from DT on tegra, and there is
no point in keeping non-DT init code.

Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/irq.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index ab95f53..7f87a50 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -283,13 +283,5 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
-   /*
-* Check if there is a devicetree present, since the GIC will be
-* initialized elsewhere under DT.
-*/
-   if (!of_have_populated_dt())
-   gic_init(0, 29, distbase,
-   IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
tegra114_gic_cpu_pm_registration();
 }
-- 
2.1.4

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[PATCH v4 04/21] ARM: tegra: update DTs to expose legacy interrupt controller

[Marc Zyngier]

Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/tegra114.dtsi | 16 +++-
 arch/arm/boot/dts/tegra124.dtsi | 16 +++-
 arch/arm/boot/dts/tegra20.dtsi  | 15 ++-
 arch/arm/boot/dts/tegra30.dtsi  | 16 +++-
 4 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f58a3d9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
 
 / {
compatible = nvidia,tegra114;
-   interrupt-parent = gic;
+   interrupt-parent = lic;
 
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
  0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
+   };
+
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra114-ictlr, nvidia,tegra30-ictlr;
+   reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50,
+ 0x60004400 0x50;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};
 
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..db85695 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
 
 / {
compatible = nvidia,tegra124;
-   interrupt-parent = gic;
+   interrupt-parent = lic;
#address-cells = 2;
#size-cells = 2;
 
@@ -173,6 +173,7 @@
  0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
 
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra124-ictlr, nvidia,tegra30-ictlr;
+   reg = 0x0 0x60004000 0x0 0x100,
+ 0x0 0x60004100 0x0 0x100,
+ 0x0 0x60004200 0x0 0x100,
+ 0x0 0x60004300 0x0 0x100,
+ 0x0 0x60004400 0x0 0x100;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
+   };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..362bb21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
 
 / {
compatible = nvidia,tegra20;
-   interrupt-parent = intc;
+   interrupt-parent = lic;
 
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
 
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+   interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
   0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+   interrupt-parent = intc;
};
 
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
 
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra20-ictlr;
+   reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = intc;
+   };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..6bea674 100644

[PATCH v4 06/21] ARM: tegra: remove old LIC support

[Marc Zyngier]

Now that all DTs have been updated, entierely drop support for
the non-DT code.

This is likely to break platforms that do not update their DT,
so print a warning at boot time.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/iomap.h |  15 
 arch/arm/mach-tegra/irq.c   | 201 +---
 arch/arm/mach-tegra/irq.h   |   6 --
 3 files changed, 2 insertions(+), 220 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
 #define TEGRA_ARM_INT_DIST_BASE0x50041000
 #define TEGRA_ARM_INT_DIST_SIZESZ_4K
 
-#define TEGRA_PRIMARY_ICTLR_BASE   0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE   SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE  0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE  SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE   0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE   SZ_64
-
 #define TEGRA_TMR1_BASE0x60005000
 #define TEGRA_TMR1_SIZESZ_8
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1593c4c..3b9098d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
 #include board.h
 #include iomap.h
 
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR  0x14
-#define ICTLR_CPU_IEP_FIR_SET  0x18
-#define ICTLR_CPU_IEP_FIR_CLR  0x1c
-
-#define ICTLR_CPU_IER  0x20
-#define ICTLR_CPU_IER_SET  0x24
-#define ICTLR_CPU_IER_CLR  0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER  0x30
-#define ICTLR_COP_IER_SET  0x34
-#define ICTLR_COP_IER_CLR  0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS   5
-
 #define SGI_MASK 0x
 
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
-   IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
 #ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
 static void __iomem *tegra_gic_cpu_base;
 #endif
 
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
 }
 
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
-   void __iomem *base;
-   u32 mask;
-
-   BUG_ON(irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
-   base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
-   __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return 0;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
-   return 1;
-}
-
 #ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
-   u32 irq = d-hwirq;
-   u32 index, mask;
-
-   if (irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
-   return -EINVAL;
-
-   index = ((irq - FIRST_LEGACY_IRQ) / 32);
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-   if (enable)
-   ictlr_wake_mask[index] |= mask;
-   else
-   ictlr_wake_mask[index] = ~mask;
-
-   return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
-   unsigned long flags;
-   int i;
-
-   local_irq_save(flags);
-   for (i = 0; i  num_ictlrs; i++) {
-   void __iomem *ictlr = ictlr_reg_base[i];
-   /* Save interrupt state */
-   cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
-   cpu_iep[i

[PATCH v4 05/21] DT: tegra: add binding for the legacy interrupt controller

[Marc Zyngier]

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/nvidia,tegra-ictlr.txt| 43 ++
 1 file changed, 43 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt 
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..1099fe0
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+
+Required properties:
+
+- compatible : should be: nvidia,tegrachip-ictlr. The LIC on
+  subsequent SoCs remained backwards-compatible with Tegra30, so on
+  Tegra generations later than Tegra30 the compatible value should
+  include nvidia,tegra30-ictlr.  
+- reg : Specifies base physical address and size of the registers.
+  Each controller must be described separately (Tegra20 has 4 of them,
+  whereas Tegra30 and later have 5  
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+  are explicitly forbidden.
+
+Example:
+
+   ictlr: interrupt-controller@60004000 {
+   compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+   reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = intc;
+   };
-- 
2.1.4

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[PATCH v4 09/21] DT: update ti,irq-crossbar binding

[Marc Zyngier]

Make it look like a real interrupt controller.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../devicetree/bindings/arm/omap/crossbar.txt  | 18 +-
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt 
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be ti,irq-crossbar
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt 
controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be 
routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-   crossbar_mpu: @4a02 {
+   crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
-   ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+   ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further 
details.
 
 An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as 
a
-quirky hardware mapping direct to GIC.
 
 Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
-   device_y@0x4a033000 {
-   /* Direct mapped GIC SPI 1 used */
-   interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
-   ...
-   };
-- 
2.1.4

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[PATCH v4 16/21] DT: exynos: update PMU binding

[Marc Zyngier]

Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt 
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
  - clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
 
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+  this PMU signals interrupts to.
+
 Example :
 pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+   interrupt-controller;
+   interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
-- 
2.1.4

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[PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.

Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/imx6qdl.dtsi  |   7 ++-
 arch/arm/boot/dts/imx6sl.dtsi   |   6 +-
 arch/arm/boot/dts/imx6sx.dtsi   |   6 +-
 arch/arm/mach-imx/common.h  |   1 -
 arch/arm/mach-imx/gpc.c | 127 
 arch/arm/mach-imx/mach-imx6q.c  |   1 -
 arch/arm/mach-imx/mach-imx6sl.c |   1 -
 arch/arm/mach-imx/mach-imx6sx.c |   1 -
 8 files changed, 119 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..aff9ded 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+   interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
 
@@ -694,8 +696,11 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
 0 90 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..0d0962b 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
ocram: sram@0090 {
@@ -603,7 +604,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..dabaf89 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
pmu {
@@ -700,7 +701,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
interrupts = GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
iomuxc: iomuxc@020e {
diff --git

[PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains

[Marc Zyngier]

Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.

Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/exynos4.dtsi|   4 ++
 arch/arm/boot/dts/exynos5250.dtsi |   4 ++
 arch/arm/boot/dts/exynos5420.dtsi |   4 ++
 arch/arm/mach-exynos/exynos.c |  14 ++---
 arch/arm/mach-exynos/suspend.c| 122 ++
 5 files changed, 129 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};
 
dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+   interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};
 
sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};
 
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};
 
@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};
 
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
 }
 
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
 static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
-   { .compatible = samsung,exynos4210-pmu },
-   { .compatible = samsung,exynos4212-pmu },
-   { .compatible = samsung,exynos4412-pmu },
-   { .compatible = samsung,exynos4415-pmu },
-   { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
-   { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
 };
 
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
-   if (!pmu_base_addr)
-   panic(failed to find exynos pmu register\n);
 }
 
 static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..b325ecd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
 #include linux/syscore_ops.h
 #include linux/cpu_pm.h
 #include linux/io.h

[PATCH v4 11/21] DT: arm,gic: kill arm,routable-irqs

[Marc Zyngier]

Nobody will regret it.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/gic.txt | 6 --
 1 file changed, 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt 
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
 Example:
 
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
-   arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
  0xfff10100 0x100;
};
-- 
2.1.4

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[PATCH v4 10/21] irqchip: GIC: get rid of routable domain

[Marc Zyngier]

The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 59 -
 include/linux/irqchip/arm-gic.h |  6 -
 2 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d, 
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-   gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-   gic_routable_irq_domain_ops-unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
 
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-   if (!intspec[0]) {
-   ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
-   if (IS_ERR_VALUE(ret))
-   return ret;
-   }
+   if (!intspec[0])
+   *out_hwirq += 16;
 
*out_type = intspec[2]  IRQ_TYPE_SENSE_MASK;
 
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
-   return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-   struct device_node *controller,
-   const u32 *intspec, unsigned int intsize,
-   unsigned long *out_hwirq,
-   unsigned int *out_type)
-{
-   *out_hwirq += 16;
-   return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-   .map = gic_routable_irq_domain_map,
-   .unmap = gic_routable_irq_domain_unmap,
-   .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-   gic_default_routable_irq_domain_ops;
-
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
-   int nr_routable_irqs;
 
BUG_ON(gic_nr = MAX_GIC_NR);
 
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
gic-gic_irqs = gic_irqs;
 
if (node) { /* DT case */
-   const struct irq_domain_ops *ops = 
gic_irq_domain_hierarchy_ops;
-
-   if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
-   ops = gic_irq_domain_ops;
-   gic_irqs = nr_routable_irqs;
-   }
-
-   gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+   gic-domain = irq_domain_add_linear(node, gic_irqs,
+   
gic_irq_domain_hierarchy_ops,
+   gic);
} else {/* Non-DT case */
/*
 * For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-   (const struct irq_domain_ops *ops)
-{
-   gic_routable_irq_domain_ops = ops

[PATCH v4 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node

[Marc Zyngier]

If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.

This is only a temporary measure until that code is removed for good.

Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/irq.c   | 12 
 arch/arm/mach-tegra/tegra.c |  1 -
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..1593c4c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,22 @@ static void tegra114_gic_cpu_pm_registration(void)
 static void tegra114_gic_cpu_pm_registration(void) { }
 #endif
 
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+   { .compatible = nvidia,tegra20-ictlr },
+   { .compatible = nvidia,tegra30-ictlr },
+   { }
+};
+
 void __init tegra_init_irq(void)
 {
int i;
void __iomem *distbase;
 
+   if (of_find_matching_node(NULL, tegra_ictlr_match))
+   goto skip_extn_setup;
+
+   tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR)  0x1f;
 
@@ -283,5 +294,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
 }
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
 {
tegra_init_irq();
irqchip_init();
-   tegra_legacy_irq_syscore_init();
 }
 
 static void __init tegra_dt_init(void)
-- 
2.1.4

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[PATCH v4 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.

On a platform with this patch applied, the system looks like
this:

root@bacon-fat:~# cat /proc/interrupts
CPU0   CPU1
 16:  0  0 WUGEN  37  gp_timer
 19: 233799 155916   GIC  27  arch_timer
 23:  0  0 WUGEN   9  l3-dbg-irq
 24:  1  0 WUGEN  10  l3-app-irq
 27:282  0 WUGEN  13  omap-dma-engine
 44:  0  0  4ae1.gpio  13  DMA
294:  0  0 WUGEN  20  gpmc
297:506  0 WUGEN  56  4807.i2c
298:  0  0 WUGEN  57  48072000.i2c
299:  0  0 WUGEN  61  4806.i2c
300:  0  0 WUGEN  62  4807a000.i2c
301:  8  0 WUGEN  60  4807c000.i2c
308:   2439  0 WUGEN  74  OMAP UART2
312:362  0 WUGEN  83  mmc2
313:502  0 WUGEN  86  mmc0
314: 13  0 WUGEN  94  mmc1
350:  0  0  PRCM  pinctrl, pinctrl
406:   35155709  0   GIC 109  ehci_hcd:usb1
407:  0  0 WUGEN   7  palmas
409:  0  0 WUGEN 119  twl6040
410:  0  0   twl6040   5  twl6040_irq_ready
411:  0  0   twl6040   0  twl6040_irq_th
IPI0:  0  1  CPU wakeup interrupts
IPI1:  0  0  Timer broadcast interrupts
IPI2:  95334 902334  Rescheduling interrupts
IPI3:  0  0  Function call interrupts
IPI4:479648  Single function call interrupts
IPI5:  0  0  CPU stop interrupts
IPI6:  0  0  IRQ work interrupts
IPI7:  0  0  completion interrupts
Err:  0

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am4372.dtsi |  11 ++-
 arch/arm/boot/dts/am437x-gp-evm.dts   |   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts   |   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts  |   1 -
 arch/arm/boot/dts/dra7.dtsi   |  12 ++-
 arch/arm/boot/dts/dra72x.dtsi |   2 +-
 arch/arm/boot/dts/dra74x.dtsi |   2 +-
 arch/arm/boot/dts/omap4-duovero.dtsi  |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts   |   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi |   2 -
 arch/arm/boot/dts/omap4.dtsi  |  18 -
 arch/arm/boot/dts/omap5-cm-t54.dts|   1 -
 arch/arm/boot/dts/omap5-uevm.dts  |   2 -
 arch/arm/boot/dts/omap5.dtsi  |  26 ---
 arch/arm/mach-omap2/omap-wakeupgen.c  | 125 +++---
 arch/arm/mach-omap2/omap-wakeupgen.h  |   1 -
 arch/arm/mach-omap2/omap4-common.c|  17 ++--
 18 files changed, 162 insertions(+), 78 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 
 / {
compatible = ti,am4372, ti,am43;
-   interrupt-parent = gic;
+   interrupt-parent = wakeupgen;
 
 
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
  0x48240100 0x0100;
+   interrupt-parent = gic;
+   };
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
};
 
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts 
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4c..69f2313 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts 
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc9..029bade 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
-   interrupt-parent = gic;
interrupts = GIC_SPI 7

[PATCH v4 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags

[Marc Zyngier]

Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-zynq/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
 
 static void __init zynq_irq_init(void)
 {
-   gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
 }
 
-- 
2.1.4

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[PATCH v4 12/21] DT: omap4/5: add binding for the wake-up generator

[Marc Zyngier]

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+  ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+
+Example:
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
+   };
-- 
2.1.4

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[PATCH v4 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake

[Marc Zyngier]

shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.

It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function.

Acked-by: Simon Horman horms+rene...@verge.net.au
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-shmobile/intc-sh73a0.c   | 7 +--
 arch/arm/mach-shmobile/setup-r8a7779.c | 7 +--
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c 
b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9e36180..fd63ae6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,11 +252,6 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void 
*dev_id)
return IRQ_HANDLED;
 }
 
-static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
-{
-   return 0; /* always allow wakeup */
-}
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -318,8 +313,8 @@ void __init sh73a0_init_irq(void)
void __iomem *gic_cpu_base = IOMEM(0xf100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
-   gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
register_intc_controller(intcs_desc);
register_intc_controller(intc_pint0_desc);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c 
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d17..989de2d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -713,14 +713,9 @@ void __init r8a7779_init_late(void)
 }
 
 #ifdef CONFIG_USE_OF
-static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
-{
-   return 0; /* always allow wakeup */
-}
-
 void __init r8a7779_init_irq_dt(void)
 {
-   gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
 
irqchip_init();
 
-- 
2.1.4

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[PATCH v4 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags

[Marc Zyngier]

Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.

Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-ux500/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
 */
 void __init ux500_init_irq(void)
 {
-   gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
 
/*
-- 
2.1.4

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[PATCH v4 21/21] irqchip: gic: Drop support for gic_arch_extn

[Marc Zyngier]

Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 54 -
 include/linux/irqchip/arm-gic.h |  2 --
 2 files changed, 56 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 #define NR_GIC_CPU_IF 8
 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
-   .irq_eoi= NULL,
-   .irq_mask   = NULL,
-   .irq_unmask = NULL,
-   .irq_retrigger  = NULL,
-   .irq_set_type   = NULL,
-   .irq_set_wake   = NULL,
-};
-
 #ifndef MAX_GIC_NR
 #define MAX_GIC_NR 1
 #endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
 {
u32 mask = 1  (gic_irq(d) % 32);
 
-   raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + 
(gic_irq(d) / 32) * 4);
-   if (gic_arch_extn.irq_mask)
-   gic_arch_extn.irq_mask(d);
-   raw_spin_unlock(irq_controller_lock);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
u32 mask = 1  (gic_irq(d) % 32);
 
-   raw_spin_lock(irq_controller_lock);
-   if (gic_arch_extn.irq_unmask)
-   gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + 
(gic_irq(d) / 32) * 4);
-   raw_spin_unlock(irq_controller_lock);
 }
 
 static void gic_eoi_irq(struct irq_data *d)
 {
-   if (gic_arch_extn.irq_eoi) {
-   raw_spin_lock(irq_controller_lock);
-   gic_arch_extn.irq_eoi(d);
-   raw_spin_unlock(irq_controller_lock);
-   }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 }
 
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int 
type)
if (type != IRQ_TYPE_LEVEL_HIGH  type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
 
-   raw_spin_lock(irq_controller_lock);
-
-   if (gic_arch_extn.irq_set_type)
-   gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
 
-   raw_spin_unlock(irq_controller_lock);
-
return 0;
 }
 
 static int gic_retrigger(struct irq_data *d)
 {
-   if (gic_arch_extn.irq_retrigger)
-   return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
 }
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const 
struct cpumask *mask_val,
 }
 #endif
 
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
-   int ret = -ENXIO;
-
-   if (gic_arch_extn.irq_set_wake)
-   ret = gic_arch_extn.irq_set_wake(d, on);
-
-   return ret;
-}
-
-#else
-#define gic_set_wake   NULL
-#endif
-
 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 {
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
 #ifdef CONFIG_SMP
.irq_set_affinity   = gic_set_affinity,
 #endif
-   .irq_set_wake   = gic_set_wake,
 };
 
 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
set_handle_irq(gic_handle_irq);
}
 
-   gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
 
 struct device_node;
 
-extern struct irq_chip gic_arch_extn;
-
 void gic_set_irqchip_flags(unsigned long flags);
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
-- 
2.1.4

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[PATCH v4 17/21] irqchip: gic: add an entry point to set up irqchip flags

[Marc Zyngier]

A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.

Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 5 +
 include/linux/irqchip/arm-gic.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
+void gic_set_irqchip_flags(unsigned long flags)
+{
+   gic_chip.flags |= flags;
+}
+
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
 
 extern struct irq_chip gic_arch_extn;
 
+void gic_set_irqchip_flags(unsigned long flags);
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
-- 
2.1.4

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Re: [PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 19/01/15 10:47, Lucas Stach wrote:
 Am Montag, den 19.01.2015, 09:44 + schrieb Marc Zyngier:
 IMX6 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the GPC block is actually the first
 interrupt controller in the chain, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs won't even boot.

 Tested-by: Stefan Agner ste...@agner.ch
 Acked-by: Stefan Agner ste...@agner.ch
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 ---
  arch/arm/boot/dts/imx6qdl.dtsi  |   7 ++-
  arch/arm/boot/dts/imx6sl.dtsi   |   6 +-
  arch/arm/boot/dts/imx6sx.dtsi   |   6 +-
  arch/arm/mach-imx/common.h  |   1 -
  arch/arm/mach-imx/gpc.c | 127 
 
  arch/arm/mach-imx/mach-imx6q.c  |   1 -
  arch/arm/mach-imx/mach-imx6sl.c |   1 -
  arch/arm/mach-imx/mach-imx6sx.c |   1 -
  8 files changed, 119 insertions(+), 31 deletions(-)

 [...]
 
 --- a/arch/arm/mach-imx/common.h
 +++ b/arch/arm/mach-imx/common.h
 @@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
  static inline void imx_smp_prepare(void) {}
  #endif
  void imx_src_init(void);
 -void imx_gpc_init(void);
  void imx_gpc_pre_suspend(bool arm_power_off);
  void imx_gpc_post_resume(void);
  void imx_gpc_mask_all(void);
 diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
 index 5f3602e..838da3c 100644
 --- a/arch/arm/mach-imx/gpc.c
 +++ b/arch/arm/mach-imx/gpc.c
 @@ -22,6 +22,7 @@
  #define GPC_PGC_CPU_PDN 0x2a0
  
  #define IMR_NUM 4
 +#define GPC_MAX_IRQS(IMR_NUM * 32)
  
  static void __iomem *gpc_base;
  static u32 gpc_wake_irqs[IMR_NUM];
 @@ -56,17 +57,17 @@ void imx_gpc_post_resume(void)
  
  static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
  {
 -unsigned int idx = d-hwirq / 32 - 1;
 +unsigned int idx = d-hwirq / 32;
  u32 mask;
  
 -/* Sanity check for SPI irq */
 -if (d-hwirq  32)
 -return -EINVAL;
 -
  mask = 1  d-hwirq % 32;
  gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx]  ~mask;
  
 +/*
 + * Do *not* call into the parent, as the GIC doesn't have any
 + * wake-up facility...
 + */
  return 0;
  }
  
 @@ -96,7 +97,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
  void __iomem *reg;
  u32 val;
  
 -reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
 +reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
  val = readl_relaxed(reg);
  val = ~(1  hwirq % 32);
  writel_relaxed(val, reg);
 @@ -107,7 +108,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
  void __iomem *reg;
  u32 val;
  
 -reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
 +reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
  val = readl_relaxed(reg);
  val |= 1  (hwirq % 32);
  writel_relaxed(val, reg);
 @@ -115,37 +116,115 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
  
  static void imx_gpc_irq_unmask(struct irq_data *d)
  {
 -/* Sanity check for SPI irq */
 -if (d-hwirq  32)
 -return;
 -
  imx_gpc_hwirq_unmask(d-hwirq);
 +irq_chip_unmask_parent(d);
  }
  
  static void imx_gpc_irq_mask(struct irq_data *d)
  {
 -/* Sanity check for SPI irq */
 -if (d-hwirq  32)
 -return;
 -
  imx_gpc_hwirq_mask(d-hwirq);
 +irq_chip_mask_parent(d);
 +}
 +
 +static struct irq_chip imx_gpc_chip = {
 +.name   = GPC,
 +.irq_eoi= irq_chip_eoi_parent,
 +.irq_mask   = imx_gpc_irq_mask,
 +.irq_unmask = imx_gpc_irq_unmask,
 +.irq_retrigger  = irq_chip_retrigger_hierarchy,
 +.irq_set_wake   = imx_gpc_irq_set_wake,
 +};
 +
 +static int imx_gpc_domain_xlate(struct irq_domain *domain,
 +struct device_node *controller,
 +const u32 *intspec,
 +unsigned int intsize,
 +unsigned long *out_hwirq,
 +unsigned int *out_type)
 +{
 +if (domain-of_node != controller)
 +return -EINVAL; /* Shouldn't happen, really... */
 +if (intsize != 3)
 +return -EINVAL; /* Not GIC compliant */
 +if (intspec[0] != 0)
 +return -EINVAL; /* No PPI should point to this domain */
 +
 +*out_hwirq = intspec[1];
 +*out_type = intspec[2];
 +return 0;
 +}
 +
 +static int imx_gpc_domain_alloc(struct irq_domain *domain,
 +  unsigned int irq,
 +  unsigned int nr_irqs, void *data)
 +{
 +struct of_phandle_args *args = data;
 +struct of_phandle_args parent_args

[PATCH v2] ARM: OMAP: Work around hardcoded interrupts

[Marc Zyngier]

Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.

Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.

This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.

It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.

Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
From v1:
- OMAP4 can either get the PRM interrupt from hwmod or from device tree.
  In the latter case, remove the xlate_irq method.

 arch/arm/mach-omap2/common.h   |  1 +
 arch/arm/mach-omap2/omap4-common.c | 32 ++
 arch/arm/mach-omap2/omap_hwmod.c   | 10 --
 arch/arm/mach-omap2/omap_hwmod.h   |  1 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  5 +
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c |  1 +
 arch/arm/mach-omap2/prcm-common.h  |  1 +
 arch/arm/mach-omap2/prm44xx.c  |  5 -
 arch/arm/mach-omap2/prm_common.c   | 14 +++--
 arch/arm/mach-omap2/twl-common.c   |  5 -
 10 files changed, 69 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea8..b664494 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 
+unsigned int omap4_xlate_irq(unsigned int hwirq);
 void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap4-common.c 
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44a..cc30e49 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id gic_match[] = {
+   { .compatible = arm,cortex-a9-gic, },
+   { .compatible = arm,cortex-a15-gic, },
+   { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+   struct of_phandle_args irq_data;
+   unsigned int irq;
+
+   if (!gic_node)
+   gic_node = of_find_matching_node(NULL, gic_match);
+
+   if (WARN_ON(!gic_node))
+   return hwirq;
+
+   irq_data.np = gic_node;
+   irq_data.args_count = 3;
+   irq_data.args[0] = 0;
+   irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+   irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+   irq = irq_create_of_mapping(irq_data);
+   if (WARN_ON(!irq))
+   irq = hwirq;
+
+   return irq;
+}
+
 void __init omap_gic_of_init(void)
 {
struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908d..9025fff 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, 
struct resource *res)
 
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i  mpu_irqs_cnt; i++) {
+   unsigned int irq;
+
+   if (oh-xlate_irq)
+   irq = oh-xlate_irq((oh-mpu_irqs + i)-irq);
+   else
+   irq = (oh-mpu_irqs + i)-irq;
(res + r)-name = (oh-mpu_irqs + i)-name;
-   (res + r)-start = (oh-mpu_irqs + i)-irq;
-   (res + r)-end = (oh-mpu_irqs + i)-irq;
+   (res + r)-start = irq;
+   (res + r)-end = irq;
(res + r)-flags = IORESOURCE_IRQ;
r++;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 35ca6ef..5b42faf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@ struct omap_hwmod {
spinlock_t  _lock;
struct list_headnode;
struct omap_hwmod_ocp_if*_mpu_port;
+   unsigned int(*xlate_irq)(unsigned int);
u16 flags;
u8  mpu_rt_idx;
u8  response_lat;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c314b3c..f5e68a7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -479,6 +479,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.class

Re: Regression with legacy IRQ numbers caused by 9a1091ef0017

[Marc Zyngier]

On 16/01/15 16:56, Arnd Bergmann wrote:
 On Thursday 15 January 2015 07:37:48 Tony Lindgren wrote:
 * Marc Zyngier marc.zyng...@arm.com [150115 06:46]:
 On Thu, Jan 15 2015 at  2:27:56 pm GMT, Arnd Bergmann a...@arndb.de wrote:
 On Thursday 15 January 2015 13:42:57 Marc Zyngier wrote:
 Probably there is a workable strategy, but my knowledge about OMAP is
 close to *nothing*...

 I have a feeling this might bite other platforms too and we just have
 not noticed it yet..
 
 I'm looking through the entire tree now, scanning for machines that have
 GIC and use IORESOURCE_IRQ or DEFINE_RES_IRQ in their platform code.
 Most platforms using GIC are completely converted to DT and have no
 hardcoded legacy IRQs.
 
 I have checked that cns3xxx and realview are both fine by inspection.
 
 The only one I'm not sure about is shmobile, which looks like it might
 suffer from the same problem. Simon/Magnus, could you verify this
 with a multiplatform kernel on any SoC that has GIC and uses devices
 that have interrupts defined in setup-*.c or board-*.c?

There are 3 patches floating around for shmobile, converting their
non-DT support to directly initializing the GIC instead of relying on
irqchip_init(). That's assuming their DT implementation doesn't use any
of these device declarations.

If they do, we could use a hack similar to the one I implemented for
OMAP, populating the virtual IRQ in the resource at boot time, just
after the irqchip initialization.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...
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Re: [v3,15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains

[Marc Zyngier]

Hi Pankaj,

On 15/01/15 06:41, Pankaj Dubey wrote:
 +CC: Thomas Abraham thomas...@samsung.com
 
 Hi Mark,
 
 On Monday 12 January 2015 11:56 PM, Marc Zyngier wrote:
 Exynos has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the PMU block is actually the first
 interrupt controller in the chain for RTC, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs may not even boot.

 Also, I stronly suspect that there is more than two wake-up
 interrupts on these platforms, but I leave it to the maintainers
 to fix their mess.

 Signed-off-by: Marc Zyngier marc.zyng...@arm.com

 
 I tested this series on Exynos5250, using kgene/for-next and 
 linux-next/next-20150114, but S2R failed on Exynos5250 based SMDK board.
 
 Following is the log I got on SMDK5250 board, (note I have added some 
 debugging log to know what is happening)
 
 I can see is S3C-RTC's enable_irq_wake is failing with error -6.
 I also observed that even though we are adding pmu_domain_ops using 
 irq_domain_add_hierarchy, but none of pmu_domain_ops are getting called.
 
 Please let me know if I am missing anything or do I need to modify 
 anything to test S2R on Exynos SoC.

Thanks for giving it a go. One think I noticed is that I forgot to add a
#interrupt-cells = 3; to the pmu_system_controller node.

Also, it would be interesting to know what is the hwirq associated with
the irq_desc you've printed below.

Thanks,

M.

 -
 echo +10  /sys/class/rtc/rtc1/wakealarm; sleep 1; echo mem  /sys/power/sta
 te
 [  257.428163] PM: Syncing filesystems ... done.
 [  257.431786] Freezing user space processes ... (elapsed 0.003 seconds) 
 done.
 [  257.439680] Freezing remaining freezable tasks ... (elapsed 0.001 
 seconds) done.
 [  257.544451] wake enabled for irq 116
 [  257.546916] CPU: 0 PID: 1311 Comm: ash Not tainted 
 3.19.0-rc4-next-20150114-00023-g492ff37 #15
 [  257.555141] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
 [  257.561231] [c0014430] (unwind_backtrace) from [c0011594] 
 (show_stack+0x10/0x14)
 [  257.568948] [c0011594] (show_stack) from [c0418b00] 
 (dump_stack+0x84/0xc4)
 [  257.576151] [c0418b00] (dump_stack) from [c005ce30] 
 (set_irq_wake_real+0x58/0x8c)
 [  257.583961] [c005ce30] (set_irq_wake_real) from [c005cef0] 
 (irq_set_irq_wake+0x8c/0xf0)
 [  257.592295] [c005cef0] (irq_set_irq_wake) from [c02e9d94] 
 (s3c_rtc_suspend+0xb8/0xdc)
 [  257.600456] [c02e9d94] (s3c_rtc_suspend) from [c0298c80] 
 (dpm_run_callback.isra.13+0x1c/0x60)
 [  257.609308] [c0298c80] (dpm_run_callback.isra.13) from [c02996a0] 
 (__device_suspend+0x128/0x2d0)
 [  257.618422] [c02996a0] (__device_suspend) from [c029a850] 
 (dpm_suspend+0x64/0x22c)
 [  257.626320] [c029a850] (dpm_suspend) from [c0058488] 
 (suspend_devices_and_enter+0x88/0x3dc)
 [  257.634999] [c0058488] (suspend_devices_and_enter) from 
 [c00589c8] (pm_suspend+0x1ec/0x24c)
 [  257.643680] [c00589c8] (pm_suspend) from [c00576e0] 
 (state_store+0x68/0xb8)
 [  257.650972] [c00576e0] (state_store) from [c012835c] 
 (kernfs_fop_write+0xb8/0x19c)
 [  257.658870] [c012835c] (kernfs_fop_write) from [c00cf620] 
 (vfs_write+0xa0/0x1ac)
 [  257.666595] [c00cf620] (vfs_write) from [c00cfc78] 
 (SyS_write+0x44/0x9c)
 [  257.673625] [c00cfc78] (SyS_write) from [c000e6e0] 
 (ret_fast_syscall+0x0/0x30)
 [  257.681176] genirq: PKD: irq_desc-name: (null): irq: 60
 [  257.686469] genirq: PKD: set_irq_wake_real: ret: -6
 [  257.691349] s3c-rtc 101e.rtc: enable_irq_wake failed: -6
 [  257.708926] PM: suspend of devices complete after 260.482 msecs
 [  257.713362] BUCK9: No configuration
 [  257.716840] BUCK8: No configuration
 [  257.720309] BUCK7: No configuration
 [  257.723776] BUCK6: No configuration
 [  257.727254] P1.8V_BUCK_OUT5: No configuration
 [  257.731597] LDO26: No configuration
 [  257.735066] LDO25: No configuration
 [  257.738532] LDO24: No configuration
 [  257.742009] LDO23: No configuration
 [  257.745481] LDO22: No configuration
 [  257.748954] LDO21: No configuration
 [  257.752419] LDO20: No configuration
 [  257.755897] LDO19: No configuration
 [  257.759370] LDO18: No configuration
 [  257.762835] LDO17: No configuration
 [  257.766314] P1.8V_LDO_OUT16: No configuration
 [  257.770653] P1.0V_LDO_OUT15: No configuration
 [  257.774994] P1.8V_LDO_OUT14: No configuration
 [  257.779334] P1.8V_LDO_OUT13: No configuration
 [  257.783668] P3.0V_LDO_OUT12: No configuration
 [  257.788013] P1.8V_LDO_OUT11: No configuration
 [  257.792353] P1.8V_LDO_OUT10: No configuration
 [  257.796693] LDO9: No configuration
 [  257.800079] P1.0V_LDO_OUT8: No configuration
 [  257.804332] P1.1V_LDO_OUT7

Re: [PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

On 15/01/15 17:04, Tony Lindgren wrote:
 * Marc Zyngier marc.zyng...@arm.com [150115 06:53]:
 On Thu, Jan 15 2015 at  2:40:16 pm GMT, Nishanth Menon n...@ti.com wrote:
 On 14:28-20150115, Marc Zyngier wrote:
 Assuming the workaround I posted earlier works, the OMAP/DRA7 part of
 this series is going to require some rework too (I need to know where
 these legacy interrupts are attached: crossbar, WUGEN, or GIC?).

 crossbar will never work with legacy static interrupts anyways - since
 there was never a static interrupt possible - I believe we had removed
 all the legacy hardcoded interrupt definitions for DRA7. ideally, they
 should all be dt only now.

 Yes, I guessed as much after looking at the DRA7XX hwmod.

 So only OMAP4/5 is b0rken at the moment. I can probably work around it
 as I did in this example patch, just by changing the compatible strings
 for the xlate callback. Very ugly.
 
 For the -rc, it seems the wakeupen still needs a fix as based on grepping
 for OMAP44XX_IRQ_GIC_START. Got any great ideas for that?

I think this one is fine. It computes the SPI number based on the hwirq
coming from the GIC. That direction is completely unaffected by the
linear domain stuff. It is only when you try to use a hardware IRQ as a
Linux IRQ that you run into trouble.

Thanks,

M.
-- 
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Re: Regression with legacy IRQ numbers caused by 9a1091ef0017

[Marc Zyngier]

On Thu, Jan 15 2015 at  2:27:56 pm GMT, Arnd Bergmann a...@arndb.de wrote:
 On Thursday 15 January 2015 13:42:57 Marc Zyngier wrote:
 Of course, this is in no way a proper fix, but I suppose the OMAP DT is
 still missing a few bits...

 I must be missing something here, but all the interrupts are listed
 correctly in the DT, so what is the omap_hwmod_irq_info actually
 achieving on omap4 and omap5?

 Would it work if we just remove the incorrect copy of the resource
 and use the one that comes from DT?

By the look of it, omap_hwmod_irq_info serves multiple purposes:
- low level configuration (pads, probably more stuff)
- interrupt description for some drivers, using resources.

It should be fairly easy to do the latter, but the former looks more
tricky (it would push the pad configuration down to the drivers, which
is avoided at the moment).

Probably there is a workable strategy, but my knowledge about OMAP is
close to *nothing*...

M.
-- 
Jazz is not dead. It just smells funny.
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[PATCH] ARM: OMAP: Work around hardcoded interrupts

[Marc Zyngier]

Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.

Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.

This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.

It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.

Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-omap2/common.h   |  1 +
 arch/arm/mach-omap2/omap4-common.c | 32 ++
 arch/arm/mach-omap2/omap_hwmod.c   | 10 --
 arch/arm/mach-omap2/omap_hwmod.h   |  1 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  5 +
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c |  1 +
 arch/arm/mach-omap2/prcm-common.h  |  1 +
 arch/arm/mach-omap2/prm44xx.c  |  1 +
 arch/arm/mach-omap2/prm_common.c   | 14 +++--
 arch/arm/mach-omap2/twl-common.c   |  5 -
 10 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea8..b664494 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 
+unsigned int omap4_xlate_irq(unsigned int hwirq);
 void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap4-common.c 
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44a..cc30e49 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id gic_match[] = {
+   { .compatible = arm,cortex-a9-gic, },
+   { .compatible = arm,cortex-a15-gic, },
+   { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+   struct of_phandle_args irq_data;
+   unsigned int irq;
+
+   if (!gic_node)
+   gic_node = of_find_matching_node(NULL, gic_match);
+
+   if (WARN_ON(!gic_node))
+   return hwirq;
+
+   irq_data.np = gic_node;
+   irq_data.args_count = 3;
+   irq_data.args[0] = 0;
+   irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+   irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+   irq = irq_create_of_mapping(irq_data);
+   if (WARN_ON(!irq))
+   irq = hwirq;
+
+   return irq;
+}
+
 void __init omap_gic_of_init(void)
 {
struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908d..9025fff 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, 
struct resource *res)
 
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i  mpu_irqs_cnt; i++) {
+   unsigned int irq;
+
+   if (oh-xlate_irq)
+   irq = oh-xlate_irq((oh-mpu_irqs + i)-irq);
+   else
+   irq = (oh-mpu_irqs + i)-irq;
(res + r)-name = (oh-mpu_irqs + i)-name;
-   (res + r)-start = (oh-mpu_irqs + i)-irq;
-   (res + r)-end = (oh-mpu_irqs + i)-irq;
+   (res + r)-start = irq;
+   (res + r)-end = irq;
(res + r)-flags = IORESOURCE_IRQ;
r++;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 35ca6ef..5b42faf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@ struct omap_hwmod {
spinlock_t  _lock;
struct list_headnode;
struct omap_hwmod_ocp_if*_mpu_port;
+   unsigned int(*xlate_irq)(unsigned int);
u16 flags;
u8  mpu_rt_idx;
u8  response_lat;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c314b3c..f5e68a7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -479,6 +479,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.class  = omap44xx_dma_hwmod_class,
.clkdm_name = l3_dma_clkdm,
.mpu_irqs   = omap44xx_dma_system_irqs,
+   .xlate_irq

Re: [PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

On Thu, Jan 15 2015 at  2:40:16 pm GMT, Nishanth Menon n...@ti.com wrote:
 On 14:28-20150115, Marc Zyngier wrote:
 Assuming the workaround I posted earlier works, the OMAP/DRA7 part of
 this series is going to require some rework too (I need to know where
 these legacy interrupts are attached: crossbar, WUGEN, or GIC?).
 
 crossbar will never work with legacy static interrupts anyways - since
 there was never a static interrupt possible - I believe we had removed
 all the legacy hardcoded interrupt definitions for DRA7. ideally, they
 should all be dt only now.

Yes, I guessed as much after looking at the DRA7XX hwmod.

So only OMAP4/5 is b0rken at the moment. I can probably work around it
as I did in this example patch, just by changing the compatible strings
for the xlate callback. Very ugly.

M.
-- 
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Re: Regression with legacy IRQ numbers caused by 9a1091ef0017

[Marc Zyngier]

On Wed, Jan 14 2015 at 10:14:08 pm GMT, Tony Lindgren t...@atomide.com wrote:
 Hi all,

 Looks like the legacy IRQ numbers are now all wrong at least for omap4
 since commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain.).

 Instead of this:

 # cat /proc/interrupts 
 CPU0   CPU1   
  29:   1124981   GIC  29  twd
  39:  0  0   GIC  39  TWL6030-PIH
  41:  0  0   GIC  41  l3-dbg-irq
  42:  0  0   GIC  42  l3-app-irq
  44:  0  0   GIC  44  DMA
  45:   7854  0   GIC  45  omap-dma-engine
  52:  0  0   GIC  52  gpmc
 ...


 We now have:

 # cat /proc/interrupts 
 CPU0   CPU1   
  16:343  0   GIC  69  gp_timer
  17:   1160   1017   GIC  29  twd
  18:  0  0   GIC  41  l3-dbg-irq
  19:  1  0   GIC  42  l3-app-irq
  22:   7850  0   GIC  45  omap-dma-engine
  44:  0  0  4a31.gpio  18  DMA
  61:   2730  0  48055000.gpio   2  eth0
 223:  0  0   GIC  52  gpmc
 ...

 So the DMA interrupt using the legacy mapping with something like
 irq = 12 + OMAP44XX_IRQ_GIC_START now is wrong and unfortunately
 at least omaps still have a bunch of the legacy interrupts still
 around.

Holy crap. How much of this do we have hanging around?

 And that naturally produces all kinds of strange errors like:

 WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147 
 l3_interrupt_handler+0x214/0x340()
 4400.ocp:L3 Custom Error: MASTER MPU TARGET L4CFG (Idle): Data Access in 
 Supervisor mode during Functional access
 ...
 [c05f21e4] (__irq_svc) from [c05f1974] 
 (_raw_spin_unlock_irqrestore+0x34/0x44)
 [c05f1974] (_raw_spin_unlock_irqrestore) from [c00914a8] 
 (__setup_irq+0x244/0x530)
 [c00914a8] (__setup_irq) from [c00917d4] (setup_irq+0x40/0x8c)
 [c00917d4] (setup_irq) from [c0039c8c] (omap_system_dma_probe+0x1d4/0x2b4)
 [c0039c8c] (omap_system_dma_probe) from [c03b2200] 
 (platform_drv_probe+0x44/0xa4)
 ...

 Looks like the logic changed from:

 if (of_property_read_u32(node, arm,routable-irqs, nr_routable_irqs))

 to just

 if (node)

 Which now causes irq_domain_add_linear() to be called instead of
 irq_domain_add_legacy(), which causes the breakage.

 Anybody got a sane fix in mind for the -rc series, or should we just
 revert it for now?

Reverting it is going to kill other platforms, and I'd rather have a
workaround, short of fixing it for good (which seems ambitious at -rc4).

How about something along these lines:

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea8..b664494 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 
+unsigned int omap4_xlate_irq(unsigned int hwirq);
 void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap4-common.c 
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44a..cc30e49 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id gic_match[] = {
+   { .compatible = arm,cortex-a9-gic, },
+   { .compatible = arm,cortex-a15-gic, },
+   { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+   struct of_phandle_args irq_data;
+   unsigned int irq;
+
+   if (!gic_node)
+   gic_node = of_find_matching_node(NULL, gic_match);
+
+   if (WARN_ON(!gic_node))
+   return hwirq;
+
+   irq_data.np = gic_node;
+   irq_data.args_count = 3;
+   irq_data.args[0] = 0;
+   irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+   irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+   irq = irq_create_of_mapping(irq_data);
+   if (WARN_ON(!irq))
+   irq = hwirq;
+
+   return irq;
+}
+
 void __init omap_gic_of_init(void)
 {
struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908d..9025fff 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, 
struct resource *res)
 
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i  mpu_irqs_cnt; i++) {
+   unsigned int irq;
+
+   if (oh-xlate_irq)
+   irq = oh-xlate_irq((oh-mpu_irqs + i)-irq);
+   else
+   irq = (oh-mpu_irqs + i)-irq;
(res + r)-name = (oh-mpu_irqs + i)-name;
-   (res + r)-start = (oh-mpu_irqs + 

Re: [PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

On Wed, Jan 14 2015 at 10:28:14 pm GMT, Tony Lindgren t...@atomide.com wrote:
 * Marc Zyngier marc.zyng...@arm.com [150112 10:30]:
 OMAP4/5 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.
 
 This patch does just this, updating the DT files to actually
 reflect what the HW provides.
 
 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the WUGEN HW block, kernels with this patch applied
 won't have any suspend-resume facility when booted with old DTs,
 and old kernels with updated DTs won't even boot.
 
 On a platform with this patch applied, the system looks like
 this:
 
 root@bacon-fat:~# cat /proc/interrupts
 CPU0   CPU1
  16:  0  0 WUGEN  37  gp_timer
  19: 233799 155916   GIC  27  arch_timer
  23:  0  0 WUGEN   9  l3-dbg-irq
  24:  1  0 WUGEN  10  l3-app-irq
  27:282  0 WUGEN  13  omap-dma-engine
  44:  0  0  4ae1.gpio  13  DMA

 FYI, the legacy irq numbers are now all wrong since commit
 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain.).

 Started a separate thread Regression with legacy IRQ numbers
 caused by 9a1091ef0017 on it, will give these a try once
 that's sorted out.

Assuming the workaround I posted earlier works, the OMAP/DRA7 part of
this series is going to require some rework too (I need to know where
these legacy interrupts are attached: crossbar, WUGEN, or GIC?).

Thanks,

M.
-- 
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Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 13/01/15 06:09, Linus Walleij wrote:

Hi Linus,

 On Mon, Jan 12, 2015 at 7:26 PM, Marc Zyngier marc.zyng...@arm.com wrote:
 
 IMX6 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the GPC block is actually the first
 interrupt controller in the chain, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs won't even boot.

 Tested-by: Stefan Agner ste...@agner.ch
 Acked-by: Stefan Agner ste...@agner.ch
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 
 (...)
 
 +static int imx_gpc_domain_alloc(struct irq_domain *domain,
 + unsigned int virq,
 
 Nutcase nitpick on this nice patch series: every time I see virq my
 OCD triggers, as I think the v in virq stand for virtual. These irqs
 are no more virtual than any other Linux irq numbers, hwirq is
 more to the point.
 
 I just refer to these as irq (sans v) in any code I write.

That's fair enough. I'll update that as I fix some other nits.

Thanks,

M.
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Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 12/01/15 19:00, Stefan Agner wrote:
 Hi Marc,
 
 On 2015-01-12 19:26, Marc Zyngier wrote:
 IMX6 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the GPC block is actually the first
 interrupt controller in the chain, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs won't even boot.

 Tested-by: Stefan Agner ste...@agner.ch
 Acked-by: Stefan Agner ste...@agner.ch
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 ---
  arch/arm/boot/dts/imx6qdl.dtsi  |   7 ++-
  arch/arm/boot/dts/imx6sl.dtsi   |   5 +-
  arch/arm/boot/dts/imx6sx.dtsi   |   5 +-
  arch/arm/mach-imx/common.h  |   1 -
  arch/arm/mach-imx/gpc.c | 127 
 
  arch/arm/mach-imx/mach-imx6q.c  |   1 -
  arch/arm/mach-imx/mach-imx6sl.c |   1 -
  arch/arm/mach-imx/mach-imx6sx.c |   1 -
  8 files changed, 117 insertions(+), 31 deletions(-)

 diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
 index 4fc03b7..aff9ded 100644
 --- a/arch/arm/boot/dts/imx6qdl.dtsi
 +++ b/arch/arm/boot/dts/imx6qdl.dtsi
 @@ -53,6 +53,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -82,7 +83,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   dma_apbh: dma-apbh@0011 {
 @@ -122,6 +123,7 @@
   compatible = arm,cortex-a9-twd-timer;
   reg = 0x00a00600 0x20;
   interrupts = 1 13 0xf01;
 + interrupt-parent = intc;
   clocks = clks IMX6QDL_CLK_TWD;
   };

 @@ -694,8 +696,11 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 + #interrupt-cells = 3;
   interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
 + interrupt-parent = intc;
   };

   gpr: iomuxc-gpr@020e {
 diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
 index 36ab8e0..35099b7 100644
 --- a/arch/arm/boot/dts/imx6sl.dtsi
 +++ b/arch/arm/boot/dts/imx6sl.dtsi
 @@ -72,6 +72,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -95,7 +96,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   ocram: sram@0090 {
 @@ -603,7 +604,9 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 
 GPC is in three base device trees, and missing in all of them. So the
 first is fixed
 
 this one...
 
   interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
 + interrupt-parent = intc;
   };

   gpr: iomuxc-gpr@020e {
 diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
 index 7a24fee..c476e67 100644
 --- a/arch/arm/boot/dts/imx6sx.dtsi
 +++ b/arch/arm/boot/dts/imx6sx.dtsi
 @@ -88,6 +88,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -131,7 +132,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   pmu {
 @@ -700,7 +701,9 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 
 
 ... and this one is still missing.
 
 Sorry I did not see that the first review.

I thought I had them fixed on Sunday, but it looks like I've dropped the
fixup

Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly

[Marc Zyngier]

On 12/01/15 14:14, Rob Herring wrote:
 On Wed, Jan 7, 2015 at 11:42 AM, Marc Zyngier marc.zyng...@arm.com wrote:
 The gic_arch_extn hack that a number of platform use has been nagging
 me for too long. It is only there for the benefit of a few platform,
 and yet it impacts all GIC users. Moreover, it gives people the wrong
 idea (let's use it to put some new custom hack in there...).

 But now that stacked irq domains have landed in -next, the time has
 come for gic_arch_extn to meet the Big Bit Bucket.
 
 [...]
 
 - This actively *breaks* existing setups. Once you boot a new kernel
   with an old DT, suspend/resume *will* be broken. Old kernels on a
   new DT won't even boot! You've been warned. This really outline the
   necessity of actually describing the HW in device trees...
 
 Just to be clear, you need some agreement from the maintainers of
 those platforms before doing this. It doesn't appear there is
 disagreement, but I don't see any explicit agreement either.

I'm not trying to go behind anyone's back, if that's your concern. I
fully intend to obtain every maintainer's explicit acknowledgement
before removing any feature from the kernel. The warning above is there
to get the maintainers attention on the disrupting effect of this series.

 This seems to model the interrupts as chained, but at least for some
 cases aren't these auxiliary controllers in parallel to the GIC? In

From looking at the various TRMs, they all look to be chained interrupt
controllers (at least Tegra, OMAP and IMX6 show this). I have not been
able to find a publicly available TRM for any of the Samsung platforms,
so this one could be different (but I really doubt it somehow).

 other words, do the they require configuration for interrupts to work
 for the normal non-wakeup use? I'm not sure that the h/w is being
 modeled any more accurately if that is the case. However, we don't
 really have a way to describe an interrupt line is connected to 2
 interrupt parents in DT, so I'm not sure what else you could do here.

The main problem is that they are not general-purpose interrupt
controllers. They all come first on the interrupt path, and somehow feed
two signals into the GIC: the actual interrupt, and the bypass signal.

None of that is representable in DT. I'm willing to take any idea though.

Thanks,

M.
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[PATCH v3 09/21] DT: update ti,irq-crossbar binding

[Marc Zyngier]

Make it look like a real interrupt controller.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../devicetree/bindings/arm/omap/crossbar.txt  | 18 +-
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt 
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be ti,irq-crossbar
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt 
controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be 
routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-   crossbar_mpu: @4a02 {
+   crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
-   ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+   ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further 
details.
 
 An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as 
a
-quirky hardware mapping direct to GIC.
 
 Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
-   device_y@0x4a033000 {
-   /* Direct mapped GIC SPI 1 used */
-   interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
-   ...
-   };
-- 
2.1.4

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[PATCH v3 06/21] ARM: tegra: remove old LIC support

[Marc Zyngier]

Now that all DTs have been updated, entierely drop support for
the non-DT code.

This is likely to break platforms that do not update their DT,
so print a warning at boot time.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/iomap.h |  15 
 arch/arm/mach-tegra/irq.c   | 201 +---
 arch/arm/mach-tegra/irq.h   |   6 --
 3 files changed, 2 insertions(+), 220 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
 #define TEGRA_ARM_INT_DIST_BASE0x50041000
 #define TEGRA_ARM_INT_DIST_SIZESZ_4K
 
-#define TEGRA_PRIMARY_ICTLR_BASE   0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE   SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE  0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE  SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE   0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE   SZ_64
-
 #define TEGRA_TMR1_BASE0x60005000
 #define TEGRA_TMR1_SIZESZ_8
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1593c4c..3b9098d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
 #include board.h
 #include iomap.h
 
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR  0x14
-#define ICTLR_CPU_IEP_FIR_SET  0x18
-#define ICTLR_CPU_IEP_FIR_CLR  0x1c
-
-#define ICTLR_CPU_IER  0x20
-#define ICTLR_CPU_IER_SET  0x24
-#define ICTLR_CPU_IER_CLR  0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER  0x30
-#define ICTLR_COP_IER_SET  0x34
-#define ICTLR_COP_IER_CLR  0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS   5
-
 #define SGI_MASK 0x
 
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
-   IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
 #ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
 static void __iomem *tegra_gic_cpu_base;
 #endif
 
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
 }
 
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
-   void __iomem *base;
-   u32 mask;
-
-   BUG_ON(irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
-   base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
-   __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return 0;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
-   return 1;
-}
-
 #ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
-   u32 irq = d-hwirq;
-   u32 index, mask;
-
-   if (irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
-   return -EINVAL;
-
-   index = ((irq - FIRST_LEGACY_IRQ) / 32);
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-   if (enable)
-   ictlr_wake_mask[index] |= mask;
-   else
-   ictlr_wake_mask[index] = ~mask;
-
-   return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
-   unsigned long flags;
-   int i;
-
-   local_irq_save(flags);
-   for (i = 0; i  num_ictlrs; i++) {
-   void __iomem *ictlr = ictlr_reg_base[i];
-   /* Save interrupt state */
-   cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
-   cpu_iep[i

[PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.

Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/imx6qdl.dtsi  |   7 ++-
 arch/arm/boot/dts/imx6sl.dtsi   |   5 +-
 arch/arm/boot/dts/imx6sx.dtsi   |   5 +-
 arch/arm/mach-imx/common.h  |   1 -
 arch/arm/mach-imx/gpc.c | 127 
 arch/arm/mach-imx/mach-imx6q.c  |   1 -
 arch/arm/mach-imx/mach-imx6sl.c |   1 -
 arch/arm/mach-imx/mach-imx6sx.c |   1 -
 8 files changed, 117 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..aff9ded 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+   interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
 
@@ -694,8 +696,11 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
+   #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
 0 90 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..c476e67 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};
 
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;
 
pmu {
@@ -700,7 +701,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
interrupts = GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};
 
iomuxc: iomuxc@020e {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cfcdb62..7052302 100644
--- a/arch/arm/mach-imx

[PATCH v3 05/21] DT: tegra: add binding for the legacy interrupt controller

[Marc Zyngier]

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/nvidia,tegra-ictlr.txt| 43 ++
 1 file changed, 43 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt 
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..1099fe0
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+
+Required properties:
+
+- compatible : should be: nvidia,tegrachip-ictlr. The LIC on
+  subsequent SoCs remained backwards-compatible with Tegra30, so on
+  Tegra generations later than Tegra30 the compatible value should
+  include nvidia,tegra30-ictlr.  
+- reg : Specifies base physical address and size of the registers.
+  Each controller must be described separately (Tegra20 has 4 of them,
+  whereas Tegra30 and later have 5  
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+  are explicitly forbidden.
+
+Example:
+
+   ictlr: interrupt-controller@60004000 {
+   compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+   reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = intc;
+   };
-- 
2.1.4

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[PATCH v3 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake

[Marc Zyngier]

shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.

It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function.

Acked-by: Simon Horman horms+rene...@verge.net.au
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-shmobile/intc-sh73a0.c   | 7 +--
 arch/arm/mach-shmobile/setup-r8a7779.c | 7 +--
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c 
b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9e36180..fd63ae6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,11 +252,6 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void 
*dev_id)
return IRQ_HANDLED;
 }
 
-static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
-{
-   return 0; /* always allow wakeup */
-}
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -318,8 +313,8 @@ void __init sh73a0_init_irq(void)
void __iomem *gic_cpu_base = IOMEM(0xf100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
-   gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
register_intc_controller(intcs_desc);
register_intc_controller(intc_pint0_desc);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c 
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d17..989de2d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -713,14 +713,9 @@ void __init r8a7779_init_late(void)
 }
 
 #ifdef CONFIG_USE_OF
-static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
-{
-   return 0; /* always allow wakeup */
-}
-
 void __init r8a7779_init_irq_dt(void)
 {
-   gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
 
irqchip_init();
 
-- 
2.1.4

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[PATCH v3 10/21] irqchip: GIC: get rid of routable domain

[Marc Zyngier]

The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 59 -
 include/linux/irqchip/arm-gic.h |  6 -
 2 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d, 
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-   gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-   gic_routable_irq_domain_ops-unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
 
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-   if (!intspec[0]) {
-   ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
-   if (IS_ERR_VALUE(ret))
-   return ret;
-   }
+   if (!intspec[0])
+   *out_hwirq += 16;
 
*out_type = intspec[2]  IRQ_TYPE_SENSE_MASK;
 
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
-   return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-   struct device_node *controller,
-   const u32 *intspec, unsigned int intsize,
-   unsigned long *out_hwirq,
-   unsigned int *out_type)
-{
-   *out_hwirq += 16;
-   return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-   .map = gic_routable_irq_domain_map,
-   .unmap = gic_routable_irq_domain_unmap,
-   .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-   gic_default_routable_irq_domain_ops;
-
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
-   int nr_routable_irqs;
 
BUG_ON(gic_nr = MAX_GIC_NR);
 
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
gic-gic_irqs = gic_irqs;
 
if (node) { /* DT case */
-   const struct irq_domain_ops *ops = 
gic_irq_domain_hierarchy_ops;
-
-   if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
-   ops = gic_irq_domain_ops;
-   gic_irqs = nr_routable_irqs;
-   }
-
-   gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+   gic-domain = irq_domain_add_linear(node, gic_irqs,
+   
gic_irq_domain_hierarchy_ops,
+   gic);
} else {/* Non-DT case */
/*
 * For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-   (const struct irq_domain_ops *ops)
-{
-   gic_routable_irq_domain_ops = ops

[PATCH v3 13/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.

On a platform with this patch applied, the system looks like
this:

root@bacon-fat:~# cat /proc/interrupts
CPU0   CPU1
 16:  0  0 WUGEN  37  gp_timer
 19: 233799 155916   GIC  27  arch_timer
 23:  0  0 WUGEN   9  l3-dbg-irq
 24:  1  0 WUGEN  10  l3-app-irq
 27:282  0 WUGEN  13  omap-dma-engine
 44:  0  0  4ae1.gpio  13  DMA
294:  0  0 WUGEN  20  gpmc
297:506  0 WUGEN  56  4807.i2c
298:  0  0 WUGEN  57  48072000.i2c
299:  0  0 WUGEN  61  4806.i2c
300:  0  0 WUGEN  62  4807a000.i2c
301:  8  0 WUGEN  60  4807c000.i2c
308:   2439  0 WUGEN  74  OMAP UART2
312:362  0 WUGEN  83  mmc2
313:502  0 WUGEN  86  mmc0
314: 13  0 WUGEN  94  mmc1
350:  0  0  PRCM  pinctrl, pinctrl
406:   35155709  0   GIC 109  ehci_hcd:usb1
407:  0  0 WUGEN   7  palmas
409:  0  0 WUGEN 119  twl6040
410:  0  0   twl6040   5  twl6040_irq_ready
411:  0  0   twl6040   0  twl6040_irq_th
IPI0:  0  1  CPU wakeup interrupts
IPI1:  0  0  Timer broadcast interrupts
IPI2:  95334 902334  Rescheduling interrupts
IPI3:  0  0  Function call interrupts
IPI4:479648  Single function call interrupts
IPI5:  0  0  CPU stop interrupts
IPI6:  0  0  IRQ work interrupts
IPI7:  0  0  completion interrupts
Err:  0

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am4372.dtsi |  11 ++-
 arch/arm/boot/dts/am437x-gp-evm.dts   |   1 -
 arch/arm/boot/dts/am437x-sk-evm.dts   |   1 -
 arch/arm/boot/dts/am43x-epos-evm.dts  |   1 -
 arch/arm/boot/dts/dra7.dtsi   |  12 ++-
 arch/arm/boot/dts/dra72x.dtsi |   2 +-
 arch/arm/boot/dts/dra74x.dtsi |   2 +-
 arch/arm/boot/dts/omap4-duovero.dtsi  |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts   |   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi |   2 -
 arch/arm/boot/dts/omap4.dtsi  |  18 -
 arch/arm/boot/dts/omap5-cm-t54.dts|   1 -
 arch/arm/boot/dts/omap5-uevm.dts  |   2 -
 arch/arm/boot/dts/omap5.dtsi  |  26 ---
 arch/arm/mach-omap2/omap-wakeupgen.c  | 125 +++---
 arch/arm/mach-omap2/omap-wakeupgen.h  |   1 -
 arch/arm/mach-omap2/omap4-common.c|   1 -
 18 files changed, 154 insertions(+), 70 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 
 / {
compatible = ti,am4372, ti,am43;
-   interrupt-parent = gic;
+   interrupt-parent = wakeupgen;
 
 
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
  0x48240100 0x0100;
+   interrupt-parent = gic;
+   };
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
};
 
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts 
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4c..69f2313 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts 
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc9..029bade 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
-   interrupt-parent = gic;
interrupts = GIC_SPI 7

[PATCH v3 16/21] DT: exynos: update PMU binding

[Marc Zyngier]

Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt 
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
  - clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
 
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+  this PMU signals interrupts to.
+
 Example :
 pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+   interrupt-controller;
+   interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
-- 
2.1.4

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[PATCH v3 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags

[Marc Zyngier]

Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.

Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-ux500/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
 */
 void __init ux500_init_irq(void)
 {
-   gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
 
/*
-- 
2.1.4

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[PATCH v3 07/21] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 include/linux/irq.h |  1 +
 kernel/irq/chip.c   | 16 
 2 files changed, 17 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 /* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data:  Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this 
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+   data = data-parent_data;
+   if (data-chip-irq_set_wake)
+   return data-chip-irq_set_wake(data, on);
+
+   return -ENOSYS;
+}
 #endif
 
 /**
-- 
2.1.4

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[PATCH v3 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller

[Marc Zyngier]

Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.

The stacked IRQ domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/Makefile|   1 +
 drivers/irqchip/irq-tegra.c | 368 
 2 files changed, 369 insertions(+)
 create mode 100644 drivers/irqchip/irq-tegra.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
 obj-$(CONFIG_DW_APB_ICTL)  += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..e1ac65e
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,368 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR  0x14
+#define ICTLR_CPU_IEP_FIR_SET  0x18
+#define ICTLR_CPU_IEP_FIR_CLR  0x1c
+
+#define ICTLR_CPU_IER  0x20
+#define ICTLR_CPU_IER_SET  0x24
+#define ICTLR_CPU_IER_CLR  0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER  0x30
+#define ICTLR_COP_IER_SET  0x34
+#define ICTLR_COP_IER_CLR  0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS   5
+
+static unsigned int num_ictlrs;
+
+struct tegra_ictlr_soc {
+   unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+   .num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+   .num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+   { .compatible = nvidia,tegra30-ictlr, .data = tegra30_ictlr_soc },
+   { .compatible = nvidia,tegra20-ictlr, .data = tegra20_ictlr_soc },
+   { }
+};
+
+struct tegra_ictlr_info {
+   void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+   u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+   u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *lic;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long 
reg)
+{
+   void __iomem *base = d-chip_data;
+   u32 mask;
+
+   mask = BIT(d-hwirq % 32);
+   writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+   irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+   irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+   irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+   return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+   u32 irq = d-hwirq;
+   u32 index, mask;
+
+   index = (irq / 32);
+   mask = BIT(irq % 32);
+   if (enable)
+   lic-ictlr_wake_mask[index] |= mask;
+   else
+   lic-ictlr_wake_mask[index] = ~mask

[PATCH v3 00/21] irqchip: gic: killing gic_arch_extn and co, slowly

[Marc Zyngier]

The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea (let's use it to put some new custom hack in there...).

But now that stacked irq domains have been merged into 3.19, the time
has come for gic_arch_extn to meet the Big Bit Bucket.

This patch series takes several steps towards the elimination of
gic_arch_extn:

- moves Tegra's legacy interrupt controller support to
  drivers/irqchip, implementing a stacked domain on top of the
  standard GIC.

- OMAP, imx6 and exynos are also converted to stacked domains, but
  their implementation is left in place (the code is far too
  intricately mixed with other details of the platform for me to even
  try to move it). Some OMAP variants get a special treatment as we
  also kill the crossbar horror (more on that below).

- shmobile, ux500 and zynq are only slightly modified.

- The GIC itself is cleaned up, and some other bits and bobs are
  adjusted for a good measure.

About the TI crossbar:

- The allocation of interrupts in this domain is fairly similar to
  what we do for MSI (see the GICv2m driver), and stacked domains have
  proved to be a fitting solution.

- The current description in DT is currently entierely inaccurate, and
  as we're already breaking it for the WUGEN block, we might as well
  do it again for the crossbar.

- The way crossbar, WUGEN and GIC interract is quite complex (this is
  effectively a stack of three interrupt controllers with interesting
  exceptions and braindead routing), and stacked domains are the right
  abstraction for that.

- Other platforms (Freescale Vybrid) are starting to come up with the
  same type of things, and it'd be good to avoid them following the
  same broken model.

- It removes a few lines from the code base so it can't completely be
  a bad idea!

So this patch series does exactly that: make the crossbar a stacked
interrupt controller that only takes care of setting up the routing,
fix the DTs to represent the actual HW, and remove a bit of the
craziness from the GIC code.

It is worth realizing that:

- I haven't been able to test this as much as I would have wanted to
  (it's only been tested on tegra2 and omap5).

- I've created DT bindings when needed, updated existing ones, but I
  haven't created a binding for platforms that already used an
  undocumented one (imx6, I'm looking at you).

- I've relaxed quite a bit of the locking in the GIC code. I believe
  this is safe, but someone else should give it a long hard look.

- This actively *breaks* existing setups. Once you boot a new kernel
  with an old DT, suspend/resume *will* be broken. Old kernels on a
  new DT won't even boot! You've been warned. This really outline the
  necessity of actually describing the HW in device trees...

As for the patches, they are on top of 3.19-rc3.

I've pushed the code to:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git 
irq/die-gic-arch-extn-die-die-die

I'm still targetting 3.20 for this, but obviously things are getting
quite tight. I'd very much like to hear from the maintainers about
their views concerning this series.

Thanks,

 M.

From v2 [2]:
- Addressed numerous comments from Thierry
- Merged bug fixes from Nishanth
- Merged bug fix from Stefan

From v1 [1]:
- Rebased on 3.19-rc3
- Added crossbar conversion to stacked domains
- Merged bug fixes from Nishanth

Marc Zyngier (21):
  ARM: tegra: irq: nuke leftovers from non-DT support
  irqchip: tegra: add DT-based support for legacy interrupt controller
  ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
  ARM: tegra: update DTs to expose legacy interrupt controller
  DT: tegra: add binding for the legacy interrupt controller
  ARM: tegra: remove old LIC support
  genirq: Add irqchip_set_wake_parent
  irqchip: crossbar: convert dra7 crossbar to stacked domains
  DT: update ti,irq-crossbar binding
  irqchip: GIC: get rid of routable domain
  DT: arm,gic: kill arm,routable-irqs
  DT: omap4/5: add binding for the wake-up generator
  ARM: omap: convert wakeupgen to stacked domains
  ARM: imx6: convert GPC to stacked domains
  ARM: exynos4/5: convert pmu wakeup to stacked domains
  DT: exynos: update PMU binding
  irqchip: gic: add an entry point to set up irqchip flags
  ARM: shmobile: remove use of gic_arch_extn.irq_set_wake
  ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
  ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
  irqchip: gic: Drop support for gic_arch_extn

 Documentation/devicetree/bindings/arm/gic.txt  |   6 -
 .../devicetree/bindings/arm/omap/crossbar.txt  |  18 +-
 .../devicetree/bindings/arm/samsung/pmu.txt|  13 +
 .../interrupt-controller/nvidia,tegra-ictlr.txt|  43 +++
 .../interrupt-controller/ti,omap4-wugen-mpu|  33 ++
 arch/arm/boot/dts/am4372.dtsi  |  11 +-
 arch/arm

[PATCH v3 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts |   3 +-
 arch/arm/boot/dts/dra7-evm.dts  |   2 +-
 arch/arm/boot/dts/dra7.dtsi |  35 +++---
 arch/arm/boot/dts/dra72-evm.dts |   1 -
 arch/arm/boot/dts/dra72x.dtsi   |   3 +-
 arch/arm/boot/dts/dra74x.dtsi   |   5 +-
 arch/arm/mach-omap2/omap4-common.c  |   4 -
 drivers/irqchip/irq-crossbar.c  | 207 ++--
 include/linux/irqchip/irq-crossbar.h|  11 --
 9 files changed, 146 insertions(+), 125 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts 
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..c2241c2 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
-   interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW;  /* IRQ_SYS_1N */
 
pinctrl-names = default;
@@ -358,7 +357,7 @@
 
 uart3 {
status = okay;
-   interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x248;
 
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
-   interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+   interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
  dra7_pmx_core 0x3e0;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..6f90673 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
 #include skeleton.dtsi
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
#address-cells = 1;
#size-cells = 1;
 
compatible = ti,dra7xx;
-   interrupt-parent = gic;
+   interrupt-parent = crossbar_mpu;
 
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
 GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
-   arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
  0x48212000 0x1000,
  0x48214000 0x2000,
  0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
  0x4500 0x1000;
-   interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 4 
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
 
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
-   interrupts-extended = gic GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts-extended = crossbar_mpu GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
-   interrupts-extended = gic GIC_SPI 68 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH

[PATCH v3 04/21] ARM: tegra: update DTs to expose legacy interrupt controller

[Marc Zyngier]

Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/tegra114.dtsi | 16 +++-
 arch/arm/boot/dts/tegra124.dtsi | 16 +++-
 arch/arm/boot/dts/tegra20.dtsi  | 15 ++-
 arch/arm/boot/dts/tegra30.dtsi  | 16 +++-
 4 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f58a3d9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
 
 / {
compatible = nvidia,tegra114;
-   interrupt-parent = gic;
+   interrupt-parent = lic;
 
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
  0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
+   };
+
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra114-ictlr, nvidia,tegra30-ictlr;
+   reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50,
+ 0x60004400 0x50;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
};
 
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..db85695 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
 
 / {
compatible = nvidia,tegra124;
-   interrupt-parent = gic;
+   interrupt-parent = lic;
#address-cells = 2;
#size-cells = 2;
 
@@ -173,6 +173,7 @@
  0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;
};
 
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
 
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra124-ictlr, nvidia,tegra30-ictlr;
+   reg = 0x0 0x60004000 0x0 0x100,
+ 0x0 0x60004100 0x0 0x100,
+ 0x0 0x60004200 0x0 0x100,
+ 0x0 0x60004300 0x0 0x100,
+ 0x0 0x60004400 0x0 0x100;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = gic;
+   };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
 GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;
};
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..362bb21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
 
 / {
compatible = nvidia,tegra20;
-   interrupt-parent = intc;
+   interrupt-parent = lic;
 
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
 
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+   interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
   0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+   interrupt-parent = intc;
};
 
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
 
+   lic: interrupt-controller@60004000 {
+   compatible = nvidia,tegra20-ictlr;
+   reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   interrupt-parent = intc;
+   };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..6bea674 100644

[PATCH v3 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains

[Marc Zyngier]

Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.

Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/exynos4.dtsi|   3 +
 arch/arm/boot/dts/exynos5250.dtsi |   3 +
 arch/arm/boot/dts/exynos5420.dtsi |   3 +
 arch/arm/mach-exynos/exynos.c |  14 ++---
 arch/arm/mach-exynos/suspend.c| 122 ++
 5 files changed, 126 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..adc189f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,8 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+   interrupt-controller;
+   interrupt-parent = gic;
};
 
dsi_0: dsi@11C8 {
@@ -253,6 +255,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+   interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..c31007c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   interrupt-parent = gic;
};
 
sysreg_system_controller: syscon@1005 {
@@ -230,6 +232,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};
 
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..1946c76c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+   interrupt-parent = pmu_system_controller;
status = disabled;
};
 
@@ -748,6 +749,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+   interrupt-controller;
+   interrupt-parent = gic;
};
 
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
 }
 
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
 static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
-   { .compatible = samsung,exynos4210-pmu },
-   { .compatible = samsung,exynos4212-pmu },
-   { .compatible = samsung,exynos4412-pmu },
-   { .compatible = samsung,exynos4415-pmu },
-   { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
-   { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
 };
 
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
-   if (!pmu_base_addr)
-   panic(failed to find exynos pmu register\n);
 }
 
 static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..b325ecd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
 #include linux/syscore_ops.h
 #include linux/cpu_pm.h
 #include linux/io.h
-#include linux/irqchip/arm-gic.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h

[PATCH v3 12/21] DT: omap4/5: add binding for the wake-up generator

[Marc Zyngier]

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+  ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+
+Example:
+
+   wakeupgen: interrupt-controller@48281000 {
+   compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+   interrupt-controller;
+   #interrupt-cells = 3;
+   reg = 0x48281000 0x1000;
+   interrupt-parent = gic;
+   };
-- 
2.1.4

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[PATCH v3 01/21] ARM: tegra: irq: nuke leftovers from non-DT support

[Marc Zyngier]

The GIC is now always initialized from DT on tegra, and there is
no point in keeping non-DT init code.

Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/irq.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index ab95f53..7f87a50 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -283,13 +283,5 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
-   /*
-* Check if there is a devicetree present, since the GIC will be
-* initialized elsewhere under DT.
-*/
-   if (!of_have_populated_dt())
-   gic_init(0, 29, distbase,
-   IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
tegra114_gic_cpu_pm_registration();
 }
-- 
2.1.4

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[PATCH v3 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node

[Marc Zyngier]

If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.

This is only a temporary measure until that code is removed for good.

Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/irq.c   | 12 
 arch/arm/mach-tegra/tegra.c |  1 -
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..1593c4c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,22 @@ static void tegra114_gic_cpu_pm_registration(void)
 static void tegra114_gic_cpu_pm_registration(void) { }
 #endif
 
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+   { .compatible = nvidia,tegra20-ictlr },
+   { .compatible = nvidia,tegra30-ictlr },
+   { }
+};
+
 void __init tegra_init_irq(void)
 {
int i;
void __iomem *distbase;
 
+   if (of_find_matching_node(NULL, tegra_ictlr_match))
+   goto skip_extn_setup;
+
+   tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR)  0x1f;
 
@@ -283,5 +294,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
 }
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
 {
tegra_init_irq();
irqchip_init();
-   tegra_legacy_irq_syscore_init();
 }
 
 static void __init tegra_dt_init(void)
-- 
2.1.4

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[PATCH v3 11/21] DT: arm,gic: kill arm,routable-irqs

[Marc Zyngier]

Nobody will regret it.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 Documentation/devicetree/bindings/arm/gic.txt | 6 --
 1 file changed, 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt 
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
 Example:
 
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
-   arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
  0xfff10100 0x100;
};
-- 
2.1.4

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[PATCH v3 21/21] irqchip: gic: Drop support for gic_arch_extn

[Marc Zyngier]

Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 54 -
 include/linux/irqchip/arm-gic.h |  2 --
 2 files changed, 56 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 #define NR_GIC_CPU_IF 8
 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
-   .irq_eoi= NULL,
-   .irq_mask   = NULL,
-   .irq_unmask = NULL,
-   .irq_retrigger  = NULL,
-   .irq_set_type   = NULL,
-   .irq_set_wake   = NULL,
-};
-
 #ifndef MAX_GIC_NR
 #define MAX_GIC_NR 1
 #endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
 {
u32 mask = 1  (gic_irq(d) % 32);
 
-   raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + 
(gic_irq(d) / 32) * 4);
-   if (gic_arch_extn.irq_mask)
-   gic_arch_extn.irq_mask(d);
-   raw_spin_unlock(irq_controller_lock);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
u32 mask = 1  (gic_irq(d) % 32);
 
-   raw_spin_lock(irq_controller_lock);
-   if (gic_arch_extn.irq_unmask)
-   gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + 
(gic_irq(d) / 32) * 4);
-   raw_spin_unlock(irq_controller_lock);
 }
 
 static void gic_eoi_irq(struct irq_data *d)
 {
-   if (gic_arch_extn.irq_eoi) {
-   raw_spin_lock(irq_controller_lock);
-   gic_arch_extn.irq_eoi(d);
-   raw_spin_unlock(irq_controller_lock);
-   }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 }
 
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int 
type)
if (type != IRQ_TYPE_LEVEL_HIGH  type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
 
-   raw_spin_lock(irq_controller_lock);
-
-   if (gic_arch_extn.irq_set_type)
-   gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
 
-   raw_spin_unlock(irq_controller_lock);
-
return 0;
 }
 
 static int gic_retrigger(struct irq_data *d)
 {
-   if (gic_arch_extn.irq_retrigger)
-   return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
 }
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const 
struct cpumask *mask_val,
 }
 #endif
 
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
-   int ret = -ENXIO;
-
-   if (gic_arch_extn.irq_set_wake)
-   ret = gic_arch_extn.irq_set_wake(d, on);
-
-   return ret;
-}
-
-#else
-#define gic_set_wake   NULL
-#endif
-
 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 {
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
 #ifdef CONFIG_SMP
.irq_set_affinity   = gic_set_affinity,
 #endif
-   .irq_set_wake   = gic_set_wake,
 };
 
 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
set_handle_irq(gic_handle_irq);
}
 
-   gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
 
 struct device_node;
 
-extern struct irq_chip gic_arch_extn;
-
 void gic_set_irqchip_flags(unsigned long flags);
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
-- 
2.1.4

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[PATCH v3 17/21] irqchip: gic: add an entry point to set up irqchip flags

[Marc Zyngier]

A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.

Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/irq-gic.c   | 5 +
 include/linux/irqchip/arm-gic.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
 };
 
+void gic_set_irqchip_flags(unsigned long flags)
+{
+   gic_chip.flags |= flags;
+}
+
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
   void __iomem *dist_base, void __iomem *cpu_base,
   u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
 
 extern struct irq_chip gic_arch_extn;
 
+void gic_set_irqchip_flags(unsigned long flags);
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
-- 
2.1.4

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[PATCH v3 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags

[Marc Zyngier]

Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-zynq/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
 
 static void __init zynq_irq_init(void)
 {
-   gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+   gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
 }
 
-- 
2.1.4

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Re: [PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller

[Marc Zyngier]

On 2015-01-08 10:41, Thierry Reding wrote:

On Wed, Jan 07, 2015 at 05:42:39PM +, Marc Zyngier wrote:

Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/tegra114.dtsi | 16 +++-
 arch/arm/boot/dts/tegra124.dtsi | 16 +++-
 arch/arm/boot/dts/tegra20.dtsi  | 15 ++-
 arch/arm/boot/dts/tegra30.dtsi  | 16 +++-
 4 files changed, 59 insertions(+), 4 deletions(-)



I've updated the patch to reflect the requested changes. See below for 
the few contentious points:


[...]


@@ -134,6 +134,19 @@
  0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+   interrupt-parent = gic;


Is this allowed? It makes the GIC its own parent. I guess we need it 
to

stop a loop from GIC - LIC - GIC, but it doesn't look quite right.


This seems to be the expected construct to override a parent interrupt 
controller. Actually, this is already what happens when you have a 
single interrupt-controller and a global interrupt-parent property.


[...]


timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+   interrupt-parent = gic;


Why does this get to have a non-default parent?


The per-cpu timers are using PPIs.  As such,. they are not routed 
through the LIC, but are wired to the GIC instead.


[...]


timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;


Why doesn't the Tegra timer get to keep the GIC as parent like for
Tegra114 and Tegra124? Instead I see that the Cortex-A9 TWD timer 
gets

to keep the parent instead.


The Tegra timer is using SPI (and can probably be used as a wake-up 
source). As such, it is connected to the LIC, not to the GIC.


Per-CPU timers (arch timer for A15 and TWD for A9) are all using PPIs, 
and are directly wired to the GIC.


[...]


timer@60005000 {
compatible = nvidia,tegra30-timer, nvidia,tegra20-timer;
reg = 0x60005000 0x400;


Like for Tegra20, the Tegra timer is now switched to the LIC as 
parent.


Which, in my understanding, is the right thing to do. Unless I missed 
something obvious about this?


Thanks,

M.
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Re: [PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

On 2015-01-08 14:39, Nishanth Menon wrote:

On 17:42-20150107, Marc Zyngier wrote:
[..]
diff --git a/arch/arm/boot/dts/dra7-evm.dts 
b/arch/arm/boot/dts/dra7-evm.dts

index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
-   interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+	interrupts-extended = crossbar_mpu GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH,

  dra7_pmx_core 0x3e0;

^^ interrrupt-extended for uart1 here
[..]

diff --git a/arch/arm/boot/dts/dra7.dtsi 
b/arch/arm/boot/dts/dra7.dtsi

[...]

@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
-   interrupts-extended = gic GIC_SPI 67 
IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;

^^ implies we will have both interrupts and interrupts-extended
properties for uart1 in dra7-evm.dtb

Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
does not make it clear as to what the priority will be when both
properties are present.


Yup, good call. I don't think it matters (interrupts inherits the 
implicit irq-parent, but consistency is good.



[...]
Also, for 3.19-rc3, Missing the following causing x15 to fail boot.

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
-   interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW;  /* IRQ_SYS_1N */

pinctrl-names = default;
@@ -358,7 +357,7 @@

 uart3 {
status = okay;
-   interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+	interrupts-extended = crossbar_mpu GIC_SPI 69 
IRQ_TYPE_LEVEL_HIGH,

  dra7_pmx_core 0x248;

pinctrl-names = default;


Ah, thanks for the patch, I've folded this in.

Thanks,

M.
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Re: [PATCH v2 07/21] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

On 2015-01-08 15:15, Nishanth Menon wrote:

On 17:42-20150107, Marc Zyngier wrote:

This proves to be usefull with stacked domains, when the current

^^ useful ?
minor:
+WARNING: 'usefull' may be misspelled - perhaps 'useful'?
+#6:
+This proves to be usefull with stacked domains, when the current
+CHECK: extern prototypes should be avoided in .h files
+#23: FILE: include/linux/irq.h:463:
++extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned
int on);


Consistency trumps whatever checkpatch says, I'm afraid.

Thanks,

M.
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Re: [PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator

[Marc Zyngier]

On 2015-01-08 16:52, Nishanth Menon wrote:

On 17:42-20150107, Marc Zyngier wrote:

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 .../interrupt-controller/ti,omap4-wugen-mpu| 32 
++

 1 file changed, 32 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu


diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

new file mode 100644
index 000..16149d9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

@@ -0,0 +1,32 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controllerthat

controller that
+routes interrupts to the GIC, and also serves as a wakeup source. 
It

+is also refered to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu

Could we also document ti,omap5-wugen-mpu. In addition, if you could
make this patch prior to patch #12, it helps the checkpatch at the 
very

least ;)


Sure.


also saw a few checkpatch warnings:
+WARNING: 'refered' may be misspelled - perhaps 'referred'?
+#22: FILE:

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:5:
++is also refered to as WUGEN-MPU, hence the name of the binding.
+WARNING: 'explicitely' may be misspelled - perhaps 'explicitly'?
+#39: FILE:

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu:22:
++  are explicitely forbiden.


+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt 
controller.
+- #interrupt-cells : Specifies the number of cells needed to encode 
an

+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are 
routed

+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs


I think you mean interrupt controller and not nvidia ictlr here.. :)


-ECOPYPASTE... ;-)

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Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller

[Marc Zyngier]

On 2015-01-08 10:13, Thierry Reding wrote:

On Wed, Jan 07, 2015 at 05:42:37PM +, Marc Zyngier wrote:

Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.

The stacked irq domain framework fits this pretty well, and allows


Nit: s/irq/IRQ/


the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/Makefile|   1 +
 drivers/irqchip/irq-tegra.c | 335 


 2 files changed, 336 insertions(+)
 create mode 100644 drivers/irqchip/irq-tegra.c


This matches largely what I have in a local patch (modulo the stacked
domains vs. gic_arch_extn). A few comments below.


[snip]

Thanks for the extensive review. I've implemented all of this, except 
for the hunk below:





diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o


Should these be sorted alphabetically?


Well, the left side is (up to S3C24xx, and then it all goes down the 
drain).

Do you have a suggestion?

Thanks,

M.
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Re: [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller

[Marc Zyngier]

On 2015-01-08 15:06, Nishanth Menon wrote:

On 17:42-20150107, Marc Zyngier wrote:

Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.

The stacked irq domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---


Saw a few checkpatch warnings as below: all of them seem minors.

@@ -0,0 +1,35 @@
+WARNING: added, moved or deleted file(s), does MAINTAINERS need 
updating?


I'll leave to the Tegra maintainers to update this file it they want 
to.



+#36:
+new file mode 100644
+WARNING: line over 80 characters
+#169: FILE: drivers/irqchip/irq-tegra.c:129:
++		tegra_ictlr_info-cpu_ier[i] = readl_relaxed(ictlr + 
ICTLR_CPU_IER);


As a matter of principle, I ignore what checkpatch says about the 
length of lines of code. I trust my eyes more than the tool.


[...]


+WARNING: Missing a blank line after declarations
+#196: FILE: drivers/irqchip/irq-tegra.c:156:
++  void __iomem *ictlr = tegra_ictlr_info-ictlr_reg_base[i];
++  writel_relaxed(tegra_ictlr_info-cpu_iep[i],


Done.


+WARNING: line over 80 characters
+#284: FILE: drivers/irqchip/irq-tegra.c:244:
++	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 
parent_args);

+CHECK: Please don't use multiple blank lines
+#287: FILE: drivers/irqchip/irq-tegra.c:247:
++
++
+WARNING: Missing a blank line after declarations
+#296: FILE: drivers/irqchip/irq-tegra.c:256:
++  struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
++  irq_domain_reset_irq_data(d);
`


Thanks,

M.
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Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly

[Marc Zyngier]

On 2015-01-07 17:42, Marc Zyngier wrote:

The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea (let's use it to put some new custom hack in there...).

But now that stacked irq domains have landed in -next, the time has
come for gic_arch_extn to meet the Big Bit Bucket.

This patch series takes several steps towards the elimination of
gic_arch_extn:

- moves Tegra's legacy interrupt controller support to
  drivers/irqchip, implementing a stacked domain on top of the
  standard GIC.

- OMAP, imx6 and exynos are also converted to stacked domains, but
  their implementation is left in place (the code is far too
  intricately mixed with other details of the platform for me to even
  try to move it). Some OMAP variants get a special treatment as we
  also kill the crossbar horror (more on that below).

- shmobile, ux500 and zynq are only slightly modified.

- The GIC itself is cleaned up, and some other bits and bobs are
  adjusted for a good measure.

About the TI crossbar:

- The allocation of interrupts in this domain is fairly similar to
  what we do for MSI (see the GICv2m driver), and stacked domains 
have

  proved to be a fitting solution.

- The current description in DT is currently entierely inaccurate, 
and
  as we already broke it for the OMAP WUGEN block, we might as well 
do

  it again for the TI crossbar.

- The way crossbar, WUGEN and GIC interract is quite complex (this is
  effectively a stack of three interrupt controllers with interesting
  exceptions and braindead routing), and stacked domains are the 
right

  abstraction for that.

- Other platforms (Freescale Vybrid) are starting to come up with the
  same type of things, and it'd be good to avoid them following the
  same broken model.

- It removes a few lines from the code base so it can't completely be
  a bad idea!

So this patch series does exactly that: make the crossbar a stacked
interrupt controller that only takes care of setting up the routing,
fix the DTs to represent the actual HW, and remove a bit of the
craziness from the GIC code.

It is worth realizing that:

- I haven't been able to test this as much as I would have wanted to
  (it's only been tested on tegra2 and omap5).

- I've created DT bindings when needed, updated existing ones, but I
  haven't created a binding for platforms that already used an
  undocumented one (imx6, I'm looking at you).

- I've relaxed quite a bit of the locking in the GIC code. I believe
  this is safe, but someone else should give it a long hard look.

- This actively *breaks* existing setups. Once you boot a new kernel
  with an old DT, suspend/resume *will* be broken. Old kernels on a
  new DT won't even boot! You've been warned. This really outline the
  necessity of actually describing the HW in device trees...

As for the patches, they are on top of 3.19-rc3.

I've pushed the code to:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
irq/die-gic-arch-extn-die-die-die


I've updated this branch with the changes requested in this review 
cycle. I'll give it a test run on Monday with the platforms I have 
around (mainly Tegra20 and OMAP4/5).


Unless anything major comes up, I'll post v3 with a view of getting 
this into 3.20.


Thanks,

M.
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Re: [PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 2015-01-09 17:40, Stefan Agner wrote:

Hi Marc,

On 2015-01-07 18:42, Marc Zyngier wrote:

IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/imx6qdl.dtsi  |   6 +-
 arch/arm/boot/dts/imx6sl.dtsi   |   5 +-
 arch/arm/boot/dts/imx6sx.dtsi   |   5 +-
 arch/arm/mach-imx/common.h  |   1 -
 arch/arm/mach-imx/gpc.c | 127 


 arch/arm/mach-imx/mach-imx6q.c  |   1 -
 arch/arm/mach-imx/mach-imx6sl.c |   1 -
 arch/arm/mach-imx/mach-imx6sx.c |   1 -
 8 files changed, 116 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi 
b/arch/arm/boot/dts/imx6qdl.dtsi

index 4fc03b7..c16d428 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};

clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;

dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+   interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};

@@ -694,8 +696,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;


#interrupt-cells = 3; is missing here.


Ah, nice catch!

I tested the patchset on a Colibri iMX6, but the module stopped 
booting

at some point. No error, no warn, but it looked like IRQ's are not
working:

[1.623939] platform sound: Driver imx-sgtl5000 requests probe
deferral
[1.630677] backlight supply power not found, using dummy 
regulator

[1.637067] pwm-backlight backlight: unable to request PWM, trying
legacy API
[1.644271] pwm-backlight backlight: unable to request legacy PWM
[1.650534] platform backlight: Driver pwm-backlight requests 
probe

deferral
[1.658080] platform 2028000.ssi: Driver fsl-ssi-dai requests 
probe

deferral
[1.665441] fec 2188000.ethernet eth0: Freescale FEC PHY driver
[Micrel KSZ8041] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[1.677157] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[freeze]

I figured out that the GPC code did not get called. After digging
through the parsing code, I found the reason: irq_find_host always 
opted

to intc because this was missing... So, interrupt-cells mandatory for
all interrupt-controller? Maybe we could add a warn somewhere..?


interrupt-cells has a default of 1, I believe. I suppose I could add a 
WARN_ON in the xlate/alloc functions...



With that in place, it worked fine:

Tested-by: Stefan Agner ste...@agner.ch


Thanks!




interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
 0 90 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
};

gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi 
b/arch/arm/boot/dts/imx6sl.dtsi

index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
  0x00a00100 0x100;
+   interrupt-parent = intc;
};

clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
-   interrupt-parent = intc;
+   interrupt-parent = gpc;
ranges;

ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+   interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+   interrupt

Re: [PATCH v2 06/21] ARM: tegra: remove old LIC support

[Marc Zyngier]

On 2015-01-08 11:29, Thierry Reding wrote:

On Wed, Jan 07, 2015 at 05:42:41PM +, Marc Zyngier wrote:
[...]

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c

[...]

 void __init tegra_init_irq(void)
 {
-   int i;
-   void __iomem *distbase;
-
-   if (of_find_matching_node(NULL, tegra_ictlr_match))
-   goto skip_extn_setup;
-
-   tegra_legacy_irq_syscore_init();
-
-   distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
-   num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR)  0x1f;
-
-   if (num_ictlrs  ARRAY_SIZE(ictlr_reg_base)) {
-		WARN(1, Too many (%d) interrupt controllers found. Maximum is 
%d.,

-   num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
-   num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
-   }
-
-   for (i = 0; i  num_ictlrs; i++) {
-   void __iomem *ictlr = ictlr_reg_base[i];
-   writel(~0, ictlr + ICTLR_CPU_IER_CLR);
-   writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
-   }
-
-   gic_arch_extn.irq_ack = tegra_ack;
-   gic_arch_extn.irq_eoi = tegra_eoi;
-   gic_arch_extn.irq_mask = tegra_mask;
-   gic_arch_extn.irq_unmask = tegra_unmask;
-   gic_arch_extn.irq_retrigger = tegra_retrigger;
-   gic_arch_extn.irq_set_wake = tegra_set_wake;
-   gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+   if (!of_find_matching_node(NULL, tegra_ictlr_match))
+   pr_warn(Outdated DT detected, suspend/resume will NOT work\n);


I'm not very happy about the ABI breakage here, but I also realize 
that
we need this change to properly describe the hardware. To make it 
more

obvious that people really should update their DTBs, maybe turn this
into a WARN()?


Sure, done.


-skip_extn_setup:
tegra114_gic_cpu_pm_registration();


I'm not intimately familiar with the GIC, but is this really SoC
specific? Doesn't anybody else need this? Comparing to the GIC spec 
the
write of 0x1e0 to the GIC_CPU_CTRL register (which I assume 
corresponds
to GICC_CTLR in the spec), this simply disables the IRQ and FIQ 
bypass

signals for both group 0 and group 1.


This seems to be a Tegra special, at least in mainline. But yes, I'd 
very much like to be able to remove this from platform code and make it 
part of the GIC driver if we can.


Something for a subsequent patch series, I guess.

Thanks,

M.
--
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Re: [PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains

[Marc Zyngier]

On 2015-01-08 16:44, Nishanth Menon wrote:

On 17:42-20150107, Marc Zyngier wrote:

OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.

On a platform with this patch applied, the system looks like
this:

root@bacon-fat:~# cat /proc/interrupts
CPU0   CPU1
 16:  0  0 WUGEN  37  gp_timer
 19: 233799 155916   GIC  27  arch_timer
 23:  0  0 WUGEN   9  l3-dbg-irq
 24:  1  0 WUGEN  10  l3-app-irq
 27:282  0 WUGEN  13  omap-dma-engine
 44:  0  0  4ae1.gpio  13  DMA
294:  0  0 WUGEN  20  gpmc
297:506  0 WUGEN  56  4807.i2c
298:  0  0 WUGEN  57  48072000.i2c
299:  0  0 WUGEN  61  4806.i2c
300:  0  0 WUGEN  62  4807a000.i2c
301:  8  0 WUGEN  60  4807c000.i2c
308:   2439  0 WUGEN  74  OMAP UART2
312:362  0 WUGEN  83  mmc2
313:502  0 WUGEN  86  mmc0
314: 13  0 WUGEN  94  mmc1
350:  0  0  PRCM  pinctrl, pinctrl
406:   35155709  0   GIC 109  ehci_hcd:usb1
407:  0  0 WUGEN   7  palmas
409:  0  0 WUGEN 119  twl6040
410:  0  0   twl6040   5  twl6040_irq_ready
411:  0  0   twl6040   0  twl6040_irq_th
IPI0:  0  1  CPU wakeup interrupts
IPI1:  0  0  Timer broadcast interrupts
IPI2:  95334 902334  Rescheduling interrupts
IPI3:  0  0  Function call interrupts
IPI4:479648  Single function call interrupts
IPI5:  0  0  CPU stop interrupts
IPI6:  0  0  IRQ work interrupts
IPI7:  0  0  completion interrupts
Err:  0

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/boot/dts/am4372.dtsi |  11 ++-
 arch/arm/boot/dts/dra7.dtsi   |  12 ++-
 arch/arm/boot/dts/dra72x.dtsi |   2 +-
 arch/arm/boot/dts/dra74x.dtsi |   2 +-
 arch/arm/boot/dts/omap4-duovero.dtsi  |   2 -
 arch/arm/boot/dts/omap4-panda-common.dtsi |   8 +-
 arch/arm/boot/dts/omap4-sdp.dts   |   8 +-
 arch/arm/boot/dts/omap4-var-som-om44.dtsi |   2 -
 arch/arm/boot/dts/omap4.dtsi  |  18 -
 arch/arm/boot/dts/omap5-cm-t54.dts|   1 -
 arch/arm/boot/dts/omap5-uevm.dts  |   2 -
 arch/arm/boot/dts/omap5.dtsi  |  24 --
 arch/arm/mach-omap2/omap-wakeupgen.c  | 125 
+++---

 arch/arm/mach-omap2/omap-wakeupgen.h  |   1 -
 arch/arm/mach-omap2/omap4-common.c|   1 -
 15 files changed, 154 insertions(+), 65 deletions(-)


we may need the following changes as well:

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4cf9f89..69f2313a49d1 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;

diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc90b26a..029badefad3d 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
-   interrupt-parent = gic;
interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 662261d6b2ca..2d26bc11bad6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -333,7 +333,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
-   interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..c2241c2e5d9d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6

[PATCH v2 06/21] ARM: tegra: remove old LIC support

[Marc Zyngier]

Now that all DTs have been updated, entierely drop support for
the non-DT code.

This is likely to break platforms that do not update their DT,
so print a warning at boot time.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 arch/arm/mach-tegra/iomap.h |  15 
 arch/arm/mach-tegra/irq.c   | 201 +---
 arch/arm/mach-tegra/irq.h   |   6 --
 3 files changed, 2 insertions(+), 220 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
 #define TEGRA_ARM_INT_DIST_BASE0x50041000
 #define TEGRA_ARM_INT_DIST_SIZESZ_4K
 
-#define TEGRA_PRIMARY_ICTLR_BASE   0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE   SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE  0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE  SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE   0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE   SZ_64
-
 #define TEGRA_TMR1_BASE0x60005000
 #define TEGRA_TMR1_SIZESZ_8
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index b37141d..a1befd3 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
 #include board.h
 #include iomap.h
 
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR  0x14
-#define ICTLR_CPU_IEP_FIR_SET  0x18
-#define ICTLR_CPU_IEP_FIR_CLR  0x1c
-
-#define ICTLR_CPU_IER  0x20
-#define ICTLR_CPU_IER_SET  0x24
-#define ICTLR_CPU_IER_CLR  0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER  0x30
-#define ICTLR_COP_IER_SET  0x34
-#define ICTLR_COP_IER_CLR  0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS   5
-
 #define SGI_MASK 0x
 
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
-   IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-   IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
 #ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
 static void __iomem *tegra_gic_cpu_base;
 #endif
 
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
 }
 
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
-   void __iomem *base;
-   u32 mask;
-
-   BUG_ON(irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
-   base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
-   __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
-   if (d-hwirq  FIRST_LEGACY_IRQ)
-   return 0;
-
-   tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
-   return 1;
-}
-
 #ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
-   u32 irq = d-hwirq;
-   u32 index, mask;
-
-   if (irq  FIRST_LEGACY_IRQ ||
-   irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
-   return -EINVAL;
-
-   index = ((irq - FIRST_LEGACY_IRQ) / 32);
-   mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-   if (enable)
-   ictlr_wake_mask[index] |= mask;
-   else
-   ictlr_wake_mask[index] = ~mask;
-
-   return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
-   unsigned long flags;
-   int i;
-
-   local_irq_save(flags);
-   for (i = 0; i  num_ictlrs; i++) {
-   void __iomem *ictlr = ictlr_reg_base[i];
-   /* Save interrupt state */
-   cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
-   cpu_iep[i

[PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller

[Marc Zyngier]

Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.

The stacked irq domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.

Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
 drivers/irqchip/Makefile|   1 +
 drivers/irqchip/irq-tegra.c | 335 
 2 files changed, 336 insertions(+)
 create mode 100644 drivers/irqchip/irq-tegra.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
 obj-$(CONFIG_DW_APB_ICTL)  += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..b4fc2e3
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,335 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR  0x14
+#define ICTLR_CPU_IEP_FIR_SET  0x18
+#define ICTLR_CPU_IEP_FIR_CLR  0x1c
+
+#define ICTLR_CPU_IER  0x20
+#define ICTLR_CPU_IER_SET  0x24
+#define ICTLR_CPU_IER_CLR  0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER  0x30
+#define ICTLR_COP_IER_SET  0x34
+#define ICTLR_COP_IER_CLR  0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS   5
+
+static int num_ictlrs;
+
+struct tegra_ictlr_info {
+   void __iomem *ictlr_reg_base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+   u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+   u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+   u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *tegra_ictlr_info;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long 
reg)
+{
+   void __iomem *base = d-chip_data;
+   u32 mask;
+
+   mask = BIT(d-hwirq % 32);
+   writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+   irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+   irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+   irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+   tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+   return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+   u32 irq = d-hwirq;
+   u32 index, mask;
+
+   index = (irq / 32);
+   mask = BIT(irq % 32);
+   if (enable)
+   tegra_ictlr_info-ictlr_wake_mask[index] |= mask;
+   else
+   tegra_ictlr_info-ictlr_wake_mask[index] = ~mask;
+
+   /*
+* Do *not* call into the parent, as the GIC doesn't have any
+* wake-up facility...
+*/
+   return 0;
+}
+
+static int tegra_ictlr_suspend(void)
+{
+   unsigned long flags;
+   int i;
+
+   local_irq_save(flags);
+   for (i = 0; i  num_ictlrs; i++) {
+   void __iomem *ictlr = tegra_ictlr_info-ictlr_reg_base[i];
+   /* Save interrupt state */
+   tegra_ictlr_info-cpu_ier[i] = readl_relaxed