to various interconnect violations. The issue is observed on OMAP5.
This patch tries to fix the issue by ensuring that all regions
are marked as a client domain so that XN attribute is effective.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
following transition modes ...
NO_SLEEP (0x0) - A clock domain sleep transition is never initiated,
irrespective
Benoit,
On Wednesday 09 May 2012 04:28 PM, Cousson, Benoit wrote:
Hi Kevin and Jon,
On 5/8/2012 11:22 PM, Kevin Hilman wrote:
Jon Hunterjon-hun...@ti.com writes:
Hi Benoit,
On 05/08/2012 06:01 AM, Cousson, Benoit wrote:
[...]
P.S. Please note there is also already a different fix in
with me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
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On Thursday 10 May 2012 02:23 PM, Russell King - ARM Linux wrote:
On Thu, May 10, 2012 at 12:41:35PM +0530, Santosh Shilimkar wrote:
Are you planning to merge below patch as is or split
the patch like 1) Refactoring 2) ARMv7 fix
I don't see any point in splitting this up, especially
On Thursday 10 May 2012 05:18 PM, Roger Quadros wrote:
On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
On Thu, May 10, 2012 at 5:06 PM, Roger Quadros rog...@ti.com wrote:
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
OMAP4 and OMAP5 share
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX and
r2pX. The Control Register secure banked version is now composed
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX
Tero,
On Monday 14 May 2012 03:33 PM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX and
r2pX. The Control Register secure banked version is now composed of 2
bits:
bit 0 == Secure Enable
bit
+ Tarun for any comments
On Wednesday 16 May 2012 05:05 AM, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
In order to migrate the dmtimer driver to support device-tree I found that it
was first necessary to clean-up the timer platform data. The goal of this
series is to simplify the
Jean,
On Tuesday 08 May 2012 02:10 PM, Jean Pihet wrote:
Paul,
On Mon, May 7, 2012 at 11:28 AM, Paul Walmsley p...@pwsan.com wrote:
Hi
On Wed, 18 Apr 2012, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
Introduce functional (or logical) states for power domains and the
, and
set the irq to allow the clockevent core to determine the affinity of the
timer.
Signed-off-by: Colin Cross ccr...@android.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/timer.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git
synchronization for coupled idle states
Santosh Shilimkar (3):
ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
ARM: OMAP4: CPUidle: Use coupled cpuidle states to implement SMP
cpuidle.
ARM: OMAP4: CPUidle: Open broadcast clock-event device.
arch/arm/mach-omap2/Kconfig
mode was also broken. This change fixes both the periodic/oneshot broadcast
modes.
Discussion thread :
https://lkml.org/lkml/2012/4/9/13
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c | 13 +
1 files changed, 13 insertions(+), 0
the coupled
state enter method can return.
In addition, cpuidle_coupled_parallel_barrier() is used to ensure the
clearing of the 'done' flag is synchronized on all CPUs.
Signed-off-by: Kevin Hilman khil...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2
Cross on the suggestions/fixes
on the intermediate version of this patch.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2/cpuidle44xx.c | 112 ++---
2 files changed, 67 insertions(+), 46
Jean,
On Monday 21 May 2012 07:55 PM, Shilimkar, Santosh wrote:
Jean,
On Mon, May 21, 2012 at 7:23 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
Hi Santosh,
On Thu, May 17, 2012 at 12:04 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
[...]
What do you think?
I like the idea
Tony,
Here is the EMIF driver DT support which was kept on hold for the driver
to get merged. The series has been already reviewed on the list.
This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and
-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/lpddr2/lpddr2
-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4
Cousson b-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../bindings/memory
-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/memory/emif.c | 285 -
1 file changed, 284 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/emif.c b/drivers/memory
Tony,
Here is the EMIF driver DT support which was kept on hold for the driver
to get merged. The series has been already reviewed on the list.
v4:
Fixed the DT config flag and rebased against 3.5-rc4
v3:
Rebased against the 3.5-rc2
This series adds device tree support for TI EMIF SDRAM
Cousson b-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../bindings/memory
-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/lpddr2/lpddr2
-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4
-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/memory/emif.c | 291 -
1 file changed, 290 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
index 33a4396..101997b 100644
--- a/drivers
On 3/31/2011 11:02 PM, Tony Lindgren wrote:
* Santosh Shilimkarsantosh.shilim...@ti.com [110331 01:14]:
On 3/30/2011 11:52 PM, Tony Lindgren wrote:
What it does not have is the code to dedicate gpt1 for PM
code, which can be done later once all the other dmtimer
changes are done.
Which not
go through L2X0 write
buffer.
Also since a DSB does not guarantee that the device state has
been changed, a read back from the device is introduced wherever
necessary.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea
Kevin,
On 4/1/2011 3:39 AM, Kevin Hilman wrote:
Tony Lindgrent...@atomide.com writes:
This removes the support for setting the wake-up timer for debugging.
Later on we can reserve gptimer1 for PM code only and have similar
functionality.
Signed-off-by: Tony Lindgrent...@atomide.com
While
On 4/2/2011 11:40 AM, Colin Cross wrote:
On Mon, Mar 28, 2011 at 2:22 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible
for generating wakeup event from the incoming interrupts and enable bits.
The WakeupGen
On 4/4/2011 1:55 PM, Russell King - ARM Linux wrote:
On Mon, Apr 04, 2011 at 01:50:35PM +0530, Santosh Shilimkar wrote:
On 4/3/2011 7:18 PM, Russell King - ARM Linux wrote:
On Sun, Apr 03, 2011 at 04:23:41PM +0530, Santosh Shilimkar wrote:
If you plan to commit this change then I can move
On 4/4/2011 2:42 PM, Russell King - ARM Linux wrote:
On Mon, Apr 04, 2011 at 02:34:56PM +0530, Santosh Shilimkar wrote:
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a3f50b3..7857146 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -166,7
The serial*_data should have been marked as __initdata as per
it's usage in the board files. Fix the same to remove the
section mismatch warnings caused by it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/board-3430sdp.c|6 +++---
arch/arm/mach-omap2
On 4/4/2011 8:59 PM, Catalin Marinas wrote:
On Fri, 2011-04-01 at 10:32 +0100, Santosh Shilimkar wrote:
The GIC register accesses today make use of readl()/writel()
which prove to be very expensive when used along with mandatory
barriers. This mandatory barriers also introduces an un-necessary
On 4/5/2011 1:38 AM, Linus Walleij wrote:
2011/4/4 Marc Zyngiermarc.zyng...@arm.com:
On Mon, 2011-04-04 at 14:31 +0100, Russell King - ARM Linux wrote:
If ARM are going to architect a set of timers into the hardware, let's
make sure that all such hardware has them so we can dig ourselves out
On 4/5/2011 6:14 PM, Rajendra Nayak wrote:
Add a clockdomain api to check if hardware supervised
idle transitions are enabled on a clockdomain.
Signed-off-by: Rajendra Nayakrna...@ti.com
---
arch/arm/mach-omap2/clockdomain.c | 21 +
arch/arm/mach-omap2/clockdomain.h |
On 4/6/2011 3:52 AM, Linus Walleij wrote:
2011/4/5 Santosh Shilimkarsantosh.shilim...@ti.com:
The only issue I see is the clock-events implemented using
local timers capabilities in low power modes. The local timers
won't be able wakeup CPU from DORMANT or OFF state and hence
you will need an
On 4/6/2011 3:46 AM, Linus Walleij wrote:
2011/4/5 Santosh Shilimkarsantosh.shilim...@ti.com:
[Me]
(And third it will also eventually need to hook into the timer-based
delay framework that I think Nokia is working on to be really
useful, else all delays become unpredictable.)
Do you mean
On 4/7/2011 1:35 PM, Felipe Balbi wrote:
Those were very simple to fix and while we should
be putting effort on code consolidation, having
a noisy compilation is very painful and makes it
more difficult to see newer warnings introduced
by re-factoring other code.
Signed-off-by: Felipe
for finding this.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On 4/16/2011 9:21 PM, Tarun Kanti DebBarma wrote:
In driver probe use sys_timer_reserved to identify which all timers
have already been used for clocksource and clockevent. Mark all those
timers as reserved so that no one else can use them.
Signed-off-by: Tarun Kanti DebBarmatarun.ka...@ti.com
On 4/21/2011 1:12 AM, Paul Walmsley wrote:
Hi Rajendra, Santosh,
just FYI I just observed this happening without the clockdomain patch, and
tracked this down. It seems that there is an intermittent
problem with the OMAP L3 bus code. On the 35xx BeagleBoard here, it
occasionally hangs after
Tony,
On 4/4/2011 3:17 PM, Santosh Shilimkar wrote:
On 4/4/2011 2:42 PM, Russell King - ARM Linux wrote:
[]
Thanks for pointing out this. I see Will's commit on this
one 29a38193
Here is the updated patch as you suggested.
Are you considering this patch and another one [1
go through L2X0 write
buffer.
A DSB before writel_relaxed() in gic_raise_softirq() is added to be
compliant with the Barrier Litmus document - the mailbox scenario.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea
.
Though above output would be bit miss leading, this
series removes the duplicate code from platforms and
consolidate it at one place.
FWIW, you can add my
Reviewedd-by: Santosh Shilimkar santosh.shilim...@ti.com
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
Tarun,
On 4/25/2011 3:11 PM, DebBarma, Tarun Kanti wrote:
In driver probe use sys_timer_reserved to identify which all timers
have already been used for clocksource and clockevent. Mark all those
timers as reserved so that no one else can use them.
Signed-off-by: Tarun Kanti
On 4/16/2011 9:20 PM, Tarun Kanti DebBarma wrote:
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver.
In addition, capability attribute of each of the
Tarun,
On 4/16/2011 9:21 PM, Tarun Kanti DebBarma wrote:
Make plat-omap/dmtimer.c a normal driver. It is moved to drivers/misc
as timer-omap.c and the corresponding header file has been moved to
include/linux as timer-omap.h. Files which included plat/dmtimer.h
are changed to include
On 4/29/2011 2:56 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
The cpuidle states settings can be overriden by some board-
specific settings, by calling omap3_pm_init_cpuidle.
Remove the 3430SDP specific states settings registration
since the figures are identical to the
Jean,
On 4/29/2011 2:56 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
The current implementation defines an internal structure and a
C-states array. Using those structures is redundant to the
structs used by the cpuidle framework.
This patch provides a clean-up of the
On 4/29/2011 2:56 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
The achievable power modes of the power domains in cpuidle
depends on the system wide 'enable_off_mode' knob in debugfs.
Upon changing enable_off_mode, do not change the C-states
'valid' field but instead
On 4/30/2011 9:53 PM, Sebastian Reichel wrote:
Hi,
I'm currently trying to get a mainline based kernel running on my pandaboard.
The problem is, that it's crashing very early during the init phase because of
undefined instruction exceptions:
[1.867980] udevd (56): undefined instruction:
On 4/30/2011 10:14 PM, Måns Rullgård wrote:
Sebastian Reichels...@debian.org writes:
[..]
32ecc: 9cd0ldr r4, [sp, #832] ; 0x340
32ece: fffe e92d vtbl.8 d30, {d14-d15}, d29
00032ed0_IO_vfprintf:
32ed0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp,
On 5/3/2011 3:41 PM, Catalin Marinas wrote:
[...]
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index e9c2ff8..80b3d3c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -89,7 +89,8 @@ static void gic_mask_irq(struct irq_data *d)
u32 mask = 1 (d-irq % 32);
On 5/3/2011 3:44 PM, Santosh Shilimkar wrote:
On 5/3/2011 3:41 PM, Catalin Marinas wrote:
[...]
Otherwise the patch looks fine (I'll add my ack after you fix the above).
Thanks. Will add above comment, drop the readl and repost with your ack.
Same will push it the patch system
Below
On 5/4/2011 10:34 PM, Will Deacon wrote:
Hi Santosh,
On Wed, 2011-05-04 at 12:02 +0100, Santosh Shilimkar wrote:
Will,
Can you queue this patch part of your series please?
Yes, providing that Russell is happy to pull the IRQ stuff (fasteoi,
Tegra changes and this) from me.
Thanks.
Regards
On 5/11/2011 6:11 AM, Menon, Nishanth wrote:
On Mon, Mar 14, 2011 at 06:38, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On OMAP SMP configuartion, both processors share the voltage
and clock. So both CPUs needs to be scaled together and hence
needs software co-ordination.
Signed-off
Russell,
On 5/12/2011 11:15 PM, Russell King - ARM Linux wrote:
On Fri, Apr 15, 2011 at 02:06:07PM +0100, Russell King - ARM Linux wrote:
This is work in progress.
Tried this patch on OMAP and found couple of issues.
1. Compilation break. Below is the fix for the same.
diff --git
Jean,
On 5/18/2011 11:02 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
Provide omap_pm_tick_nohz_get_sleep_length_us so that the code
from the OMAP PM modules can use it.
Signed-off-by: Jean Pihetj-pi...@ti.com
---
arch/arm/mach-omap2/pm-debug.c |7 ---
On 5/18/2011 11:02 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
Provide the the assembly function v7_flush_dcache_all to the
OMAP3 PM module, under CONFIG_CPU_V7.
v7_flush_dcache_all is used by the low level sleep code.
Signed-off-by: Jean Pihetj-pi...@ti.com
---
On 5/18/2011 11:02 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihetj-pi...@ti.com
Addition of EXPORT_SYMBOL for functions and variables used by
the code in PM modules.
Signed-off-by: Jean Pihetj-pi...@ti.com
---
arch/arm/kernel/setup.c|1 +
arch/arm/kernel/smp_tlb.c
Tod,
On 5/25/2011 8:20 AM, Todd Poynor wrote:
* Move variable declarations from header file and make these static
(the entire header file should probably go away).
Infact the intial version posted on the list had all these structures
in C file. After some comments on the list we moved them
On 5/26/2011 6:30 PM, Silesh C V wrote:
Get rid of the following and 8 other similar section mismatch
warnings
I send this [1] patch a month back. It's still not considered
though even after reminder.
Regards
Santosh
[1] https://patchwork.kernel.org/patch/684831/
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On 5/26/2011 11:40 PM, Kevin Hilman wrote:
So here's a dumb question, being rather ignorant of CPUfreq on SMP.
Should we be running a CPUfreq instance on both CPUs when they cannot be
scaled independently?
What is being scaled here is actually the cluster (the MPU SS via
dpll_mpu_ck), not an
On 5/27/2011 4:32 AM, Kevin Hilman wrote:
Move suspend wakeup timer from suspend path to be triggered based
on clockevent suspend path.
When gptimers are eventually converted to be a driver, the wakeup
timer feature can be made to be a driver-specific feature using the
driver's suspend method.
On 5/27/2011 11:37 AM, Menon, Nishanth wrote:
On Thu, May 26, 2011 at 22:06, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On 5/26/2011 11:40 PM, Kevin Hilman wrote:
So here's a dumb question, being rather ignorant of CPUfreq on SMP.
Should we be running a CPUfreq instance on both CPUs
On 5/27/2011 8:13 PM, Cousson, Benoit wrote:
On 5/27/2011 2:46 PM, Valkeinen, Tomi wrote:
On Fri, 2011-05-27 at 14:38 +0200, Cousson, Benoit wrote:
Hi Tomi,
On 5/27/2011 9:38 AM, Valkeinen, Tomi wrote:
Add omap_device_reset() function which can be used to reset the hwmods
associated with the
On 5/27/2011 8:30 PM, Cousson, Benoit wrote:
On 5/27/2011 4:51 PM, Shilimkar, Santosh wrote:
On 5/27/2011 8:13 PM, Cousson, Benoit wrote:
On 5/27/2011 2:46 PM, Valkeinen, Tomi wrote:
On Fri, 2011-05-27 at 14:38 +0200, Cousson, Benoit wrote:
Hi Tomi,
On 5/27/2011 9:38 AM, Valkeinen, Tomi
Todd,
On 5/28/2011 8:54 AM, Todd Poynor wrote:
* Make variables static.
* Define L3 TARG instance offsets, and read/write STDERRLOG registers
relative to those offsets, rather than defining STDERRLOG_MAIN
instance offsets and accessing other registers via offsets from
that register.
'.
If runtime configuration of this is needed, then adding a debugfs
entry for the ARM-generic hlt/nohlt interface should be added.
Signed-off-by: Kevin Hilmankhil...@ti.com
This makes it easy for future OMAP PM code as well.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Regards
Santosh
On 5/27/2011 4:32 AM, Kevin Hilman wrote:
Signed-off-by: Kevin Hilmankhil...@ti.com
Do you plan to keep wroking the patch which dumps registers
before and after WFI ?
Ofcourse this patch is in your pm-debug branch.
For this change
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
and indeed it doesn't scale for OMAP4.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Kevin,
On 5/27/2011 10:48 AM, Santosh Shilimkar wrote:
On 5/27/2011 4:32 AM, Kevin Hilman wrote:
Move suspend wakeup timer from suspend path to be triggered based
on clockevent suspend path.
When gptimers are eventually converted to be a driver, the wakeup
timer feature can be made
On 5/30/2011 1:38 PM, Jean Pihet wrote:
On Mon, May 30, 2011 at 9:21 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Kevin,
On 5/27/2011 10:48 AM, Santosh Shilimkar wrote:
On 5/27/2011 4:32 AM, Kevin Hilman wrote:
Move suspend wakeup timer from suspend path to be triggered based
The commit '99aa18278e' removed the boot messege for OMAP3. Do the same
for OMAP2 and OMAP4 since it's really just noise in the boot log
and PM init is always called.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
Generated against mainline v3.0-rc1
While trying out V3.0-rc1, I noticed couple of regressions. Am
posting this in case anybody come across same issues.
1.OMAP MMC code keep throwing Pbias Voltage is not same as LDO error
continuously.
Balaji is planning post right fix for the same, but just
in case you get around this issue,
Tony,
On 5/30/2011 1:35 PM, Tony Lindgren wrote:
* Kevin Hilmankhil...@ti.com [110527 14:24]:
FYI... I just found this, but won't be able to look into it until next
week, so if anyone needs a weekend debug project...
Using Tony's for-next branch, I'm able to boot an omap2plus_defconfig (+
On 5/30/2011 7:06 PM, Sergei Shtylyov wrote:
Hello.
Santosh Shilimkar wrote:
The commit '99aa18278e' removed the boot messege for OMAP3. Do the same
Please specify that commit's summary in parens -- for the human readers.
Oh, and you don't need quotes around commit ID too.
Yes I missed
On 5/31/2011 12:16 PM, T Krishnamoorthy, Balaji wrote:
On Mon, May 30, 2011 at 6:03 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
While trying out V3.0-rc1, I noticed couple of regressions. Am
posting this in case anybody come across same issues.
1.OMAP MMC code keep throwing Pbias
HIGMEM support is kernel is quite mature now and we have boards
like ZOOM, PANDA, SDP where 1 GB memories are installed.
Enable HIGMEM to make use of the additional memory.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
This won't boards which doesn't have excess memory. Tested
Fixing the change log ...
On 6/2/2011 5:36 PM, Santosh Shilimkar wrote:
HIGMEM support is kernel is quite mature now and we have boards
HIGMEM support in kernel is quite mature now and we have boards
like ZOOM, PANDA, SDP where 1 GB memories are installed.
Enable HIGMEM to make use
On 6/2/2011 6:51 PM, Premi, Sanjeev wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of
Shilimkar, Santosh
Sent: Thursday, June 02, 2011 5:36 PM
To: linux-omap@vger.kernel.org
Cc: Shilimkar, Santosh
Subject: [PATCH RFC]
the check accordingly.
Thanks for Nishant Menon n...@ti.com for reporting it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reported-by: Nishanth Menon n...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
There were some question of making the variable atomic etc
in an internal
Missed Kevin in cc. :(
Sorry about that.
Original Message
Subject: [PATCH] OMAP2+: CPUfreq: Allow the CPU scaling when secondary
CPUs are offline.
Date: Thu, 2 Jun 2011 20:21:10 +0530
From: Santosh Shilimkar santosh.shilim...@ti.com
To: linux-omap@vger.kernel.org
CC: Santosh
On 6/3/2011 4:40 AM, Kevin Hilman wrote:
Santosh Shilimkarsantosh.shilim...@ti.com writes:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This will break DVFS when secondary
CPUs are offlined.
The intention of that check was just avoid CPU frequency
On 6/3/2011 8:14 AM, Menon, Nishanth wrote:
On Thu, Jun 2, 2011 at 09:51, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This will break DVFS when secondary
CPUs are offlined.
The intention
On 6/3/2011 11:56 AM, Santosh Shilimkar wrote:
On 6/3/2011 4:40 AM, Kevin Hilman wrote:
Santosh Shilimkarsantosh.shilim...@ti.com writes:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This will break DVFS when secondary
CPUs are offlined
Nishant,
On 6/3/2011 12:09 PM, Santosh Shilimkar wrote:
On 6/3/2011 8:14 AM, Menon, Nishanth wrote:
On Thu, Jun 2, 2011 at 09:51, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This will break DVFS when
On 6/3/2011 2:01 PM, Santosh Shilimkar wrote:
On 6/3/2011 11:56 AM, Santosh Shilimkar wrote:
On 6/3/2011 4:40 AM, Kevin Hilman wrote:
[...]
Can do that as well.
After re-looking at this, seems not straight forward. This check is
not for cpufreqdriver_init time but per-CPU init functions
().
Thanks for Nishant Menon n...@ti.com for reporting issue
with hot-plug and Kevin Hilman khil...@ti.com for his
comment on excessive check in target().
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reported-by: Nishanth Menon n...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
Shilimkarsantosh.shilim...@ti.com
Signed-off-by: Oleg Drokingr...@linuxhacker.ru
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Signed-off-by: Colin Crossccr...@android.com
Looks good. This needs to be fixed on top of the clean-up
branch where GPIO movemnt to driver/gpio/* happening.
For this change,
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On 6/7/2011 7:35 AM, Nishanth Menon wrote:
Since we do module_init, cpufreq initializes before power late_init
where many of the required data structures are registered. Move
cpufreq init to late_initcall instead. Further CONFIG_CPU_FREQ
on which the build depends is bool and does'nt support
...@google.com
Looks good to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap2plus-cpufreq.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap2plus-cpufreq.c
b/arch/arm/mach-omap2/omap2plus-cpufreq.c
index
disabling SMP
Signed-off-by: Miguel Vadillovadi...@ti.com
---
arch/arm/mach-omap2/include/mach/omap4-common.h |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h
b
it's ready for merge.
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Kevin Hilman (4):
OMAP3: PM debug: remove sleep_while_idle feature
OMAP2: PM debug: remove register dumping
OMAP3: PM debug: remove register dumping
OMAP2: PM
On 6/13/2011 8:05 PM, Tony Lindgren wrote:
* Santosh Shilimkarsantosh.shilim...@ti.com [110612 23:32]:
On 6/13/2011 11:55 AM, Vadillo, Miguel wrote:
Function omap_smc2 is undeclared when disabling SMP
Looks like this won't apply to current mainline kernel, care
to check if it's still
On 6/13/2011 8:19 PM, Vadillo, Miguel wrote:
Yes, sorry about this mistake, the patch its just for an internal tree
and I wasn't careful enough to check the mainline. Sorry about the
noise.
Thanks for confirming it.
Regards
Santosh
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!
other info that might help us debug this:
rcu_scheduler_active = 1, debug_locks = 1
no locks held by swapper/1.
...
---
Fix the same by protecting it with rcu_read lock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rafael J
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