On Monday 10 October 2011 11:31 PM, Kevin Hilman wrote:
> Hi Santosh,
>
> Santosh Shilimkar writes:
>
>> The series adds OMAP4 MPUSS (MPU SubSystem) power management support for
>> suspend (S2R), CPU hotplug and CPUidle.
>
> There are a few more compile error
On Tuesday 08 November 2011 04:16 PM, Cousson, Benoit wrote:
> Hi Govind,
>
> On 11/8/2011 7:28 AM, Govindraj.R wrote:
>> Patch to fix below compilation error on latest mainline commit
>> b32fc0a0629bf5894b35f33554c118aacfd0d1e2 with omap2plus_defconfig.
>>
>> arch/arm/mach-omap2/omap_l3_noc.c:250
On 6/26/2011 11:53 PM, Jean Pihet wrote:
Hi Santosh,
On Sat, Jun 25, 2011 at 3:23 PM, Santosh Shilimkar
wrote:
On 6/24/2011 7:38 AM, jean.pi...@newoldbits.com wrote:
From: Jean Pihet
Since cpuidle is a CPU centric framework it decides the MPU
next power state based on the MPU exit_latency
On 6/28/2011 3:29 PM, Colin Cross wrote:
On Fri, Jun 24, 2011 at 6:53 AM, Sanjeev Premi wrote:
+#ifdef CONFIG_SMP
+ /* Adjust jiffies before transition */
+ for_each_cpu(i, policy->cpus) {
+ unsigned long lpj = per_cpu(cpu_data, i).loops_per_jiffy;
+
+
On 6/28/2011 3:53 PM, Colin Cross wrote:
On Tue, Jun 28, 2011 at 3:45 PM, Santosh Shilimkar
mailto:santosh.shilim...@ti.com>> wrote:
[]
Can't this rewrite the loops_per_jiffy for the other CPU while it is
in a udelay? If it has already calculated the numb
On 6/28/2011 4:00 PM, Santosh Shilimkar wrote:
On 6/28/2011 3:53 PM, Colin Cross wrote:
On Tue, Jun 28, 2011 at 3:45 PM, Santosh Shilimkar
mailto:santosh.shilim...@ti.com>> wrote:
[]
Can't this rewrite the loops_per_jiffy for the other CPU while it is
in a udelay? If it
On 6/28/2011 4:03 PM, Russell King - ARM Linux wrote:
On Tue, Jun 28, 2011 at 03:45:22PM -0700, Santosh Shilimkar wrote:
The udelay code doesn't use the per-cpu lpj variable. It uses the global
lpj. Secondly the calibration of no. of loops to be done is
precalculateed so overwrite shou
+ Benoit
On 7/5/2011 5:19 AM, Jan Weitzel wrote:
The gpmc clock on omap44xx is called gpmc_ick not gpmc_ck in
clock44xx_data.c
Signed-off-by: Jan Weitzel
This happened after renaming the clock-nodes some time back.
Looks good to me as a fix though in long run GPMC should be
moved to hwmod to a
On 7/5/2011 11:35 AM, Kevin Hilman wrote:
Santosh Shilimkar writes:
+ Benoit
On 7/5/2011 5:19 AM, Jan Weitzel wrote:
The gpmc clock on omap44xx is called gpmc_ick not gpmc_ck in
clock44xx_data.c
Signed-off-by: Jan Weitzel
This happened after renaming the clock-nodes some time back.
Looks
+ Tomi,
On 7/9/2011 3:25 PM, Paul Walmsley wrote:
Hi
On Mon, 9 May 2011, sricharan wrote:
Paul Walmsley reported a kernel hang issue with beagle board
during boot. This is an intermittent bug and the execution was
found to be stuck at the l3 interrupt handler.
This was due to a dss initiator
Felipe,
On 7/10/2011 2:52 AM, Felipe Balbi wrote:
From: Felipe Balbi
Date: Sun, 10 Jul 2011 12:22:20 +0300
Subject: [PATCH] usb: musb: fix build breakage
Organization: Texas Instruments\n
This patch fixes the compilation brekage which
commits 208466dc ("usb: otg:OMAP4430: Powerdown
the internal
->cpus mask would contain only
the boot CPU.
Signed-off-by: Santosh Shilimkar
[santosh.shilim...@ti.com: re-based against omap cpufreq
upstream branch and fixed notifiers]
Signed-off-by: Russell King
Cc: Kevin Hilman
---
Patch is outcome of below discussion.
http://www.mail-archive.com/linux-o
On 7/11/2011 4:21 PM, Kevin Hilman wrote:
Fix boot crash in watchdog driver when runtime PM is disabled.
When runtime PM is disabled, devices should be left enabled so that
all device accesses in drivers will succeed even though the runtime PM
get/put calls are noops.
This is already the case f
From: Rajendra Nayak
Program all powerdomain target state as ON; This is to
prevent domains from hitting low power states (if bootloader
has target states set to something other than ON) and potentially
even losing context while PM is not fully initilized.
The PM late init code can then program t
from OSWR to ON.
This issue was reported and investigated by Patrick Titiano
Signed-off-by: Santosh Shilimkar
Signed-off-by: Rajendra Nayak
Reported-by: Patrick Titiano
Cc: Kevin Hilman
Cc: Benoit Cousson
Cc: Paul Walmsley
---
arch/arm/mach-omap2/clockdomain.c |7 ++-
1 files changed
On 7/15/2011 12:54 AM, Paul Walmsley wrote:
On Wed, 13 Jul 2011, Santosh Shilimkar wrote:
From: Rajendra Nayak
Program all powerdomain target state as ON; This is to
prevent domains from hitting low power states (if bootloader
has target states set to something other than ON) and potentially
Hi Paul,
On 7/15/2011 1:03 AM, Paul Walmsley wrote:
cc'ing Patrick
Hi Rajendra, Santosh,
some comments here:
On Wed, 13 Jul 2011, Santosh Shilimkar wrote:
While using clockdomain force wakeup method, not waiting for powerdomain
to be effectively ON may end up locking the clockdomai
Shubro,
On 7/21/2011 4:39 PM, Shubhrajyoti D wrote:
Under some conditions the driver may want to do a reset
of the device. Adding a reset field to the platform
data.
Signed-off-by: Shubhrajyoti D
---
include/linux/i2c-omap.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff -
On 7/21/2011 4:39 PM, Shubhrajyoti D wrote:
Under some error conditions the i2c driver may do a reset
adding support in the platform.
Signed-off-by: Shubhrajyoti D
---
As commented on 1/5, this one should be folded
with 1/5 unless and until you have some valid reason.
Regards
Santosh
--
To un
On 7/21/2011 4:39 PM, Shubhrajyoti D wrote:
The reset in the driver at init is not needed
anymore as the hwmod framework takes care of
reseting it.
Signed-off-by: Shubhrajyoti D
---
drivers/i2c/busses/i2c-omap.c | 73
1 files changed, 22 insertions(+
On 7/21/2011 4:39 PM, Shubhrajyoti D wrote:
The SYSC register should not accessed in the driver removing the
define from the driver.
Signed-off-by: Shubhrajyoti D
Looks good.
Acked-by: Santosh Shilimkar
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On 7/21/2011 4:39 PM, Shubhrajyoti D wrote:
Currently restore is done always.
Adding conditional restore. The restore is done only if the context is lost.
Minor comment. You may want to say 'i2c register restore'
instead of just 'restore'
Signed-off-by: Shubhrajyoti D
o
Keerthy,
On 7/21/2011 4:49 PM, J, KEERTHY wrote:
Hello Russel,
MADC stands for monitoring ADC. It is part of TWL4030 power IC.
TWL4030 is only on OMAP3 and hence not applicable for OMAP4.
The driver is split accross mfd and hwmon. Generic ADC
reading part is in mfd and exposing the individual
+ Benoit
On 7/27/2011 11:50 AM, Archit Taneja wrote:
Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The Latest
TRM mentions the correct fields in the register.
You can mention the TRM version instead of 'latest'
Latest is very much relative :)
Signed-off-by: Archit Tan
decreasing order of the field's end bit.
Thanks for the update.
Acked-by: Santosh Shilimkar
.../include/mach/ctrl_module_pad_core_44xx.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
b/arc
Tomi,
On 8/1/2011 11:31 AM, Tomi Valkeinen wrote:
On Sat, 2011-07-09 at 18:30 -0600, Paul Walmsley wrote:
Hi Santosh,
On Sat, 9 Jul 2011, Santosh Shilimkar wrote:
Sorry for not closing the loop on this thread but I thought Tomi
root-caused the DSS timeout issue to incorrect reset sequence of
+ Tero
On Tuesday 24 April 2012 03:20 PM, Jean Pihet wrote:
> Hi Grazvydas, Kevin,
>
> I did some gather some performance measurements and statistics using
> custom tracepoints in __omap3_enter_idle.
> All the details are at
> http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measur
controller
driver.
Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Cc: Greg KH
---
include/memory/jedec_ddr.h | 175
mainline yet.
Discussions with Santosh Shilimkar
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
did the initial code snippet for thermal
handling.
Testing:
- The driver is tested on OMAP4430 SDP.
- The driver in a slightly adapted form is also tested on OMAP5.
- Since
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Cc: Greg KH
---
drivers/memory/emif.c | 148 +
1 files
From: Aneesh V
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to
change handling needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from
also takes care of going back to nominal settings
when temperature falls back to nominal levels.
Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Cc: Greg KH
From: Aneesh V
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by
: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilim...@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Cc: Greg KH
---
Documentation/memory-devices/ti-emif.txt | 57 ++
drivers/Kconfig
Greg,
On Monday 23 April 2012 08:14 PM, Shilimkar, Santosh wrote:
> On Mon, Apr 23, 2012 at 7:57 PM, Greg KH wrote:
>> On Mon, Apr 23, 2012 at 04:34:46PM +0530, Shilimkar, Santosh wrote:
>>> Afzal,
>>>
>>> On Mon, Apr 23, 2012 at 4:26 PM, Mohammed, Afzal wrote:
Hi Aneesh,
On Fri,
) defined in this series should be
called omap4plus_*() or similar considering they can
be directly used on OMAP5 devices too.
Otherwise FWIW,
Reviewed-tested-by: Santosh Shilimkar
Regards
santosh
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To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the
Greg,
On Wednesday 02 May 2012 10:46 AM, Greg KH wrote:
> On Fri, Apr 27, 2012 at 05:54:02PM +0530, Santosh Shilimkar wrote:
>> Add a driver for the EMIF SDRAM controller used in Texas Instrument SoCs
>>
>> EMIF is an SDRAM controller that supports, based on its revision,
>
+: Add prm and cm base init function.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Makefile
ARM: OMAP4: Remove un-used WakeupGen register defines.
ARM: OMAP: dma: Make use of cpu_class_is_omap2
Since OMAP4 code base now makes use of OMAP4 specific PRCM functions,
cm2xxx_3xxx.c need not be compiled for OMAP4 only builds.
Signed-off-by: Santosh Shilimkar
Cc: Paul Walmsley
---
arch/arm/mach-omap2/Makefile |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/arch
Current OMAP code doesn't use any of the OMAP_WKG_ENB_SECURE_*
registers.
So remove those defines.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |8
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/in
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Makefile | 160 -
1 files changed, 78 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 56ed62e..669e2b1 100644
--- a/arch/arm/mach-omap2
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need to patch
the file for any future OMAP2+ devices.
In long run, all these attributes should come from hwmod dev_attr based
on DMA IP version.
Signed-off-by: Santosh Shilimkar
EMIF, GMPC and DMM driver can ioremap() the address
space as part of driver intialisation and there is
no need to have static IO mapping for them.
Hence remove the un-used static IP space and let
the respective drivers manage it as part if driver
init.
Signed-off-by: Santosh Shilimkar
---
arch
All OMAP2PLUS arch based machines makes use of mach-omap2 directory.
So just add one entry so that there is no need to patch this file
for any OMAP2+ devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/Makefile |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch
Signed-off-by: R Sricharan
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/cminst44xx.c | 28 ++--
arch/arm/mach-omap2/common.c |1 +
arch/arm/mach-omap2/common.h |1 +
arch/arm/mach-omap2/prcm-common.h | 13 +
arch/arm/mach-omap2
On Friday 27 April 2012 07:43 PM, Tarun Kanti DebBarma wrote:
> This cleanup got missed while implementing following:
> 25db711 gpio/omap: Fix IRQ handling for SPARSE_IRQ
> 384ebe1 gpio/omap: Add DT support to GPIO driver
>
> Cc: Kevin Hilman
> Cc: Tony Lindgren
> Cc: Sa
t;
> Cc: Kevin Hilman
> Cc: Tony Lindgren
> Cc: Santosh Shilimkar
> Cc: Cousson, Benoit
> Cc: Grant Likely
> Signed-off-by: Tarun Kanti DebBarma
> ---
> arch/arm/mach-omap2/gpio.c |2 ++
> arch/arm/plat-omap/include/plat/gpio.h |2 ++
> drivers/gp
store correctly in
> *_runtime_resume(), the bank->workaround_enabled check is
> moved after context restore. Otherwise, it would prevent
> context restore when bank->enabled_non_wakeup_gpios is 0.
>
> Cc: Kevin Hilman
> Cc: Tony Lindgren
> Cc: Santosh Shilimkar
> Cc: Cousson, Be
o:
> OMAP2+ platforms: OMAP2430SDP, OMAP3430SDP, OMAP4430SDP
> OMAP1: Bootup test on OMAP1710SDP.
>
> Cc: Kevin Hilman
> Cc: Tony Lindgren
> Cc: Santosh Shilimkar
> Cc: Cousson, Benoit
> Cc: Grant Likely
> Tarun Kanti DebBarma (8):
> gpio/omap: remove virtual
On Friday 04 May 2012 05:33 AM, Greg KH wrote:
> On Thu, May 03, 2012 at 06:38:23PM -0400, Paul Gortmaker wrote:
>> On Fri, Apr 27, 2012 at 8:24 AM, Santosh Shilimkar
>> wrote:
>>> Add a driver for the EMIF SDRAM controller used in Texas Instrument SoCs
>>
>> H
On Saturday 05 May 2012 04:25 AM, Tony Lindgren wrote:
> * R Sricharan [120503 00:30]:
>> --- a/arch/arm/mach-omap2/omap-hotplug.c
>> +++ b/arch/arm/mach-omap2/omap-hotplug.c
>> @@ -17,8 +17,10 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #include
>> +#include
>>
>> #in
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> The series adds minimal OMAP5 support.
> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> hence large part of the peripherals are re-used.
>
> OMAP5432
debug console etc.
Signed-off-by: R Sricharan
Signed-off-by: Santosh Shilimkar
Cc: Russell King
Cc: Catalin Marinas
---
arch/arm/boot/compressed/head.S |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed
-omap-dev.git
for_3.5/omap_misc_cleanup
R Sricharan (1):
ARM: OMAP2+: dma: Define dma capabilities register bitfields and use them.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Mak
On Tuesday 08 May 2012 04:33 AM, Tony Lindgren wrote:
> * Santosh Shilimkar [120502 02:51]:
>> This series has some miscellianeous clean up patches which help to add future
>> OMAP2+ device support with bit less changes. It is a preparatory series for
>> adding minimal OMAP5
On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
> * Santosh Shilimkar [120507 02:53]:
>> Tony,
>>
>> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
>>> The series adds minimal OMAP5 support.
>>> OMAP5430 has a dual core Cortex-A15 based MPU subsy
On Tuesday 08 May 2012 06:17 PM, Will Deacon wrote:
> Hello,
>
> On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
>> From: Santosh Shilimkar
>>
>> Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
>> are runtime checked using cp
en domain is Manager.
>>
>> This can lead to accesses to non-accessible address regions leading
>> to various interconnect violations. The issue is observed on OMAP5.
>>
>> This patch tries to fix the issue by ensuring that all regions
>> are marked as a cl
On Tuesday 08 May 2012 07:53 PM, Catalin Marinas wrote:
> On Tue, May 08, 2012 at 03:20:43PM +0100, Santosh Shilimkar wrote:
>> On Tuesday 08 May 2012 07:46 PM, Catalin Marinas wrote:
>>> On Tue, May 08, 2012 at 03:01:57PM +0100, Shilimkar, Santos
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
> From: Jon Hunter
>
> For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
> following transition modes ...
>
> NO_SLEEP (0x0) - A clock domain sleep transition is never initiated,
>irrespective of the hard
Benoit,
On Wednesday 09 May 2012 04:28 PM, Cousson, Benoit wrote:
> Hi Kevin and Jon,
>
> On 5/8/2012 11:22 PM, Kevin Hilman wrote:
>> Jon Hunter writes:
>>
>>> Hi Benoit,
>>>
>>> On 05/08/2012 06:01 AM, Cousson, Benoit wrote:
>>>
>>> [...]
>>>
>>> P.S. Please note there is also already a di
ue.
>>>
>>> I'll sort out a patch later today for this.
>> Great.
>
> This works for my 4430SDP board. I haven't booted it on anything else yet.
> Please can you check that this solves the issue for you? Thanks.
>
Yes it does.
Are you planning to m
On Thursday 10 May 2012 02:23 PM, Russell King - ARM Linux wrote:
> On Thu, May 10, 2012 at 12:41:35PM +0530, Santosh Shilimkar wrote:
>> Are you planning to merge below patch as is or split
>> the patch like 1) Refactoring 2) ARMv7 fix
>
> I don't see any point in spl
On Thursday 10 May 2012 05:18 PM, Roger Quadros wrote:
> On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
>> On Thu, May 10, 2012 at 5:06 PM, Roger Quadros wrote:
>>> Hi,
>>>
>>> On 05/03/2012 10:26 AM, R Sricharan wrote:
>>>> From: Santosh
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
> Santosh,
>
> Tero Kristo writes:
>
>> From: Santosh Shilimkar
>>
>> GIC distributor control register has changed between CortexA9 r1pX and
>> r2pX. The Control Register secure banked version is now
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
> On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
>> Santosh,
>>
>> Tero Kristo writes:
>>
>>> From: Santosh Shilimkar
>>>
>>> GIC distributor control register has c
Tero,
On Monday 14 May 2012 03:33 PM, Tero Kristo wrote:
> From: Santosh Shilimkar
>
> GIC distributor control register has changed between CortexA9 r1pX and
> r2pX. The Control Register secure banked version is now composed of 2
> bits:
> bit 0 == Secure Enable
>
+ Tarun for any comments
On Wednesday 16 May 2012 05:05 AM, Jon Hunter wrote:
> From: Jon Hunter
>
> In order to migrate the dmtimer driver to support device-tree I found that it
> was first necessary to clean-up the timer platform data. The goal of this
> series is to simplify the timer platfor
Jean,
On Tuesday 08 May 2012 02:10 PM, Jean Pihet wrote:
> Paul,
>
> On Mon, May 7, 2012 at 11:28 AM, Paul Walmsley wrote:
>> Hi
>>
>> On Wed, 18 Apr 2012, jean.pi...@newoldbits.com wrote:
>>
>>> From: Jean Pihet
>>>
>>> Introduce functional (or logical) states for power domains and the
>>> API
, and
set the irq to allow the clockevent core to determine the affinity of the
timer.
Signed-off-by: Colin Cross
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/timer.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach
Kevin Hilman (1):
ARM: OMAP4: CPUidle: add synchronization for coupled idle states
Santosh Shilimkar (3):
ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
ARM: OMAP4: CPUidle: Use coupled cpuidle states to implement SMP
cpuidle.
ARM: OMAP4: CPUidle: Open broadcast cloc
dcast
mode was also broken. This change fixes both the periodic/oneshot broadcast
modes.
Discussion thread :
https://lkml.org/lkml/2012/4/9/13
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/cpuidle44xx.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
state enter method can return.
In addition, cpuidle_coupled_parallel_barrier() is used to ensure the
clearing of the 'done' flag is synchronized on all CPUs.
Signed-off-by: Kevin Hilman
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/cpuidle44xx.c | 22 +
d Colin Cross on the suggestions/fixes
on the intermediate version of this patch.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2/cpuidle44xx.c | 112 ++---
2 files changed, 67 insertions(+), 46 deletions(-)
dif
Jean,
On Monday 21 May 2012 07:55 PM, Shilimkar, Santosh wrote:
> Jean,
>
> On Mon, May 21, 2012 at 7:23 PM, Jean Pihet wrote:
>> Hi Santosh,
>>
>> On Thu, May 17, 2012 at 12:04 PM, Santosh Shilimkar
>> wrote:
[...]
>> What do you think?
>>
>
Tony,
Here is the EMIF driver DT support which was kept on hold for the driver
to get merged. The series has been already reviewed on the list.
This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and ot
Cousson
Reviewed-by: Grant Likely
Tested-by: Lokesh Vutla
Signed-off-by: Aneesh V
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++
.../devicetree/bindings/lpddr2/lpddr2
: Santosh Shilimkar
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4-sdp.dts | 13 ++
arch/arm/boot/dts/omap4.dtsi | 18
4 files changed, 111
Reviewed-by: Grant Likely
Tested-by: Lokesh Vutla
Signed-off-by: Aneesh V
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 file changed, 55 insertions(+)
create mode 100644
From: Aneesh V
Device tree support for the EMIF driver.
Reviewed-by: Benoit Cousson
Reviewed-by: Grant Likely
Tested-by: Lokesh Vutla
Signed-off-by: Aneesh V
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar
Cc: Greg Kroah-Hartman
---
drivers/memory
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it to newly created drivers/bus.
Cc: Arnd Bergmann
Cc: Tony Lindgren
Tested-by: Lokesh Vutla
Signed-off-by: Santosh Shilimkar
---
Patch just moves OMAP interconnect drivers as is to
...@github.com:SantoshShilimkar/linux.git for_3.7/omap5_arch_timer
for you to fetch changes up to 3c7c5dab44d6c8861bc86dab924353d8d40344f8:
ARM: OMAP5: Enable arch timer support (2012-09-19 13:00:37 +0530)
Santosh Shilimkar (2):
ARM: OMAP: Add
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based on top of current linux next +
kevin's cpufreq fixes.
Have scann
On Monday 08 October 2012 02:22 PM, Santosh Shilimkar wrote:
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based on
On Thursday 11 October 2012 01:41 PM, Benoit Cousson wrote:
Hi Lokesh,
On 10/11/2012 08:16 AM, Lokesh Vutla wrote:
+ devicetree-discuss
Hi Benoit,
On Wednesday 10 October 2012 08:31 PM, Benoit Cousson wrote:
On 10/10/2012 02:05 PM, Lokesh Vutla wrote:
Device tree data for the EMIF sdram con
(-22)
twd_local_timer_register failed -22
The right fix is to not add any base, as it is a local
timer. For the OMAP44XX_IRQ_LOCALWDT we had defined earlier
there are no users, so no need to fix that.
Reported-by: Russell King
Signed-off-by: Tony Lindgren
Acked-by: Santosh Shilimkar
---
Thanks for the fix Lokesh. Looks fine to me.
Acked-by: Santosh Shilimkar
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Tero, paul,
On Thursday 18 October 2012 02:07 PM, Tero Kristo wrote:
On Thu, 2012-10-18 at 06:48 +, Paul Walmsley wrote:
On Thu, 18 Oct 2012, Paul Walmsley wrote:
Here are some basic OMAP test results for Linux v3.7-rc1.
Logs and other details at http://www.pwsan.com/omap/testlogs/test_v3
work Paul !!
This series and part2 both looks good to me.
Sorry for not being able to help in some of these clean-ups
because of other work priorities as talked at LPC.
Feel free to add my ack for the whole series if you need one.
Acked-by: Santosh Shilimkar
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kko for finding this.
Acked-by: Santosh Shilimkar
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On 4/16/2011 9:21 PM, Tarun Kanti DebBarma wrote:
In driver probe use sys_timer_reserved to identify which all timers
have already been used for clocksource and clockevent. Mark all those
timers as reserved so that no one else can use them.
Signed-off-by: Tarun Kanti DebBarma
---
arch/arm/plat
On 4/21/2011 1:12 AM, Paul Walmsley wrote:
Hi Rajendra, Santosh,
just FYI I just observed this happening without the clockdomain patch, and
tracked this down. It seems that there is an intermittent
problem with the OMAP L3 bus code. On the 35xx BeagleBoard here, it
occasionally hangs after po
Tony,
On 4/4/2011 3:17 PM, Santosh Shilimkar wrote:
On 4/4/2011 2:42 PM, Russell King - ARM Linux wrote:
[]
Thanks for pointing out this. I see Will's commit on this
one "29a38193"
Here is the updated patch as you suggested.
Are you considering this patch and another
x27;t go through L2X0 write
buffer.
A DSB before writel_relaxed() in gic_raise_softirq() is added to be
compliant with the Barrier Litmus document - the mailbox scenario.
Signed-off-by: Santosh Shilimkar
Cc: Catalin Marinas
Cc: Will Deacon
---
Rebased on top of Will Deacon's &quo
Marc,
On 4/21/2011 12:38 AM, Marc Zyngier wrote:
Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.
Tested on a Pandaboard.
Cc: Tony Lindgren
Cc: Santosh Shilimkar
Signed-off-by: Marc Zyngier
---
Have reviewed and tested your series along with
OMAP
Tarun,
On 4/25/2011 3:11 PM, DebBarma, Tarun Kanti wrote:
In driver probe use sys_timer_reserved to identify which all timers
have already been used for clocksource and clockevent. Mark all those
timers as reserved so that no one else can use them.
Signed-off-by: Tarun Kanti DebBarma
---
Change
On 4/16/2011 9:20 PM, Tarun Kanti DebBarma wrote:
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver.
In addition, capability attribute of each of the ti
Tarun,
On 4/16/2011 9:21 PM, Tarun Kanti DebBarma wrote:
Make plat-omap/dmtimer.c a normal driver. It is moved to drivers/misc
as timer-omap.c and the corresponding header file has been moved to
include/linux as timer-omap.h. Files which included plat/dmtimer.h
are changed to include linux/timer
On 4/29/2011 2:56 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihet
The cpuidle states settings can be overriden by some board-
specific settings, by calling omap3_pm_init_cpuidle.
Remove the 3430SDP specific states settings registration
since the figures are identical to the default ones (i
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