On Thu, 2012-02-16 at 14:13 +0530, Shilimkar, Santosh wrote:
Tero,
On Thu, Feb 16, 2012 at 2:09 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-02-15 at 11:35 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
Some clockdomains can't support manual domain transitions
Hi,
Following changes compared to previous version:
- updated to work with mainline
- added acked-by Samuel Ortiz to patch 4 MFD part (no changes done to that
part of code since previous version)
- changed min_uV parameter name from patch 4/5 to target_uV
Tested with omap3 beagle: changed +
OMAP3 uses the default settings for VDD1 channel, otherwise the settings will
overlap with VDD2 and attempting to modify VDD1 voltage will actually change
VDD2 voltage.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc3xxx_data.c |1 +
1 files changed, 1 insertions(+), 0
Beagleboard rev-c4 has a speed sorted OMAP3530 chip which can run at 720MHz.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c | 29 +
arch/arm/mach-omap2/opp3xxx_data.c |4
2 files changed, 33 insertions(+), 0
VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used
to control MPU/IVA voltage, and VDD2 is used for CORE. These regulators
are needed by DVFS.
Voltage ranges for VDD1 and VDD2 are taken from twl4030/twl5030 data manual.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm
VDD1 and VDD2 now use voltage processor for controlling the regulators.
This is done by passing additional voltdm data during the regulator init.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/twl-common.c | 33 +++--
1 files changed, 31
, a data pointer for these, and
the previously used features bitmask.
Signed-off-by: Tero Kristo t-kri...@ti.com
Acked-by: Samuel Ortiz sa...@linux.intel.com [for the MFD part]
Cc: Mark Brown broo...@opensource.wolfsonmicro.com
Cc: Liam Girdwood l...@ti.com
---
drivers/mfd/twl-core.c
On Thu, 2012-02-16 at 15:27 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 2:27 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-02-15 at 11:37 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
Attempting this will cause problems especially with off-mode enabled
On Thu, 2012-02-16 at 15:15 +0200, Tero Kristo wrote:
On Thu, 2012-02-16 at 15:27 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 2:27 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-02-15 at 11:37 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes
On Thu, 2012-02-16 at 21:15 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 8:53 PM, Tero Kristo t-kri...@ti.com wrote:
On Thu, 2012-02-16 at 15:15 +0200, Tero Kristo wrote:
On Thu, 2012-02-16 at 15:27 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 2:27 PM, Tero Kristo t
On Thu, 2012-02-16 at 09:31 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
On Thu, 2012-02-16 at 21:15 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 8:53 PM, Tero Kristo t-kri...@ti.com wrote:
On Thu, 2012-02-16 at 15:15 +0200, Tero Kristo wrote:
On Thu
On Thu, 2012-02-16 at 11:36 -0800, Kevin Hilman wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
Hi Kevin,
On Thu, Feb 16, 2012 at 11:20 AM, Kevin Hilman khil...@ti.com wrote:
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 8a36342..140c032 100644
Non-smp platforms don't have local timer support, but the twd_cpufreq_init
only checks for IS_ERR during init. Check against null also, to avoid
crashes during cpufreq transitions on non-smp platforms.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/kernel/smp_twd.c |2 +-
1 files
On Thu, 2012-02-16 at 12:23 -0600, Menon, Nishanth wrote:
On Thu, Feb 16, 2012 at 04:27, Tero Kristo t-kri...@ti.com wrote:
VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used
to control MPU/IVA voltage, and VDD2 is used for CORE. These regulators
are needed by DVFS
On Fri, 2012-02-17 at 16:17 +0530, Shilimkar, Santosh wrote:
On Fri, Feb 17, 2012 at 4:04 PM, Tero Kristo t-kri...@ti.com wrote:
Non-smp platforms don't have local timer support, but the twd_cpufreq_init
only checks for IS_ERR during init. Check against null also, to avoid
crashes during
Hi,
Just some cosmetic changes compared to previous version:
- dropped out '[patchv9 4/5] regulator: twl4030: add support for external
controller', as this was accepted for merge by Mark
- changed names of regulators from VDD1 / VDD2 - vdd_mpu_iva / vdd_core
in patch 3
- added document codes
OMAP3 uses the default settings for VDD1 channel, otherwise the settings will
overlap with VDD2 and attempting to modify VDD1 voltage will actually change
VDD2 voltage.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc3xxx_data.c |1 +
1 files changed, 1 insertions(+), 0
Beagleboard rev-c4 has a speed sorted OMAP3530 chip which can run at 720MHz.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c | 29 +
arch/arm/mach-omap2/opp3xxx_data.c |4
2 files changed, 33 insertions(+), 0
VDD1 and VDD2 now use voltage processor for controlling the regulators.
This is done by passing additional voltdm data during the regulator init.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/twl-common.c | 33 +++--
1 files changed, 31
: TWL5030 ES1.2 Data Manual rev E
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/twl-common.c | 36
1 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index
Hi,
This set applies on top of the pwrdm / clkdm / voltdm usecounting patch
set I sent last week (see:
http://www.spinics.net/lists/linux-omap/msg64670.html):
Following changes done compared to previous version.
- split out the basic usecounting support as its own set (see above)
- added lots
routines to set a cap if the voltage is out of
reach for the PMIC.
Reported-by: Jon Hunter jon-hun...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 17
These are now called vddmin and vddmax, as these fields will be used
globally for selecting voltage ranges for a pmic channel, and not
only for voltage processor.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 27 ++-
arch/arm/mach-omap2
domain code is changed to use these.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_twl.c| 25 ---
arch/arm/mach-omap2/vc.c | 241 ++---
arch/arm/mach-omap2/vc.h |8 +-
arch/arm/mach
This is applied when PMIC is entering or leaving a sleep mode.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/voltage.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 940a0d6
Both startup and shutdown take 500us at maximum, value taken from
TWL6030 data manual.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_twl.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2
This contains startup and shutdown times for the oscillator. By default
use ULONG_MAX. Oscillator setup is used for calculating and setting up
latencies for sleep modes that disable oscillator.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm.c | 27
Now we select the vddmin and vddmax values based on both pmic and
voltage processor data, this allows usage of different power ICs.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vp.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach
We now use the previously defined oscillator setup / shutdown times
to calculate the register values for CLKSETUP.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc.c | 62 ++
1 files changed, 62 insertions(+), 0 deletions
As voltdm-pmic now contains startup and shutdown times for PMIC, use
these for calculating the fields in the PMICSETUPTIME register.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch
Based on the oscillator datasheet for this device.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
Beagleboard rev-c4 has a speed sorted OMAP3530 chip which can run at 720MHz.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c | 29 +
arch/arm/mach-omap2/opp3xxx_data.c |4
2 files changed, 33 insertions(+), 0
Voltage code will now enable / disable auto_ret / auto_off dynamically
according to the voltagedomain usecounts. This is accomplished via
the usage of the voltdm callback functions for sleep / wakeup.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc.c | 139
OMAP3 uses the default settings for VDD1 channel, otherwise the settings will
overlap with VDD2 and attempting to modify VDD1 voltage will actually change
VDD2 voltage.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/vc.c |5 -
arch/arm/mach-omap2
If we are switching the state of an idle powerdomain, we must wait for
the wakeup to complete before attempting to switch to the new state,
otherwise the powerdomain may not be ready for the switch and will fail.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm.c |1 +
1
On Tue, 2012-02-21 at 14:53 +, Russell King - ARM Linux wrote:
On Tue, Feb 21, 2012 at 08:40:22AM -0600, Menon, Nishanth wrote:
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
These are now called vddmin and vddmax, as these fields will be used
globally for selecting
On Tue, 2012-02-21 at 16:00 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used
to control MPU/IVA voltage, and VDD2 is used for CORE. These regulators
are needed by DVFS.
Voltage ranges for VDD1 and VDD2
On Wed, 2012-02-22 at 14:37 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
On Thu, 2012-02-16 at 09:31 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
On Thu, 2012-02-16 at 21:15 +0530, Shilimkar, Santosh wrote:
On Thu, Feb 16, 2012 at 8:53 PM, Tero
On Wed, 2012-02-22 at 19:37 -0600, Menon, Nishanth wrote:
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
[...]
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 949938d..940a0d6 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm
controller.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Mark Brown broo...@opensource.wolfsonmicro.com
Cc: Liam Girdwood l...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Kevin Hilman khil...@ti.com
---
drivers/mfd/twl-core.c| 15 ++
drivers/regulator/twl
Hi,
This set adds core retention support on top of mainline. The set
also adds IO CHAIN wakeup capability for OMAP4, which is a nice feature
to have while trying suspend / resume with CSWR as it is quite difficult
to wake up the device without this.
Patch 6 might cause some stir, but this is
From: Rajendra Nayak rna...@ti.com
Remove the FIXME's in the suspend sequence since
we now intend to support system level RET support.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/pm44xx.c |6 --
1 files changed, 0
From: Rajendra Nayak rna...@ti.com
patch adds IO Daisychain support for OMAP4 as per section 3.9.4 in OMAP4430
Public TRM.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm44xx.c
Padlevel WKST bit in the first interrupt, module specific interrupt
handler will not triggered for the second time
Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Tero Kristo
From: Rajendra Nayak rna...@ti.com
With no driver handling DSP/TESLA, if brought out of reset, it stays
active and does not assert standby.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |1 +
1 files
Previous code used wrong instance for the interrupt register access.
Use the right one which is OCP_SOCKET.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prm44xx.c | 21 +++--
1 files changed, 11 insertions(+), 10 deletions
of irq_desc allocation scheme.
Once SPARSE_IRQ is enabled for OMAP kernel, this patch can be reverted.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prm_common.c | 14 +-
arch/arm/plat-omap/include/plat/irqs.h |6
On Tue, 2012-11-06 at 13:52 -0800, Kevin Hilman wrote:
Kevin Hilman khil...@deeprootsystems.com writes:
Tero Kristo t-kri...@ti.com writes:
Added similar PM errata flag support as omap3 has. This should be used
in similar manner, set the flags during init time, and check the flag
On Tue, 2012-11-06 at 13:19 -0800, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
Hi Kevin,
On Mon, 2012-11-05 at 14:23 -0800, Kevin Hilman wrote:
Hi Tero,
Tero Kristo t-kri...@ti.com writes:
Hi,
Changes compared to previous version:
- rebased on top of 3.7
by adding a minimal function back that disables the USB PHY during
boot.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Kishon Vijay Abraham I kis...@ti.com
Cc: Felipe Balbi ba...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap_phy_internal.c
to
me, thus for whole set:
Acked-by: Tero Kristo t-kri...@ti.com
On Tue, 2012-11-13 at 09:28 +0100, Peter Ujfalusi wrote:
Hello,
This series converts the twl-core to use regmap for IO towards the chip.
With the conversion to regmap IO we no longer need to allocate bigger buffer
for
writes.
I
Signed-off-by: Tero Kristo t-kri...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
I guess this commit will allow DSS to go to a lower power state. So what
might be happening is:
- After returning back from the lower power state, the DISPC base
address
On Thu, 2012-11-22 at 16:44 +0200, Tomi Valkeinen wrote:
On 2012-11-22 16:34, Tero Kristo wrote:
I guess you checked that DSS pwrdm is switching between RET and ON in
your setup?
Yes:
# cat /debug/pm_debug/count |grep dss
[ 35.356567] pwrdm state mismatch(l3init_pwrdm) 3 != 1
On Tue, 2012-11-27 at 14:21 +0200, Tomi Valkeinen wrote:
On 2012-11-27 13:56, Archit Taneja wrote:
On Tuesday 27 November 2012 04:53 PM, Tomi Valkeinen wrote:
Hmm, well this feels like a hack. DISPC driver doesn't know how the DSS
modules are arranged, which module belongs to which power
Hi Paul,
I just tested this + next two powerdomain series from you on omap3beagle
+ omap4panda boards. This set seems fine, for the code I don't have any
major complaints either, thus you can add my ack if you like. I'll send
comments for the next two sets soon also.
-Tero
On Sat, 2012-12-08 at
Hi Paul / Jean,
On Wed, 2012-12-12 at 11:33 +0100, Jean Pihet wrote:
clip
+/**
+ * _match_pwrst: determine the closest supported power state
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum (i.e.
Hi Paul,
On Sun, 2012-12-09 at 10:53 -0700, Paul Walmsley wrote:
clip
@@ -112,24 +112,26 @@ static void omap3_core_restore_context(void)
static void omap3_save_secure_ram_context(void)
{
u32 ret;
- int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+ int
, as several power domains can't idle
after this anymore (they get programmed to ON state due to CSWR not
being supported on them.) Following patch fixes this problem (applies on
top of the whole set):
=
From: Tero Kristo t-kri...@ti.com
Date: Wed, 2 Jan 2013 18:05:42 +0200
Subject
Hi Paul,
On Sun, 2012-12-09 at 10:53 -0700, Paul Walmsley wrote:
From: Jean Pihet jean.pi...@newoldbits.com
The PM code uses some counters to keep track of the power domains
transitions, in order to provide the information to drivers (in
pwrdm_get_context_loss_count) and to expose the
Hi Paul,
As mentioned with the previous set, I have tested this one also on
omap3beagle + omap4panda boards. omap4 has one regression caused by this
set, as commented on the patch itself. Also posted a couple of other
minor comments. Other than that, you can consider this set as acked by
me.
quickly and don't have any comments to it.
-Tero
From: Tero Kristo t-kri...@ti.com
Date: Thu, 3 Jan 2013 20:07:27 +0200
Subject: [PATCH] ARM: OMAP4: PM: fix cpu0 statistics update during idle
Cpu0 PM counters do not update, as the cpu0 fpwrst is set to ON before
calling pwrdm_post_transition
This will save some power.
Signed-off-by: Tero Kristo tero.kri...@nokia.com
---
arch/arm/plat-omap/dmtimer.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf..949becc 100644
--- a/arch/arm/plat-omap
This saves some power. OMAP4 version should check for GPT module ID, as
autoidle is only supported on a subset of these.
Signed-off-by: Tero Kristo tero.kri...@nokia.com
---
arch/arm/plat-omap/dmtimer.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat
On Wed, 2013-01-30 at 17:15 +, Paul Walmsley wrote:
Hi Tero et al.,
On Tue, 22 Jan 2013, Paul Walmsley wrote:
As we've discussed, there are known bootloader dependencies with the OMAP4
PM retention idle code, introduced in v3.8. Boards booted with u-boot
versions even as recent
Hi Paul and Mike,
It looks like we need to start putting more effort into this clock data
move now, as this is starting to hinder us on several fronts.
Unfortunately I still can't personally participate in this work myself
as I am now allocated to some hwmod related work, but Eduardo should
have
, FSUSB
per discussion with Tero Kristo
- Likely dependent on the bootloader version
- fails with 2012.07-00136-g755de79
Do you still see the issue after upgrading the boot-loader version ?
I think you should definitely upgrade your bootloader, the old one you
are using is prone
Hi,
This is an RFC version of the clock data move under drivers/clk.
Tested under 3.8 and boots fine, but don't try this out unless
you are experimental sort (I quickly tried with 3.9-rc3 and it failed to
boot with that.)
The approach taken here has minimal impact on the clock data
and should
Clock header register declarations were previously converting
addresses to direct pointers. This doesn't work with an ioremapping
driver, so these are changed into { module, offset } tuples.
These are parsed by the driver into actual register addresses.
Signed-off-by: Tero Kristo t-kri...@ti.com
This patch adds basic infrastructure support for registering clocks
under common clock framework. This patch is done in preparation for
moving clock data from arch/arm/mach-omap2/ folder under /drivers/clk/omap.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Mike Turquette mturque...@linaro.org
Modifies the omap4 clock init code to support the new clock
registration method.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/omap/cclock44xx_data.c | 52 ++-
1 files changed, 21 insertions(+), 31 deletions
in the clk_lookup will still succeed despite
this.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/clkdev.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..05b01a1
On Thu, 2013-03-21 at 11:50 -0700, Mike Turquette wrote:
Quoting Tero Kristo (2013-03-21 10:35:40)
This patch adds basic infrastructure support for registering clocks
under common clock framework. This patch is done in preparation for
moving clock data from arch/arm/mach-omap2/ folder under
On Fri, 2013-03-22 at 10:58 +0530, Rajendra Nayak wrote:
Tero,
On Thursday 21 March 2013 11:05 PM, Tero Kristo wrote:
Hi,
This is an RFC version of the clock data move under drivers/clk.
Tested under 3.8 and boots fine, but don't try this out unless
you are experimental sort (I
On Fri, 2013-03-22 at 09:47 -0700, Mike Turquette wrote:
Quoting Tero Kristo (2013-03-22 01:39:08)
On Thu, 2013-03-21 at 11:50 -0700, Mike Turquette wrote:
Quoting Tero Kristo (2013-03-21 10:35:40)
This patch adds basic infrastructure support for registering clocks
under common clock
On Tue, 2013-03-26 at 18:43 +, Paul Walmsley wrote:
Hi.
On Tue, 19 Mar 2013, Tero Kristo wrote:
I think you should definitely upgrade your bootloader, the old one you
are using is prone to cause trouble due to bugs it has, and we have no
simple way to workaround the issues
On Thu, 2013-04-04 at 16:42 +0530, Santosh Shilimkar wrote:
+ Tero and few more TI folks,
Hi,
Added some comments below.
On Thursday 04 April 2013 01:12 AM, Paul Walmsley wrote:
Hi Santosh
On Wed, 3 Apr 2013, Santosh Shilimkar wrote:
Thes patchset has already missed last couple
Hi Mike,
On Mon, 2013-06-03 at 23:39 -0700, Mike Turquette wrote:
This is a very incomplete conversion of a handful of OMAP4 PRCM clocks
from the statically defined clock data in
arch/arm/mach-omap2/cclock44xx_data.c to a new dts file in
arch/arm/boot/dts/omap4-clocks.dtsi.
I gave a quick
On Fri, 2013-06-07 at 14:31 +0530, Sricharan R wrote:
On Friday 07 June 2013 01:22 PM, Paul Walmsley wrote:
cc Benoît
On Fri, 7 Jun 2013, Sricharan R wrote:
I used autogen to remove the data, but some of the data were not in sync
with the mainline .(like abe, dss, aess, context
clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clkdev.c | 32
1 file changed, 32 insertions
of_property_read_u8 does not work properly because of endianess problem
with its current implementation, and this causes it to always return
0 with little endian architectures. Instead, use property_read_u32
until this is fixed.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk
Hi,
This set converts the OMAP4 clock data to device tree format.
This set also fixes a couple of problems detected in the basic clock
devicetree code (patches 2 3), and adds some generic support functions
for the transition phase when all the drivers are not fully devicetree
compliant (see
Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.h | 150
This node adds support for a clock node which allows control to the
clockdomain enable / disable.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/omap/Makefile |2 +-
drivers/clk/omap/clk.c|1 +
drivers/clk/omap/gate.c | 88
clock names.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 39 +++
arch/arm/mach-omap2/clock.h | 16
2 files changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap4-clocks.dtsi | 1704 +++
arch/arm/boot/dts/omap4.dtsi|2 +
2 files changed, 1706
Turquette.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/Makefile |1 +
drivers/clk/omap/Makefile |1 +
drivers/clk/omap/clk.c| 44
include/linux/clk/omap.h | 24
OMAP clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo t
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/omap/Makefile |2 +-
drivers/clk/omap/clk.c|1 +
drivers/clk/omap/dpll.c | 307
The existing implementation had a couple of bugs:
1) table_size was attempted to read improperly, it has to be calculated
from the 'len' parameter of a property
2) Reading the integer entries from the table was reading only first
two entries of the DT data
Signed-off-by: Tero Kristo t-kri
On 06/19/2013 04:30 PM, Nishanth Menon wrote:
On 16:19-20130619, Tero Kristo wrote:
snip
diff --git a/arch/arm/boot/dts/omap4-clocks.dtsi
b/arch/arm/boot/dts/omap4-clocks.dtsi
new file mode 100644
index 000..b420d8a
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-clocks.dtsi
[...]
+/* XXX
On 06/21/2013 04:24 AM, Stephen Boyd wrote:
On 06/19/13 06:19, Tero Kristo wrote:
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..70608db 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -106,6 +106,8
On 06/21/2013 10:32 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [130619 06:25]:
Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.
Do you
On 06/21/2013 10:25 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [130619 06:25]:
Now that the OMAP4 PRCM clock data has been converted to device tree
representation, it is no longer needed as static clock data. OMAP4
clock init routine is also changed to register DT clocks first
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap4-clocks.dtsi | 1692 +++
arch/arm/boot/dts/omap4.dtsi|2 +
2 files changed, 1694
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/omap/Makefile |2 +-
drivers/clk/omap/clk.c|1 +
drivers/clk/omap/dpll.c | 307
Hi,
Changes compared to previous version:
PATCH 2 - removed some unnecessary headers + module defs
- added Mike under copyright
PATCH 4 - fixed the copyright in the header file
PATCH 8 - removed a few incorrect comments from the data file
- moved /include/ for the clock DT file
Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.h | 150
clock names.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 39 +++
arch/arm/mach-omap2/clock.h | 16
2 files changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index
This node adds support for a clock node which allows control to the
clockdomain enable / disable.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/omap/Makefile |2 +-
drivers/clk/omap/clk.c|1 +
drivers/clk/omap/gate.c | 88
clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Russell King li...@arm.linux.org.uk
---
drivers/clk/clkdev.c | 32
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